Skip to content

Commit 00230e3

Browse files
committed
fix(cpus): workaround for Cortex-A78C erratum 2772121
Cortex-A78C erratum 2772121 is a Cat B erratum that applies to all revisions <=r0p2 and is still open. The workaround is to insert a dsb before the isb in the power down sequence. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9
1 parent e64a26a commit 00230e3

File tree

3 files changed

+47
-3
lines changed

3 files changed

+47
-3
lines changed

docs/design/cpu-specific-build-macros.rst

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,10 @@ For Cortex-A78C, the following errata build flags are defined :
357357
Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
358358
erratum is still open.
359359

360+
- ``ERRATA_A78C_2772121`` : This applies errata 2772121 workaround to
361+
Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
362+
This erratum is still open.
363+
360364
For Cortex-X1 CPU, the following errata build flags are defined:
361365

362366
- ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1

lib/cpus/aarch64/cortex_a78c.S

Lines changed: 35 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
2+
* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -117,13 +117,13 @@ func check_errata_2132064
117117
b cpu_rev_var_range
118118
endfunc check_errata_2132064
119119

120-
/* --------------------------------------------------------------------
120+
/* ----------------------------------------------------------
121121
* Errata Workaround for A78C Erratum 2242638.
122122
* This applies to revisions r0p1 and r0p2 of the Cortex A78C
123123
* processor and is still open.
124124
* x0: variant[4:7] and revision[0:3] of current cpu.
125125
* Shall clobber: x0-x17
126-
* --------------------------------------------------------------------
126+
* ----------------------------------------------------------
127127
*/
128128
func errata_a78c_2242638_wa
129129
/* Compare x0 against revisions r0p1 - r0p2 */
@@ -152,6 +152,31 @@ func check_errata_2242638
152152
b cpu_rev_var_range
153153
endfunc check_errata_2242638
154154

155+
/* ----------------------------------------------------------------
156+
* Errata Workaround for A78C Erratum 2772121.
157+
* This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
158+
* processor and is still open.
159+
* x0: variant[4:7] and revision[0:3] of current cpu.
160+
* Shall clobber: x0-x17
161+
* ----------------------------------------------------------------
162+
*/
163+
func errata_a78c_2772121_wa
164+
mov x17, x30
165+
bl check_errata_2772121
166+
cbz x0, 1f
167+
168+
/* dsb before isb of power down sequence */
169+
dsb sy
170+
1:
171+
ret x17
172+
endfunc errata_a78c_2772121_wa
173+
174+
func check_errata_2772121
175+
/* Applies to all revisions <= r0p2 */
176+
mov x1, #0x02
177+
b cpu_rev_var_ls
178+
endfunc check_errata_2772121
179+
155180
func check_errata_cve_2022_23960
156181
#if WORKAROUND_CVE_2022_23960
157182
mov x0, #ERRATA_APPLIES
@@ -215,6 +240,12 @@ func cortex_a78c_core_pwr_dwn
215240
mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
216241
orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
217242
msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
243+
#if ERRATA_A78C_2772121
244+
mov x15, x30
245+
bl cpu_get_rev_var
246+
bl errata_a78c_2772121_wa
247+
mov x30, x15
248+
#endif /* ERRATA_A78C_2772121 */
218249
isb
219250
ret
220251
endfunc cortex_a78c_core_pwr_dwn
@@ -237,6 +268,7 @@ func cortex_a78c_errata_report
237268
report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
238269
report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
239270
report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
271+
report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
240272
report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
241273

242274
ldp x8, x30, [sp], #16

lib/cpus/cpu-ops.mk

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -394,6 +394,10 @@ ERRATA_A78C_2376749 ?=0
394394
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
395395
ERRATA_A78C_2395411 ?=0
396396

397+
# Flag to apply erratum 2772121 workaround during powerdown. This erratum
398+
# applies to revisions r0p0, r0p1 and r0p2 of the A78C cpu. It is still open.
399+
ERRATA_A78C_2772121 ?=0
400+
397401
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
398402
# to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1.
399403
ERRATA_X1_1821534 ?=0
@@ -1062,6 +1066,10 @@ $(eval $(call add_define,ERRATA_A78C_2376749))
10621066
$(eval $(call assert_boolean,ERRATA_A78C_2395411))
10631067
$(eval $(call add_define,ERRATA_A78C_2395411))
10641068

1069+
# Process ERRATA_A78C_2772121 flag
1070+
$(eval $(call assert_boolean,ERRATA_A78C_2772121))
1071+
$(eval $(call add_define,ERRATA_A78C_2772121))
1072+
10651073
# Process ERRATA_X1_1821534 flag
10661074
$(eval $(call assert_boolean,ERRATA_X1_1821534))
10671075
$(eval $(call add_define,ERRATA_X1_1821534))

0 commit comments

Comments
 (0)