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Merge "fix(cpus): workaround for Cortex-A510 erratum 2684597" into integration
2 parents fc3bdab + aea4ccf commit 1678bbb

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‎docs/design/cpu-specific-build-macros.rst‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -669,7 +669,7 @@ For Cortex-A510, the following errata build flags are defined :
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
670670
r0p3 and r1p0, it is fixed in r1p1.
671671

672-
- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
672+
- ``ERRATA_A510_2347730``: This applies errata 2347730 workaround to
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Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
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r0p3, r1p0 and r1p1. It is fixed in r1p2.
675675

@@ -681,6 +681,10 @@ For Cortex-A510, the following errata build flags are defined :
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Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
682682
r0p3, r1p0, r1p1. It is fixed in r1p2.
683683

684+
- ``ERRATA_A510_2684597``: This applies erratum 2684597 workaround to
685+
Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
686+
r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
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684688
DSU Errata Workarounds
685689
----------------------
686690

‎lib/cpus/aarch64/cortex_a510.S‎

Lines changed: 41 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2022, ARM Limited. All rights reserved.
2+
* Copyright (c) 2023, Arm Limited. All rights reserved.
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
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*/
@@ -361,6 +361,45 @@ func check_errata_2666669
361361
b cpu_rev_var_ls
362362
endfunc check_errata_2666669
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364+
/* ------------------------------------------------------
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* Errata Workaround for Cortex-A510 Erratum 2684597.
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* This erratum applies to revision r0p0, r0p1, r0p2,
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* r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
368+
* is fixed in r1p3.
369+
* Shall clobber: x0-x17
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* ------------------------------------------------------
371+
*/
372+
.globl errata_cortex_a510_2684597_wa
373+
func errata_cortex_a510_2684597_wa
374+
mov x17, x30
375+
/* Ensure this errata is only applied to Cortex-A510 cores */
376+
jump_if_cpu_midr CORTEX_A510_MIDR, 1f
377+
b 2f
378+
379+
1:
380+
/* Check workaround compatibility. */
381+
mov x0, x18
382+
bl check_errata_2684597
383+
cbz x0, 2f
384+
385+
tsb csync
386+
2:
387+
ret x17
388+
endfunc errata_cortex_a510_2684597_wa
389+
/* ------------------------------------------------------
390+
* Errata Workaround for Cortex-A510 Erratum 2684597.
391+
* This erratum applies to revision r0p0, r0p1, r0p2,
392+
* r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
393+
* is fixed in r1p3.
394+
* Shall clobber: x0-x17
395+
* ------------------------------------------------------
396+
*/
397+
func check_errata_2684597
398+
/* Applies to revision < r1p3 */
399+
mov x1, #0x12
400+
b cpu_rev_var_ls
401+
endfunc check_errata_2684597
402+
364403
/* ----------------------------------------------------
365404
* HW will do the cache maintenance while powering down
366405
* ----------------------------------------------------
@@ -401,6 +440,7 @@ func cortex_a510_errata_report
401440
report_errata ERRATA_A510_2347730, cortex_a510, 2347730
402441
report_errata ERRATA_A510_2371937, cortex_a510, 2371937
403442
report_errata ERRATA_A510_2666669, cortex_a510, 2666669
443+
report_errata ERRATA_A510_2684597, cortex_a510, 2684597
404444
report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
405445

406446
ldp x8, x30, [sp], #16

‎lib/cpus/aarch64/runtime_errata.S‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
/*
2+
* Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
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*
4+
* SPDX-License-Identifier: BSD-3-Clause
5+
*/
6+
7+
#include <asm_macros.S>
8+
#include <cortex_a510.h>
9+
#include <cpu_macros.S>
10+
11+
/*
12+
* void apply_cpu_pwr_dwn_errata(void);
13+
*
14+
* This function applies various CPU errata during power down.
15+
*/
16+
.globl apply_cpu_pwr_dwn_errata
17+
func apply_cpu_pwr_dwn_errata
18+
mov x19, x30
19+
bl cpu_get_rev_var
20+
mov x18, x0
21+
22+
#if ERRATA_A510_2684597
23+
bl errata_cortex_a510_2684597_wa
24+
#endif
25+
26+
ret x19
27+
endfunc apply_cpu_pwr_dwn_errata

‎lib/cpus/cpu-ops.mk‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -745,6 +745,11 @@ ERRATA_A510_2371937 ?=0
745745
# to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2.
746746
ERRATA_A510_2666669 ?=0
747747

748+
# Flag to apply erratum 2684597 workaround during powerdown. This erratum
749+
# applies to revision r0p0, r0p1, r0p2, r0p3, r1p0, r1p1 and r1p2 of the
750+
# Cortex-A510 cpu and is fixed in r1p3.
751+
ERRATA_A510_2684597 ?=0
752+
748753
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
749754
# Applying the workaround results in higher DSU power consumption on idle.
750755
ERRATA_DSU_798953 ?=0
@@ -1407,6 +1412,10 @@ $(eval $(call add_define,ERRATA_A510_2371937))
14071412
$(eval $(call assert_boolean,ERRATA_A510_2666669))
14081413
$(eval $(call add_define,ERRATA_A510_2666669))
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1415+
# Process ERRATA_A510_2684597 flag
1416+
$(eval $(call assert_boolean,ERRATA_A510_2684597))
1417+
$(eval $(call add_define,ERRATA_A510_2684597))
1418+
14101419
#Process ERRATA_DSU_798953 flag
14111420
$(eval $(call assert_boolean,ERRATA_DSU_798953))
14121421
$(eval $(call add_define,ERRATA_DSU_798953))

‎lib/psci/aarch64/psci_helpers.S‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -124,6 +124,9 @@ endfunc psci_do_pwrup_cache_maintenance
124124
* -----------------------------------------------------------------------
125125
*/
126126
func psci_power_down_wfi
127+
#if ERRATA_A510_2684597
128+
bl apply_cpu_pwr_dwn_errata
129+
#endif
127130
dsb sy // ensure write buffer empty
128131
1:
129132
wfi

‎lib/psci/psci_lib.mk‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
#
2-
# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
2+
# Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
33
#
44
# SPDX-License-Identifier: BSD-3-Clause
55
#
@@ -21,7 +21,8 @@ PSCI_LIB_SOURCES := lib/el3_runtime/cpu_data_array.c \
2121
lib/psci/${ARCH}/psci_helpers.S
2222

2323
ifeq (${ARCH}, aarch64)
24-
PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
24+
PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S \
25+
lib/cpus/aarch64/runtime_errata.S
2526
endif
2627

2728
ifeq (${USE_COHERENT_MEM}, 1)

‎lib/psci/psci_private.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
2+
* Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
33
*
44
* SPDX-License-Identifier: BSD-3-Clause
55
*/
@@ -304,6 +304,9 @@ int psci_spd_migrate_info(u_register_t *mpidr);
304304
*/
305305
void prepare_cpu_pwr_dwn(unsigned int power_level);
306306

307+
/* This function applies various CPU errata during power down. */
308+
void apply_cpu_pwr_dwn_errata(void);
309+
307310
/* Private exported functions from psci_on.c */
308311
int psci_cpu_on_start(u_register_t target_cpu,
309312
const entry_point_info_t *ep);

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