diff --git a/docs/solutions/reference-designs/eval-ad4630/ad4630-16-eval-board.rst b/docs/solutions/reference-designs/eval-ad4630/ad4630-16-eval-board.rst new file mode 100644 index 00000000000..f90b66d1aa9 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad4630/ad4630-16-eval-board.rst @@ -0,0 +1,2 @@ +.. image:: https://wiki.analog.com/_media/resources/eval/section>resources/eval/ad4630-24-eval-board&showfooter=nofooter + :alt: section>resources/eval/ad4630-24-eval-board&showfooter=nofooter diff --git a/docs/solutions/reference-designs/eval-ad4630/ad4630-24-developer-guide.rst b/docs/solutions/reference-designs/eval-ad4630/ad4630-24-developer-guide.rst new file mode 100644 index 00000000000..286dc24cd11 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad4630/ad4630-24-developer-guide.rst @@ -0,0 +1,239 @@ +AD463x and AD403x Developer's Guide +=================================== + +Overview +-------- + +The :adi:`ad4630-24` and :adi:`ad4030-24` are part of a family of 16 and 24-bit SAR analog-to-digital converters that support sampling rates of 2 MSPS and 500 kSPS. This family of ADCs offers market-leading linearity and noise performance, enabling an evolution in the performance of ATE, electronic test and measurement, health care and scientific instrumentation systems. The evaluation boards that support these converters have been designed to work with off-the-shelf 3rd party system boards that can be used to manage the data capture process as well as host embedded applications development. This developer's guide contains information and resource links that are intended to support users that desire to develop a custom application using the `ZedBoard `_. The DUT board may be either the evaluation board for the AD463x/AD403x, or a board that the user has designed. The only requirements for the user designed board are: 1. The board should have an FMC connector. 2. The digital interface through the FMC connector should use the same pin and signal assignments used on the EVAL-AD4630-24FMCZ/EVAL-AD4030-24FMCZ board (see :adi:`EVAL-AD4630-24 ` / :adi:`EVAL-AD4030-24 ` for schematics). Otherwise, changing these assignments will require a modification of the HDL and a recompile. ADI provides the source files for the FPGA HDL, but it cannot support debug of the user modifications to the source. 3. It is recommended that the board provide a reference clock (100 MHz or less, see the :doc:`EVAL-AD4630-24FMCZ User Guide ` for more information on the reference clock requirements. 4. It is recommended to derive the digital IO voltage from the ZedBoard. The EVAL-AD4630-24FMCZ schematics provide an example of this. 5. Optional: The ZedBoard provides a 12 volt supply rail through the FMC connector which can be used to provide the main power supply for the user board. However, the latter may also be powered from a separate external supply. + +The user should consult the relevant EVAL-AD463x/EVAL-AD403x eval board user +guide to access the basic details of the evaluation board hardware. The +evaluation board schematics can be downloaded from the relevant evaluation board +web page. + +Supported Platforms +~~~~~~~~~~~~~~~~~~~ + +ZedBoard +-------- + +The AD463x/AD403x family uses the Digilent ZedBoard as the default system controller. The `ZedBoard `_ web page contains more technical documentation on the board. In addition to the ZedBoard, other 3rd party boards that have an FMC form factor may also be used with the AD463x/AD403x family of boards. As an example, see Arrow's `DataStorm DAQ `_, which uses the Intel Cyclone V SoC. |image1| |image2| \*\* Figure 1. ZedBoard (EVAL-AD463x/AD4030x system board) \*\* + +While ADI provides software that runs within the Linux environment on the ZedBoard, it also offers device drivers that can be used with other system boards, with or without an RTOS. These options will be covered in the **Software** section below. + +Basic HW and SW Architecture +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Hardware +-------- + +The AD463x evaluation board connects to the ZedBoard through an FMC connector. +This connector hosts the following signal groups + +- The digital interface between the ADC and the host processor (SoC). +- The digital I/O power supply rail. +- 12V power from the ZedBoard to the evaluation board. +- A high speed system clock used by the SoC, sourced on the evaluation board. + +The ZedBoard hosts a Xilinx Zynq7000 class SoC with dual ARM Cortex-9 hard processors and FPGA fabric. The board boots from an SD card that is shipped with each evaluation board. The **Software** section below provides more information on the software that is provided with the evaluation system. + +Software +-------- + +Two use cases are supported for developing a custom application using the +EVAL-AD463x system. They are basically distinguished by the nature of the host +processor for the ADC. ADI provides software components that support both use +cases. The following table summarizes the use cases and ADI software components. + +**Table 1. Use cases and supporting SW components** + ++-----------------+-----------------------+----------------------------------------+ +| Host processor | Host Environment | Available SW Components | ++=================+=======================+========================================+ +| SoC + FPGA | Embedded Linux | Linux image, Linux device drivers, HDL | ++-----------------+-----------------------+----------------------------------------+ +| Microcontroller | Embedded RTOS/No RTOS | No OS drivers | ++-----------------+-----------------------+----------------------------------------+ + +| The **SD card** image that ships with the evaluation board contains multiple files that can be used to reconfigure the personality of the system to match one of the valid operating modes of the ADC. The /boot directory contains a Linux image (see below), a boot.bin file which contains the FPGA configuration (among other files), and a device tree file (device.dtb). The latter two files together define the operating configuration of the system. For most user-developed applications, the configuration files provided on the SD card, along with tools that can be used to set the desired configuration, are sufficient, meaning the user should not need to build a unique Linux image, rebuild HDL, or manually modify the devicetree.dtb file. +| The following paragraphs provide additional details on the nature of these files. + +- An ADI-maintained Kuiper **Linux** distribution (uImage). Currently, the version that is installed on the SD card is customized to support product evaluation and has features that enable compatibility with :adi:`ACE `. Like the standard Kuiper Linux image, it also includes IIO support, which consists of: + + - **LibIIO subsystem** - a library of IIO functions that are used to create custom device drivers that run within the Linux system (see :doc:`LibIIO ` for more details). These drivers have already been generated for the AD463x/AD4030x and incorporated in the uImage file. + - **IIOD** - An IIO daemon that exposes IIO devices over a network connection to a remote host. + +(More information on the general Kuiper Linux distribution can be found at **\ :doc:`ADI Kuiper Linux `** + **Device tree file** that describes the attributes of the AD4630/AD4030 configuration. The attributes of the ADC node in the device tree set the clocking mode (SPI or Echo), data rate (single or dual edge), output data format (see data sheet), and number of active lanes per channel (1, 2, or 4). During boot, the system loads the device.dtb file contained in the boot directory. If the operating configuration of the ADC needs to be changed, the device tree must be updated with the new ADC attributes. Instructions for changing the operating configuration of the ADC and HDL are provided in a later section of this guide. + **BOOT.BIN** files that are used to configure the FPGA. The default boot.bin file in the boot directory will correspond to a specific interface operating mode, distinguished by clocking mode (SPI vs. Echo), number of active lanes per channel (1, 2, or 4), and data rate (SDR vs. DDR). **The boot.bin must be synchronized to the ADC attributes in the device tree**. Unique boot.bin files have been pre-generated and stored on the SD card for several different configurations. Table 2 lists the available configurations (boot.bin files) that correspond to clocking modes, lanes, data rate mode. These files are available on the SD card in sub-directories that are labeled according to the configuration. This simplifies the HDL architecture and avoids the introduction of bugs due to unnecessary complexity. + +To change the ADC operating mode, two optional methods are available. See the section below entitled **How to Modify the SD Card Image**. + +**Table 2. BOOT.BIN partitioning for AD4630/AD4030 clocking modes, lane modes and data rates** + ++---------------+-------------------------+--------------+--------------------------+ +| Clocking Mode | Lane Mode (per channel) | Data Rate | Requires unique BOOT.BIN | ++===============+=========================+==============+==========================+ +| SPI | 1 | Single (SDR) | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 2 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 4 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| Echo Clock | 1 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | Dual (DDR) | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 2 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | DDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 4 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | DDR | X | ++---------------+-------------------------+--------------+--------------------------+ + +The following sections will specifically address the Linux driver, No-OS driver, +and HDL for the AD463x family. + +Linux Driver +~~~~~~~~~~~~ + +The user guide for the AD463x family Linux driver can be found here: :doc:`AD463x Linux Driver User Guide `. The user guide provides: + +- links to the driver source code and device tree; +- an overview of the AD463x device tree options and their attributes; +- examples of how to test the driver using console commands; +- examples on how to directly access device registers for debug +- Other links to resources that have more information on IIO usage. + +HDL +~~~ + +The AD463x HDL user guide can be found here: :doc:`AD463x HDL User Guide `. The HDL user guide provides a high level description of the AD4630 HDL architecture, functionality, a link to the source file repository, and how to build a desired boot.bin configuration. Table 2 above lists all of the preconfigured modes, so in most cases it is not necessary for the user to build a unique boot.bin file. **Note:** The currently available boot.bin options only support **Zone 2 capture**, as this enables relaxed timing requirements for the interface. See the ADC data sheet for a description of Zone 2 capture. + +No-OS Drivers +~~~~~~~~~~~~~ + +The No-OS driver can be used in a bare metal application or in a non-Linux RTOS environment. Some customization, or creation of an adaptation layer for the specific platform may be required. The :doc:`AD463x No-OS user guide ` provides a general description of the driver, code documentation, and source code links. + +How to Modify the SD Card Image for alternative operating configurations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Users that are developing a custom application for the AD4630/AD4030 outside the +ACE environment, using the ZedBoard running Linux, can modify the boot image to +match one of the existing configurations listed in Table 2. Generating the +appropriate boot image can be done using the method below. Once the ACE +Environment method is executed, the boot directory on the SD card will retain +the desired boot configuration until such time that the user performs another +configuration update. + +ACE Environment +--------------- + +The :doc:`AD4630/AD4030 Evaluation Board User Guide ` contains instructions on how to change the operating configuration of the board using ACE. Note that this method assumes that the DUT board is the standard EVAL-AD4630-24FMCZ board (or AD4030-24 version), supported by an ACE plug-in. You can alter the configuration inside of the board view of the AD4630-24 ACE plugin, click apply, wait 30 seconds and the new configuration will load. + +How to Re-image the SD card +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If SD card contents have been corrupted, or the user desires to create another copy of the SD card image, instructions on how to program the SD card with a replacement/new image can be found at :doc:`ADI Kuiper Linux with support for ACE `. + +System Operational Constraints +============================== + +Sampling Frequency +------------------ + +The following table illustrates the maximum sampling rates that can be achieved +based on the device configuration. Note that the FPGA SPI engine only supports +Zone 2 data transfers from the AD4630/AD4030. + +**Table 3. Maximum sampling rate by device configuration **^ Clocking Mode ^ Lane Mode (per channel) ^ Data Rate ^ Data format ^ Max sampling rate ^ \| SPI \| 1 \| Single (SDR) \| 32-bit \| 1.75 MSPS (**note 1**) \| \| \| \| SDR \| 24-bit \| 2 MSPS \| \| \| \| Dual (DDR) \| 32 or 24-bit \| 2 MSPS \| \| \| 2 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| \| 4 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| Echo Clock \| 1 \| SDR \| 32-bit \| 1.75 MSPS (**note 1**) \| + +=== === ========== ============ ====== + SDR 24-bit 2 MSPS + DDR 32 or 24-bit 2 MSPS + 2 SDR or DDR 32 or 24-bit 2 MSPS + 4 SDR or DDR 32 or 24-bit 2 MSPS +=== === ========== ============ ====== + +**Note 1**: The sampling rate in Single lane, 32-bit output formats in SDR mode are limited by the FPGA SPI engine. This is not a limitation of the AD4630/AD4030 device. + +Application Frameworks +====================== + +Python +------ + +PyADI-IIO is an ADI maintained Python library of device specific abstraction +modules. Each device module supports the simplified development of Python +applications that use IIO by providing an API that takes care of many of the +underlying IIO details. This section of the developer's guide will describe +information on using the PyADI bindings for the AD4630/AD4030 family. + +Installation +------------ + +These instructions assume a fresh installation of all required software + +- Download `latest version `_ of python3. The Python downloader should recognize the host operating system and then download the appropriate installer. If downloading for a different machine select the Python installer accordingly. (Do not run installer yet) +- Run the installer as Administrator. During installation, **check "Add Python 3.x,x to PATH" before clicking "Install Now"** + +|image3| + +- Optional Python install: download and install a Python distribution such as `Anaconda `_. Ensure to select the proper Python version and host operating system. Recommended - install a Python editor (eg. `PyCharm `_ **community version**). One can also use `Spyder `_ that comes with Anaconda. +- Recommended - If using Anaconda, create a virtual environment for each project. Once the environment is created and activated, then: +- Install **pyadi-iio**. If running Anaconda in Windows, run the Anaconda prompt and enter **pip install pyadi-iio**. Detailed py-adi installation guide can be found :doc:`here. ` +- PyADI-IIO updates are published quarterly. It is recommended to run **pip** quarterly to get the latest updates. + +Running the AD463x/AD403x example Python scripts +------------------------------------------------ + +Generic examples for AD463x/AD403x are available in the :git-pyadi-iio:`source repo `. The example code can be used for either AD4630-24 or AD4030-24 (and derivatives). Set the device_name parameter to ensure that channel operations are appropriately handled. Basic documentation can be found at `API documentation `_. + +Note that python does not automatically scan for usb context or an IP address unless a scan is embedded in the python script. If a ZedBoard is connected via an ethernet cable, then the argument passed in the ADC device instantiation statement is **uri="ip:analog.local"** which is the default host name for the ZedBoard (see code example below). If the default hostname of the board has been changed, this should be used instead. If using at USB connection to the board, then pass the IP address for the USB port (see code example for alternative USB connection below). The USB context/IP address can be read from the board by opening a terminal/command-prompt on the PC and entering: + +:: + + iio_info -s + +.. image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ad4630-scan-usb-context.jpg + :width: 800 + +As seen above, the USB argument can be either **"usb:1.17.6"**, or**"ip:169.254.26.1"** to instantiate the device. + +The generic examples can be downloaded and executed, or custom code (see below) +can be created. + +.. code:: python + + # Import library + import adi + + # Setup actual device from ad463x family + device_name = "ad4630-24" # + + #Instantiate ADC if using Ethernet connection + adc = adi.ad4630(uri="ip:analog.local", device_name=device_name) + #ADC instantiation if using USB + #adc = adi.ad4630(uri="usb:1.17.6", device_name=device_name) + # To connect via USB + + # Configure properties + adc.rx_buffer_size = 2**12 # Rx Buffer Size + adc.sample_rate = 2000000 # Sampling Frequency + + # Get data + data = adc.rx() + +Troubleshooting +=============== + +A troubleshooting guide can be found :doc:`here `. The latter covers some tips related to ZedBoard startup and the SD card containing the Kuiper Linux image. + +.. |image1| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/zedboard_image-top.png + :width: 400 +.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/zedboard_image-bottom.png + :width: 400 +.. |image3| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ad4630-python-installation.png + :width: 800 diff --git a/docs/solutions/reference-designs/eval-ad4630/ad4630-24-eval-board.rst b/docs/solutions/reference-designs/eval-ad4630/ad4630-24-eval-board.rst new file mode 100644 index 00000000000..3240bb506d7 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad4630/ad4630-24-eval-board.rst @@ -0,0 +1,581 @@ +AD4630/AD4030 Evaluation Board User Guide +========================================= + +General Description +------------------- + +The EVAL-AD4630-24FMCZ, EVAL-AD4030-24FMCZ & EVAL-AD4630-16FMCZ evaluation boards enable quick and easy evaluation of the AD4X3X family of 24-bit & 16-bit precision successive approximation register (SAR) analog-to-digital converters (ADCs). The `AD4630-24 `_ & `AD4630-16 `_ are 2MSPS per channel, low power, dual channel 24-bit or 16-bit SAR ADCs while the `AD4030-24 `_ is a single channel 24-bit precision SAR ADC that supports up to 2 MSPS per channel. The evaluation boards demonstrate the performance of either the AD4630-24, AD4030-24 or AD4630-16 and provides a configurable analog front end (AFE) for a variety of system applications. The evaluations board are designed for use with the Digilent `ZedBoard `_. The ZedBoard is used to control data capture and buffering. The evaluation board connects to the ZedBoard board via a field-programmable gate array (FPGA) mezzanine card (FMC) low pin count (LPC) connector. The ZedBoard hosts a Xilinx Zynq7000 SoC, which has two processor cores and programmable FPGA fabric. The ZedBoard connects to the PC through USB. + +Evaluation Boards available +--------------------------- + +Two different EVAL board revision has been released on the market for AD4630-24 +and AD4630-16, the old Rev C which is obsoleted and the new revision, Rev E. On +the other hand, there is only one existing revision for AD4030-24, Rev A/B, +which is still available: + +− **OLD** AD4630-24 and AD4630-16 **Rev C** (obsoleted) evaluation boards include: + +- Two differential input channels with SMA connectors +- A high precision buffered band gap 5V reference (:adi:`LTC6655 `). +- An analog front end (AFE) that provides signal conditioning and drive for the AD4630-24 & AD4630-16. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- Full power supply solution that provides all the necessary voltage rails from + a 12V supply that is provided from the ZedBoard through the FMC connector. + +.. image:: https://wiki.analog.com/_media/resources/eval/eval-ad4630-16_top.jpg + :width: 600 + +**Figure 1a. EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ. Rev C** + +− **NEW** AD4630-24 and AD4630-16 **Rev E** evaluation boards include: + +- Two differential input channels with SMA connectors +- A high precision, low power and low noise 5V reference :adi:`ADR4550 `. There is also the option to mount a high precision buffered band gap 5V reference, the :adi:`LTC6655 `. +- An analog front end (AFE) that provides signal conditioning and drive for the AD4630-24 & AD4630-16. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- Multiple different input configurations with the amplifier `ADA4896-2 `_ +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- New form format and improved full power supply solution that provides all the necessary voltage rails from a 12V supply that is provided from the ZedBoard through the FMC connector. +- Extra connectors to supply the board externally if needed. + +.. important:: + + New boards EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ REV E have a date code + bigger than DC>2435 + +.. image:: https://wiki.analog.com/_media/resources/eval/cb-ad464030-24fmcz_top-evaluation-board.jpg + :width: 600 + +**Figure 1b. New EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ. Rev E** + +− AD4030-24 **Rev A/B** evaluation board includes: + +- One differential input channel with SMA connectors +- A high precision buffered band gap 5V reference (:adi:`LTC6655 `). +- An analog front end (AFE) that provides signal conditioning and drive for the AD4030-24. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- Full power supply solution that provides all the necessary voltage rails from + a 12V supply that is provided from the ZedBoard through the FMC connector. + +.. image:: https://wiki.analog.com/_media/resources/eval/52675_2.jpg + :width: 400 + +**Figure 1c. EVAL-AD4030-24FMCZ. Rev A/B** + +Full descriptions of these products are available in their respective data +sheets, which should be consulted when using the evaluation board. + +Features +-------- + +- On-board voltage reference, clock source, and ADC drivers +- Versatile analog signal conditioning circuitry +- FMC-LPC system board connector +- ACE PC software for configuration and data analysis (time and frequency domain) +- Compatible with other off-the-shelf controller boards + +Evaluation Board Kit Contents +----------------------------- + +- EVAL-AD4630-24FMCZ, EVAL-AD4030-24FMCZ or EVAL-AD4630-16FMCZ evaluation board +- Micro-SD memory card (with adapter) containing system board boot software and Linux OS +- Optional - ZedBoard (system controller board ) + +Equipment Needed +---------------- + +- PC with Windows 7 or Windows 10 operating system +- Digilent ZedBoard with 12 V wall adapter power supply +- Precision signal source +- SMA Cable(s) (input to evaluation board) +- Recommended - Band-pass filter centered on test signal frequency. + +Quick Start Guide +----------------- + +.. important:: + + To avoid potential issues, ensure the ZedBoard VADJ SELECT = 2.5V. |image1|\ + +- Download and install the ACE Software tool from the :adi:`ACE` download page. If ACE is already installed, make sure you have the latest version by using the ‘Check For Updates’ option in the ACE sidebar. +- An ACE Quickstart guide is available here: :doc:`ACE Quickstart - Using ACE and Installing Plug-ins ` +- Insert the EVAL-SD-KUIPERZ SD card into the SD card slot on the underside of + the ZedBoard. + +.. note:: + + If there is a need to re-image or create a new SD card, instructions are available here: :doc:`ADI Kuiper Linux with support for ACE Evaluation `. + +- Ensure the ZedBoard boot configuration jumpers are set to use the SD card as + shown. + +.. image:: https://wiki.analog.com/_media/resources/tools-software/linux-software/zedboard-sd-card-boot-jumpers.png + :align: center + :width: 200 + +.. important:: + + To avoid potential damage, ensure the VADJ SELECT jumper is set to the + correct voltage for the Product Evaluation Board. + +- Connect the Product Evaluation Board to the FMC connector on the ZedBoard. + +.. note:: + + There may be additional steps and hardware required for a given Product Evaluation Board, for example, function generators connections and setup. This information may be included with the eval kit or in the User guide for the corresponding Product Evaluation Boards page that can be found by searching :adi:`Product Evaluation Boards and Kits `. + +- Connect the USB cable from the PC to the J13/USB OTG port and the PSU to + J20/DC input. + +.. image:: https://wiki.analog.com/_media/resources/tools-software/linux-software/zedboard-usb_otg-power.png + :align: center + :width: 200 + +- Slide SW8/POWER switch to the ON position. The green LD13/POWER LED should turn on. +- The blue LD12/DONE LED & red LD0 LED should start blinking ~20-30 seconds + later which indicates the boot process is complete. + +.. tip:: + + Linux versions prior to ADI Kuiper Linux for Evaluation version 2024-8-27 + will instead boot with the BLUE LD12/DONE LED blinking immediately and LD7 + blinking after ~20-30Seconds. This may indicate that an improved version of + the ACE plugin is available if the SD-Card is updated to the latest version. + +- Launch the ACE software from the Analog Devices folder in the Windows Start + menu. The Evaluation Board should appear in the ACE Start Tab >> Attached + Hardware view. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ace_attached_hw-screen.png + :align: center + :width: 200 + +Setting Up the Evaluation Board +------------------------------- + +Figure 1 illustrates the evaluation system components. To use the system, +connect the evaluation board to the ZedBoard, connect a micro-USB cable to the +USB OTG port, apply power to the ZedBoard, open the ACE GUI, and supply an input +stimulus to one or both ADC channels. + +Each ADC channel has dedicated SMA connectors that support either a singled-ended or differential input. The signals on these inputs are injected to the configurable AFE (see the **Analog Front End** section below for more details). The digital interface to the system controller board uses level shifters to translate between the VIO supply of the AD4630-16 and the I/O voltage of the Zynq 7000 on the ZedBoard. By default, the evaluation board is powered from the system controller board 12V supply through the FMC connector. The **Power Supplies** section contains a list of optional on-board connections that can be used to connect external supplies and references to the board. + +Evaluation Board Hardware (EVAL-AD4630-24/16FMCZ REV C and EVAL-AD4030-24FMCZ REV A/B) +-------------------------------------------------------------------------------------- + +.. image:: https://wiki.analog.com/_media/resources/eval/20220509_112436.jpg + :width: 600 + +**Figure 2. EVAL-AD4630-XXFMCZ Evaluation System** + +Power Supplies +~~~~~~~~~~~~~~ + +The primary 12V supply to the EVAL-AD4X30-XXFMCZ comes from the ZedBoard through +the FMC connector. 12V is regulated down to an intermediate voltage with a +switcher and then is post regulated down to the various voltage rails. 12V is +also used to generate the negative rails for the buffers and final drive +amplifiers. + +Each of the voltage rails are brought out to turrets so they can be easily measured (see **Figure 1**). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the `AD4630-24 datasheet `_, `AD4030-24 datasheet `_ or `AD4630-16 datasheet `_ should be consulted to ensure that the external supply values comply with the device requirements. + +============ ========================================= ======== ======== +Power Supply Function Min. (V) Max. (V) +============ ========================================= ======== ======== ++12V 12V primary supply via FMC connector N/A N/A +GND Ground connection N/A N/A ++3.3V 3.3V for various digital logic 3.26 3.33 ++1.8V 1.8V for the ADC 1.77 1.81 +VIO 1.8V supply for the ADC digital I/O 1.8 1.87 ++5V 5V for the ADC 5.26 5.4 +REFIN 5V ADC reference input 4.95 5.05 +VAMP+ Positive supply for the amplifiers 5.36 5.47 +VAMP- Negative supply for the amplifiers -3.5 -3.28 +VP1 5.7V at the input of the switcher 5.45 5.75 +REF 5V at the ADC reference output 4.95 5.05 +EN 1.8V enable signal for the power supplies 1.75 1.85 +============ ========================================= ======== ======== + +**Table 1. On-Board Power Supplies** + +Reference Circuit +~~~~~~~~~~~~~~~~~ + +By default, the on-board LT6655 provides a 5 V reference to the AD4630-24, +AD4030-24 & AD4630-16. It drives the REFIN pin of the ADC through an R-C filter +(R=100Ω, C=1μF) that reduces the low frequency noise. The REFIN pin is connected +to an internal buffer, eliminating the need for an external buffer. However, if +the user desires to use an external reference that drives the internal buffer, +it can be attached the EXT REF SMA connector (see figure below). R137 should be +populated with a zero ohm resistor, and R136 should be open. The internal buffer +can be bypassed by attaching an external reference to the REF turret on the +board. To reduce the ADC power consumption, the internal reference buffer can be +disabled (see respective products data sheet). + +|image2| **Figure 3. EVAL-AD4X30-XXFMCZ Reference circuit (AD4630-24 shown. Configuration applies to all parts)** + +Clock Circuit +~~~~~~~~~~~~~ + +The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4630-24, AD4030-24 or AD4630-16. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4X30-XXFMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R55 and connect an external clock source to J1, the CLK IN SMA. **The external clock frequency must be < 100 MHz**. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm. + +|image3| **Figure 4. EVAL-AD4X30-XXFMCZ clock circuit (AD4630-24 shown. Configuration applies to all parts)** + +Analog Front End +~~~~~~~~~~~~~~~~ + +The EVAL-AD4X30-XXFMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 5, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. **Note:** As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity. + +|image4| **Figure 5. Differential Driver AFE (default) (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+---------------------------------------------------------+ +| Function: | Single ended to differential via differential amplifier | ++==============================================+=========================================================+ +| Comments: | Best distortion | ++----------------------------------------------+---------------------------------------------------------+ +| Required changes from default configuration: | No changes required | ++----------------------------------------------+---------------------------------------------------------+ + +**Table 2. EVAL-AD4620-16FMCZ Default AFE Configuration** + +A second topology can be seen in Figure 6. This topology consists of a pair of unity gain buffers, the ADA4896-2. It also can be driven by either a singled-ended or differential source. This network is ideal for observing the best noise performance of the AD4630-16, due to the low voltage and current noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers a common mode input impedance of 10 MΩ and a wide input common mode voltage range of -4.9V to +4.1V (when using +/- 5V supplies). **Note:** This driver circuit also inverts the polarity of the input signal. To preserve polarity when measuring DC voltages, connect a positive voltage to IN_A/B-. Likewise, a negative DC voltage should be connected to IN_A/B+. + +|image5| **// Figure 6. Dual Buffer AFE (AD4630-24 shown. Configuration applies to all parts) //** + ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | Differential input using buffer amplifiers | ++==============================================+=================================================================================================================================================================+ +| Comments: | Best noise & relaxed drive requirement for signal source | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R10, R12,R119, R120, R121 & R122 (Ch. A); R20, R22, R123, R124, R125 & R126 (Ch. B). Install: R31, R33, R47, & R49 (Ch. A); R60, R62, R75 & R78 (Ch. B) | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**Table 3. Unity Gain Dual Buffer Configuration** + +Figure 7 shows a driver network which combines the ADA4896-2 with the ADA4945-1. +This circuit is ideal for applications that require a high input impedance along +with gain to maximize the input range of the ADC. The gain of the ADA4945-1 can +modified by changing either the feedback resistors or input resistors. + +|image6| **Figure 7. High Impedance Buffer with Gain AFE (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+=========================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus signal scaling. | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove:R120, R121 (Ch. A);R124, R125 (Ch. B). Install: R31, R127, R28, R47, R128 & R43 (Ch. A); R60, R129, R57, R78, R130 & R72 (Ch. B) | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 4. High Impedance with Gain Configuration //** + +Figure 8 shows an input configuration that allows the AD4630-16 to be directly +driven from the SMA connectors. This enables testing with alternative driver +configurations mounted on an external PCB. + +|image7| **Figure 8. Direct Driven Inputs (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | Direct input path | ++==============================================+============================================================================================================================================================+ +| Comments: | Supports evaluation with an alternative driver | ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R10, R12, R119 & R122 (Ch A); R20, R22, R123, R126 (Ch B). Install: R28, R29, R120, R121, R43 & R44 (Ch A); R124, R57, R58, R125, R72 & R73 (Ch B) | ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**Table 5. Direct Drive Configuration** + +Evaluation Board Hardware (EVAL-AD4630-24/16FMCZ REV E) +------------------------------------------------------- + +.. image:: https://wiki.analog.com/_media/resources/eval/d_ad4630-24_setup.png + :width: 600 + +**Figure 9. EVAL-AD4630-XXFMCZ Evaluation System** + +Power Supplies +~~~~~~~~~~~~~~ + +The primary 12V supply to the EVAL-AD4X30-XXFMCZ comes from the ZedBoard through +the FMC connector. 12V is regulated down to an intermediate voltage, +7.5V, with +a switcher and then is post regulated down to the various voltage rails. 12V is +also used to generate the negative rails, -3.3V for the buffers and final drive +amplifiers. + +Each of the voltage rails are brought out to turrets so they can be easily measured (see **Figure 1**). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the `AD4630-24 datasheet `_, `AD4030-24 datasheet `_ or `AD4630-16 datasheet `_ should be consulted to ensure that the external supply values comply with the device requirements. + +============ ========================================= ======== ======== +Power Supply Function Min. (V) Max. (V) +============ ========================================= ======== ======== ++12V 12V primary supply via FMC connector N/A N/A +GND Ground connection N/A N/A ++3.3V 3.3V for various digital logic 3.26 3.33 ++1.8V 1.8V for the ADC 1.77 1.81 +VIO 1.8V supply for the ADC digital I/O 1.77 1.81 ++5.4V 5.4V for the ADC 5.34 5.46 +REFIN 5V ADC reference input 4.95 5.05 +VAMP+ Positive supply for the amplifiers 6.35 6.5 +VAMP- Negative supply for the amplifiers -3.35 -3.28 +VP1 7.5V at the input of the switcher 7.425 7.575 +REF 5V at the ADC reference output 4.95 5.05 +EN 1.8V enable signal for the power supplies 1.75 1.85 +============ ========================================= ======== ======== + +**Table 6. On-Board Power Supplies** + +The following block diagram shows all the different power supplies options available in the new evaluation board. In case necessary, it is possible to supply all the LDOs directly with external power supplies via J7 and J8. There is also two different options to generate the -3.3V although only the LT3093 is mounted on the board. |image8| **Figure 10. Power-tree** + +Reference Circuit +~~~~~~~~~~~~~~~~~ + +By default, the on-board ADR4550 provides a 5 V reference to the AD4630-24 & +AD4630-16. It drives the REFIN pin of the ADC through an R-C filter (R=100Ω, +C=22μF) that reduces the low frequency noise. The REFIN pin is connected to an +internal buffer, eliminating the need for an external buffer. However, if the +user desires to use an external reference that drives the internal buffer, it +can be attached the J5 SMA connector (see figure below). R124 should be +populated with a zero ohm resistor, and R116 and R123 should be open. The +internal buffer can be bypassed by attaching an external reference to the REF +turret on the board. To reduce the ADC power consumption, the internal reference +buffer can be disabled (see respective products data sheet). There is also the +option to mount the LTC6655 or the LTC6655LN reference which is suitable to use +it together with the unbuffered input of the ADC. + +|image9| **Figure 11. EVAL-AD4630-XXFMCZ Reference circuit (AD4630-24 shown. Configuration applies to all parts)** + +Clock Circuit +~~~~~~~~~~~~~ + +The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4630-24 or AD4630-16. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4630-XXFMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R1 and connect an external clock source to J6, the CLK IN SMA. **The external clock frequency must be < 100 MHz**. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm. + +|image10| **Figure 12. EVAL-AD4630-XXFMCZ clock circuit (AD4630-24 shown. Configuration applies to all parts)** + +Analog Front End +~~~~~~~~~~~~~~~~ + +The EVAL-AD4630-XXFMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 13, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. **Note:** As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity. + +|image11| **Figure 13. Differential Driver AFE (default) (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+---------------------------------------------------------+ +| Function: | Single ended to differential via differential amplifier | ++==============================================+=========================================================+ +| Comments: | Best distortion | ++----------------------------------------------+---------------------------------------------------------+ +| Required changes from default configuration: | No changes required | ++----------------------------------------------+---------------------------------------------------------+ + +**Table 7. EVAL-AD4620-16FMCZ Default AFE Configuration** + +There is one buffer used to generate common mode voltage, U26. The voltage can +be adjusted from 0V to Vref by selecting correctly the ratio between R98, (or +R122 or R99) and R5. + +|image12| **// Figure 14. Common mode voltage generation //** + +A second topology can be seen in Figure 15. This topology consists of a pair of +unity gain buffers, the ADA4896-2. It also can be driven by either a +singled-ended or differential source. This network is ideal for observing the +best noise performance of the AD4630-16, due to the low voltage and current +noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers +a common mode input impedance of 10 MΩ and a wide input common mode voltage +range of -4.9V to +4.1V (when using +/- 5V supplies). To use the full span of +the ADC the input signal of each buffer needs to be centered at 2.5V + +|image13| **// Figure 15. Dual Buffer AFE.//** + ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ +| Function: | Differential input using buffer amplifiers | ++==============================================+===============================================================================================================+ +| Comments: | Best noise & relaxed drive requirement for signal source | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R114, R108, R112, R106, R139, R136, R137 and R134 | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ + +**Table 8. Unity Gain Dual Buffer Configuration** + +If the signal generator connected to the inputs of the ADC cannot generate a DC +offset, there is the option to use the VOCM buffer to create an DC offset and +connect it to the non-inverting input of the ADA4896 amplifiers like Figure 16. + +|image14| **Figure 16. High Impedance Buffer with VOCM generated internally** + ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+===============================================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus DC offset. | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R114, R108, R112, R106, R139, R136, R137, R134, R120, R119, R103, R102, R142, R141, R132 and R131 | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 9. High Impedance Buffer with VOCM //** + +Another option available (Figure 17) on the board is to use the ADA4896 in an +inverting configuration with the possibility of connecting an DC offset on the +non-inverting pin. I this case it is necessary to have two input signals delayed +180º and select the correct resistors values to generate a 2.5V (R98 and R3) as +VOCM. + +|image15| **Figure 17. High Impedance Buffer with VOCM generated internally** + ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+==============================================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus DC offset. | ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R126, R96, R112, R106, R145, R129, R137, R134, R120, R119, R103, R102, R142, R141, R132 and R131 | ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 10 High Impedance Buffer with VOCM //** + +Figure 18 shows an input configuration that allows the AD4630-16 to be directly +driven from the SMA connectors. This enables testing with alternative driver +configurations mounted on an external PCB. + +|image16| **Figure 18. Direct Driven Inputs (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ +| Function: | Direct input path | ++==============================================+================================================================================================================+ +| Comments: | Supports evaluation with an alternative driver | ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R121, R118, R104, R105, R143, R140, R133 and R130. | ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ + +**Table 10. Direct Drive Configuration** + +Controller Board +---------------- + +The ZedBoard, which is the system controller board, enables the configuration of +the ADC and capture of data from the evaluation board by the PC via USB (or +Ethernet). The AD4X30-XX family of parts support a multi-lane serial port +interface (SPI) for each data converter channel. The SPI interface for each +channel is connected to the ZedBoard via the FMC connector (P1). The ZedBoard™ +functions as the communication link between the PC and connected evaluation +board. It buffers samples captured from the evaluation board in its DDR3 memory. +The ZedBoard board requires power from a 12V wall adapter (included with the +ZedBoard). It hosts a Xilinx® ZYNQ® 7020 SoC, which contains two ARM® Cortex-A9 +Processors and a Series-7 FPGA with 85k Programmable Logic cells. A Linux OS +runs on the host processor system. It communicates with the PC through either a +USB 2.0 high speed port or a 10/100/1000 Ethernet port. The default software +configuration uses USB. + +EVALUATION HARDWARE SETUP +~~~~~~~~~~~~~~~~~~~~~~~~~ + +When the ACE evaluation software installation is complete, take the following +steps to set up the ZedBoard and the evaluation board together: + +1. Insert the SD card provided with the evaluation board into J12 on the + ZedBoard + +2. Connect the Evaluation board to the FMC connector of the ZedBoard. + +3. Connect the provided power supplies to J20 on the ZedBoard. + +4. Connect the USB cable to the USB OTG (J13) on the ZedBoard and to the + computer + +5. Connect the desired input signal to the appropriate input on the evaluation + board (J2-J5) + +6. Move SW8 to the ON position to start the ZedBoard + +7. Start the ACE evaluation software (Refer to section below). + +Software Support +---------------- + +The ADI ACE application provides a ‘plug and play’ evaluation experience, +enabling users to get up and running quickly with the product evaluation board. +ACE can configure the embedded software on supported controller boards and +provides a quick and easy way to get setup, configure the board and perform data +capture and analysis and/or waveform generation. For ACE installation and +documentation instructions see www.analog.com/ace. Make sure to follow the +instructions to install the necessary evaluation board plug-in support. + +- If the machine that ACE is installed on has internet access, you can find/install/update plug-ins directly from the ACE application. For environments without internet access, you can download these plug-ins from the previous link to portable storage and install them into ACE. +- Note: Product specific documentation for the evaluation software can be found + within the ACE plug-in. + +The controller board supported by ACE with this product evaluation board is the +ZedBoard. + +System Operational Constraints +------------------------------ + +Sampling Frequency +~~~~~~~~~~~~~~~~~~ + +The following table illustrates the maximum sampling rates that can be achieved +based on the device configuration. Note that the FPGA SPI engine only supports +Zone 2 data transfers from the AD4630/AD4030. + +**Table 11. Maximum sampling rate by device configuration **^ Clocking Mode ^ Lane Mode (per channel) ^ Data Rate ^ Data format ^ Max sampling rate ^ \| SPI \| 1 \| Single (SDR) \| 32-bit \| 1.75 MSPS (**note 1**) \| \| \| \| SDR \| 24-bit \| 2 MSPS \| \| \| \| Dual (DDR) \| 32 or 24-bit \| 2 MSPS \| \| \| 2 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| \| 4 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| Echo Clock \| 1 \| SDR \| 32-bit \| 1.75 MSPS (**note 1**) \| + +=== === ========== ============ ====== + SDR 24-bit 2 MSPS + DDR 32 or 24-bit 2 MSPS + 2 SDR or DDR 32 or 24-bit 2 MSPS + 4 SDR or DDR 32 or 24-bit 2 MSPS +=== === ========== ============ ====== + +**Note 1**: The sampling rate in Single lane, 32-bit output formats in SDR mode are limited by the FPGA SPI engine. This is not a limitation of the AD4630/AD4030 device. + +Software Developers Guide +------------------------- + +Analog Devices supports the development of custom applications using the EVAL-AD4X30-XX system and are described in the :doc:`AD463x and AD403x Developer's Guide ` + +.. tip:: + + Visit :doc:`AD463x and AD403x Developer's Guide ` for an overview of the additional software drivers that are provided with the evaluation system + +Evaluation Board Support and Troubleshooting +-------------------------------------------- + +Technical Support +~~~~~~~~~~~~~~~~~ + +Technical support for the evaluation board hardware and software can be obtained by posting a question to ADI's :ez:`EngineerZone ` technical support community for precision ADCs. + +The evaluation board schematic and other board files can be found on the :adi:`EVAL-AD4630-16FMCZ `, :adi:`EVAL-AD4630-24FMCZ ` & :adi:`EVAL-AD4030-24FMCZ ` web pages. + +Troubleshooting +~~~~~~~~~~~~~~~ + +A troubleshooting guide can be found at: :doc:`Troubleshooting Guide for ADI Kuiper Linux for ACE Evaluation `. The latter covers some tips related to ZedBoard startup and the SD card containing the Kuiper Linux image. + +.. |image1| image:: https://wiki.analog.com/_media/resources/eval/adj.png + :width: 100 +.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad4630_ref_ckt.png + :width: 400 +.. |image3| image:: https://wiki.analog.com/_media/resources/eval/eval-ad4630-24_clk_ckt.png + :width: 400 +.. |image4| image:: https://wiki.analog.com/_media/resources/eval/ad4630_fda_ckt.svg + :width: 600 +.. |image5| image:: https://wiki.analog.com/_media/resources/eval/ad4630_dual_buf_ckt.svg + :width: 600 +.. |image6| image:: https://wiki.analog.com/_media/resources/eval/ad4630_cascaded_buf_fda_ckt.svg + :width: 800 +.. |image7| image:: https://wiki.analog.com/_media/resources/eval/ad4630_direct_drive_ckt.png + :width: 600 +.. |image8| image:: https://wiki.analog.com/_media/resources/eval/powertree.png + :width: 600 +.. |image9| image:: https://wiki.analog.com/_media/resources/eval/reference2.png + :width: 600 +.. |image10| image:: https://wiki.analog.com/_media/resources/eval/clock_diagram.png + :width: 600 +.. |image11| image:: https://wiki.analog.com/_media/resources/eval/differential.png + :width: 600 +.. |image12| image:: https://wiki.analog.com/_media/resources/eval/vocm.png + :width: 600 +.. |image13| image:: https://wiki.analog.com/_media/resources/eval/single_ended_config1.png + :width: 600 +.. |image14| image:: https://wiki.analog.com/_media/resources/eval/config2.png + :width: 600 +.. |image15| image:: https://wiki.analog.com/_media/resources/eval/config3.png + :width: 600 +.. |image16| image:: https://wiki.analog.com/_media/resources/eval/ad4630_direct_drive_ckt.png + :width: 600 diff --git a/docs/solutions/reference-designs/eval-ad4630/ad4630.rst b/docs/solutions/reference-designs/eval-ad4630/ad4630.rst new file mode 100644 index 00000000000..4bb213f44a8 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad4630/ad4630.rst @@ -0,0 +1,346 @@ +AD4630 ADC Linux Driver +======================= + +Supported Devices +----------------- + +- :adi:`AD4030-24` +- :adi:`AD4630-16` +- :adi:`AD4630-24` +- :adi:`ADAQ4216` +- :adi:`ADAQ4220` +- :adi:`ADAQ4224` + +Evaluation Boards +----------------- + +- :adi:`EVAL-AD4630-24 ` + +Status +------ + ++------------------------------------------------------------------------------------------+------------+ +| Source | Mainlined? | ++==========================================================================================+============+ +| :git-linux:`git ` | [No] | ++------------------------------------------------------------------------------------------+------------+ + +Files +----- + ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++=========================+=================================================================================================================================================================================+ +| driver | :git-linux:`master/drivers/iio/adc/ad4630.c ` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree bindings | :git-linux:`Documentation/devicetree/bindings/iio/adc/adi,ad4630.yaml` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree for ad4630 | :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-ad4630-24.dts` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree for adaq4224 | :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-adaq4224-24.dts` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Overview +-------- + +The :adi:`ad4030-24`, :adi:`ad4630-16`, and :adi:`ad4630-24` are 24-bit, 2 MSPS SAR ADCs highly configurable through an extensive configuration register list. + +Enabling the driver +------------------- + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +.. hint:: + + The AD4630 Driver depends on CONFIG_SPI + +:: + + Linux Kernel Configuration + Device Drivers ---> + ... + <*> Industrial I/O support ---> + --- Industrial I/O support + ... + Analog to digital converters ---> + ... + <*> Analog Devices AD4630 ADC driver + ... + ... + ... + +Adding a device tree entry +-------------------------- + +Required properties +~~~~~~~~~~~~~~~~~~~ + +- **compatible**: Must be one of "adi,ad7091r2", "adi,ad7091r4", "adi,ad7091r8". +- **reg**: number of SPI chip select id for the device. +- **clocks**: reference clock phandle +- **clock-names**: name for the reference clock +- **dmas**: phandle for dma-engine +- **dma-names**: name for the dma-engine +- **pwms**: phandles for the PWM device used as conversion start trigger. +- **pwm-names**: name for PWM devices + +Optional properties +~~~~~~~~~~~~~~~~~~~ + +- **vref-supply**: phandle + specifier to a regulator for the external VREF supply. If no external VREF is supplied this attribute should be omitted. + see: Documentation/devicetree/bindings/regulator/regulator.txt + +Device tree example +~~~~~~~~~~~~~~~~~~~ + +:: + + // SPDX-License-Identifier: GPL-2.0 + /* + * Analog Devices AD4630-24 + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2022 Analog Devices Inc. + */ + /dts-v1/; + + #include "zynq-zed.dtsi" + #include "zynq-zed-adv7511.dtsi" + #include + #include + + / { + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_1_8: regulator-vdd-1-8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vio: regulator-vio { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + clocks { + cnv_ext_clk: ext-clk { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "cnv_ext_clk"; + }; + }; + }; + + &fpga_axi { + rx_dma: rx-dmac@44a30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44a30000 0x1000>; + #dma-cells = <1>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <64>; + adi,source-bus-type = <1>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <0>; + }; + }; + }; + + spi_clk: axi-clkgen@0x44a70000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44a70000 0x10000>; + #clock-cells = <0>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "spi_clk"; + }; + + axi_pwm_gen: axi-pwm-gen@ { + compatible = "adi,axi-pwmgen"; + reg = <0x44b00000 0x1000>; + label = "ad463x_cnv"; + #pwm-cells = <2>; + clocks = <&cnv_ext_clk>; + + }; + + axi_spi_engine: spi@44a00000 { + compatible = "adi,axi-spi-engine-1.00.a"; + reg = <0x44a00000 0x1FF>; + interrupt-parent = <&intc>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>, <&spi_clk>; + clock-names = "s_axi_aclk", "spi_clk"; + num-cs = <1>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + + ad463x: ad463x@0 { + compatible = "adi,ad463x"; + reg = <0>; + vdd-supply = <&vref>; + vdd_1_8-supply = <&vdd_1_8>; + vio-supply = <&vio>; + vref-supply = <&vref>; + spi-max-frequency = <80000000>; + reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>; + adi,lane-mode = <0>; + adi,clock-mode = <0>; + adi,out-data-mode = <0>; + adi,spi-trigger; + clocks = <&cnv_ext_clk>; + clock-names = "trigger_clock"; + dmas = <&rx_dma 0>; + dma-names = "rx"; + pwm-names = "spi_trigger", "cnv"; + pwms = <&axi_pwm_gen 0 0>, <&axi_pwm_gen 1 0>; + }; + }; + }; + +Driver testing +============== + +Each and every IIO device, typically a hardware chip, has a device folder under +/sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under +every of these directory folders reside a set of files, depending on the +characteristics and features of the hardware device in question. These files are +consistently generalized and documented in the IIO ABI documentation. In order +to determine which IIO deviceX corresponds to which hardware device, the user +can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the +sequence in which the iio device drivers are loaded/registered is constant, the +numbering is constant and may be known in advance. + +.. tip:: + + \ TIP: An example program whiroot@analog:/sys/bus/iio/devices# ls -lch uses + the interface can be found here: + + + - :doc:`IIO Oscilloscope ` + + +Show device name +---------------- + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/name + adaq4224 + + +Show channel scale +------------------ + +**Description:** Scale to be applied to in_voltageX_raw in order to obtain the measured voltage in millivolts + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_scale + 0.000196695 + + +Show channel list of available scales +------------------------------------- + +**Description:** List of available scales to be applied to in_voltageX_raw in order to obtain the measured voltage in millivolts. This affects the gain applied to the input signal before ADC sampling. This attribute is available for ADAQ devices only. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_scale_available + 0.000196695 0.000333786 0.001323223 0.003975629 + + +Show channel calibration offset +------------------------------- + +**Description:** Hardware applied calibration offset (calibbias). This is a hardware supported offset that can be applied to compensate for variation between different instances of the part. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_calibbias + 0 + + +Show channel calibration scale +------------------------------ + +**Description:** Hardware applied calibration scale factor. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_calibscale + 1.000000 + + +More Information +================ + +- IIO mailing list: linux-iio@vger.kernel.org +- `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ +- `IIO Documentation `_ +- :doc:`IIO test and visualization application ` +- :doc:`libiio - IIO system library ` +- :doc:`libiio - Internals ` +- :doc:`Pointers and good books ` +- `IIO High Speed `_ +- `Software Defined Radio using the IIO framework `_ +- + +|libiio introduction| + +*Need Help?* + +- :ez:`Analog Devices Linux Device Drivers Help Forum ` +- `Ask a Question `_ + +.. |libiio introduction| image:: https://wiki.analog.com/_media/software/linux/docs/iio/youtube>p_vntewue24 diff --git a/docs/solutions/reference-designs/eval-ad4630/index.rst b/docs/solutions/reference-designs/eval-ad4630/index.rst new file mode 100644 index 00000000000..c5b73c32e27 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad4630/index.rst @@ -0,0 +1,48 @@ +.. _eval_ad4630 eval: + +EVAL AD4630 +=================================================================== + +.. TODO: Add a picture of the chip/board + +Overview +------------------------------------------------------------------------------- + +.. TODO: Describe in max 10 rows the main features and applications. + +Features: + +- feature 1 +- feature 2 + +Applications: + +- application 1 +- application 2 + +.. toctree:: + :hidden: + + ad4630 + ad4630-16-eval-board + ad4630-24-developer-guide + ad4630-24-eval-board + +Recommendations +------------------------------------------------------------------------------- + +People who follow the flow that is outlined, have a much better experience with +things. However, like many things, documentation is never as complete as it +should be. If you have any questions, feel free to ask on our +:ref:`EngineerZone forums `, but before that, please make +sure you read our documentation thoroughly. + +Warning +------------------------------------------------------------------------------- + +.. esd-warning:: + +Help and support +------------------------------------------------------------------------------- + +Please go to :ref:`Help and Support ` page. diff --git a/docs/wiki-migration/resources/eval/ad4630-16-eval-board.rst b/docs/wiki-migration/resources/eval/ad4630-16-eval-board.rst new file mode 100644 index 00000000000..f90b66d1aa9 --- /dev/null +++ b/docs/wiki-migration/resources/eval/ad4630-16-eval-board.rst @@ -0,0 +1,2 @@ +.. image:: https://wiki.analog.com/_media/resources/eval/section>resources/eval/ad4630-24-eval-board&showfooter=nofooter + :alt: section>resources/eval/ad4630-24-eval-board&showfooter=nofooter diff --git a/docs/wiki-migration/resources/eval/ad4630-24-eval-board.rst b/docs/wiki-migration/resources/eval/ad4630-24-eval-board.rst new file mode 100644 index 00000000000..3240bb506d7 --- /dev/null +++ b/docs/wiki-migration/resources/eval/ad4630-24-eval-board.rst @@ -0,0 +1,581 @@ +AD4630/AD4030 Evaluation Board User Guide +========================================= + +General Description +------------------- + +The EVAL-AD4630-24FMCZ, EVAL-AD4030-24FMCZ & EVAL-AD4630-16FMCZ evaluation boards enable quick and easy evaluation of the AD4X3X family of 24-bit & 16-bit precision successive approximation register (SAR) analog-to-digital converters (ADCs). The `AD4630-24 `_ & `AD4630-16 `_ are 2MSPS per channel, low power, dual channel 24-bit or 16-bit SAR ADCs while the `AD4030-24 `_ is a single channel 24-bit precision SAR ADC that supports up to 2 MSPS per channel. The evaluation boards demonstrate the performance of either the AD4630-24, AD4030-24 or AD4630-16 and provides a configurable analog front end (AFE) for a variety of system applications. The evaluations board are designed for use with the Digilent `ZedBoard `_. The ZedBoard is used to control data capture and buffering. The evaluation board connects to the ZedBoard board via a field-programmable gate array (FPGA) mezzanine card (FMC) low pin count (LPC) connector. The ZedBoard hosts a Xilinx Zynq7000 SoC, which has two processor cores and programmable FPGA fabric. The ZedBoard connects to the PC through USB. + +Evaluation Boards available +--------------------------- + +Two different EVAL board revision has been released on the market for AD4630-24 +and AD4630-16, the old Rev C which is obsoleted and the new revision, Rev E. On +the other hand, there is only one existing revision for AD4030-24, Rev A/B, +which is still available: + +− **OLD** AD4630-24 and AD4630-16 **Rev C** (obsoleted) evaluation boards include: + +- Two differential input channels with SMA connectors +- A high precision buffered band gap 5V reference (:adi:`LTC6655 `). +- An analog front end (AFE) that provides signal conditioning and drive for the AD4630-24 & AD4630-16. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- Full power supply solution that provides all the necessary voltage rails from + a 12V supply that is provided from the ZedBoard through the FMC connector. + +.. image:: https://wiki.analog.com/_media/resources/eval/eval-ad4630-16_top.jpg + :width: 600 + +**Figure 1a. EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ. Rev C** + +− **NEW** AD4630-24 and AD4630-16 **Rev E** evaluation boards include: + +- Two differential input channels with SMA connectors +- A high precision, low power and low noise 5V reference :adi:`ADR4550 `. There is also the option to mount a high precision buffered band gap 5V reference, the :adi:`LTC6655 `. +- An analog front end (AFE) that provides signal conditioning and drive for the AD4630-24 & AD4630-16. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- Multiple different input configurations with the amplifier `ADA4896-2 `_ +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- New form format and improved full power supply solution that provides all the necessary voltage rails from a 12V supply that is provided from the ZedBoard through the FMC connector. +- Extra connectors to supply the board externally if needed. + +.. important:: + + New boards EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ REV E have a date code + bigger than DC>2435 + +.. image:: https://wiki.analog.com/_media/resources/eval/cb-ad464030-24fmcz_top-evaluation-board.jpg + :width: 600 + +**Figure 1b. New EVAL-AD4630-24FMCZ and EVAL-AD4630-16FMCZ. Rev E** + +− AD4030-24 **Rev A/B** evaluation board includes: + +- One differential input channel with SMA connectors +- A high precision buffered band gap 5V reference (:adi:`LTC6655 `). +- An analog front end (AFE) that provides signal conditioning and drive for the AD4030-24. The AFE can be configured to use either the `ADA4896-2 `_ in a dual buffer configuration, or the `ADA4945-1 `_, a fully differential amplifier. +- An optional 100 MHz clock source that provides a reference clock for the FPGA and ADC. +- Full power supply solution that provides all the necessary voltage rails from + a 12V supply that is provided from the ZedBoard through the FMC connector. + +.. image:: https://wiki.analog.com/_media/resources/eval/52675_2.jpg + :width: 400 + +**Figure 1c. EVAL-AD4030-24FMCZ. Rev A/B** + +Full descriptions of these products are available in their respective data +sheets, which should be consulted when using the evaluation board. + +Features +-------- + +- On-board voltage reference, clock source, and ADC drivers +- Versatile analog signal conditioning circuitry +- FMC-LPC system board connector +- ACE PC software for configuration and data analysis (time and frequency domain) +- Compatible with other off-the-shelf controller boards + +Evaluation Board Kit Contents +----------------------------- + +- EVAL-AD4630-24FMCZ, EVAL-AD4030-24FMCZ or EVAL-AD4630-16FMCZ evaluation board +- Micro-SD memory card (with adapter) containing system board boot software and Linux OS +- Optional - ZedBoard (system controller board ) + +Equipment Needed +---------------- + +- PC with Windows 7 or Windows 10 operating system +- Digilent ZedBoard with 12 V wall adapter power supply +- Precision signal source +- SMA Cable(s) (input to evaluation board) +- Recommended - Band-pass filter centered on test signal frequency. + +Quick Start Guide +----------------- + +.. important:: + + To avoid potential issues, ensure the ZedBoard VADJ SELECT = 2.5V. |image1|\ + +- Download and install the ACE Software tool from the :adi:`ACE` download page. If ACE is already installed, make sure you have the latest version by using the ‘Check For Updates’ option in the ACE sidebar. +- An ACE Quickstart guide is available here: :doc:`ACE Quickstart - Using ACE and Installing Plug-ins ` +- Insert the EVAL-SD-KUIPERZ SD card into the SD card slot on the underside of + the ZedBoard. + +.. note:: + + If there is a need to re-image or create a new SD card, instructions are available here: :doc:`ADI Kuiper Linux with support for ACE Evaluation `. + +- Ensure the ZedBoard boot configuration jumpers are set to use the SD card as + shown. + +.. image:: https://wiki.analog.com/_media/resources/tools-software/linux-software/zedboard-sd-card-boot-jumpers.png + :align: center + :width: 200 + +.. important:: + + To avoid potential damage, ensure the VADJ SELECT jumper is set to the + correct voltage for the Product Evaluation Board. + +- Connect the Product Evaluation Board to the FMC connector on the ZedBoard. + +.. note:: + + There may be additional steps and hardware required for a given Product Evaluation Board, for example, function generators connections and setup. This information may be included with the eval kit or in the User guide for the corresponding Product Evaluation Boards page that can be found by searching :adi:`Product Evaluation Boards and Kits `. + +- Connect the USB cable from the PC to the J13/USB OTG port and the PSU to + J20/DC input. + +.. image:: https://wiki.analog.com/_media/resources/tools-software/linux-software/zedboard-usb_otg-power.png + :align: center + :width: 200 + +- Slide SW8/POWER switch to the ON position. The green LD13/POWER LED should turn on. +- The blue LD12/DONE LED & red LD0 LED should start blinking ~20-30 seconds + later which indicates the boot process is complete. + +.. tip:: + + Linux versions prior to ADI Kuiper Linux for Evaluation version 2024-8-27 + will instead boot with the BLUE LD12/DONE LED blinking immediately and LD7 + blinking after ~20-30Seconds. This may indicate that an improved version of + the ACE plugin is available if the SD-Card is updated to the latest version. + +- Launch the ACE software from the Analog Devices folder in the Windows Start + menu. The Evaluation Board should appear in the ACE Start Tab >> Attached + Hardware view. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ace_attached_hw-screen.png + :align: center + :width: 200 + +Setting Up the Evaluation Board +------------------------------- + +Figure 1 illustrates the evaluation system components. To use the system, +connect the evaluation board to the ZedBoard, connect a micro-USB cable to the +USB OTG port, apply power to the ZedBoard, open the ACE GUI, and supply an input +stimulus to one or both ADC channels. + +Each ADC channel has dedicated SMA connectors that support either a singled-ended or differential input. The signals on these inputs are injected to the configurable AFE (see the **Analog Front End** section below for more details). The digital interface to the system controller board uses level shifters to translate between the VIO supply of the AD4630-16 and the I/O voltage of the Zynq 7000 on the ZedBoard. By default, the evaluation board is powered from the system controller board 12V supply through the FMC connector. The **Power Supplies** section contains a list of optional on-board connections that can be used to connect external supplies and references to the board. + +Evaluation Board Hardware (EVAL-AD4630-24/16FMCZ REV C and EVAL-AD4030-24FMCZ REV A/B) +-------------------------------------------------------------------------------------- + +.. image:: https://wiki.analog.com/_media/resources/eval/20220509_112436.jpg + :width: 600 + +**Figure 2. EVAL-AD4630-XXFMCZ Evaluation System** + +Power Supplies +~~~~~~~~~~~~~~ + +The primary 12V supply to the EVAL-AD4X30-XXFMCZ comes from the ZedBoard through +the FMC connector. 12V is regulated down to an intermediate voltage with a +switcher and then is post regulated down to the various voltage rails. 12V is +also used to generate the negative rails for the buffers and final drive +amplifiers. + +Each of the voltage rails are brought out to turrets so they can be easily measured (see **Figure 1**). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the `AD4630-24 datasheet `_, `AD4030-24 datasheet `_ or `AD4630-16 datasheet `_ should be consulted to ensure that the external supply values comply with the device requirements. + +============ ========================================= ======== ======== +Power Supply Function Min. (V) Max. (V) +============ ========================================= ======== ======== ++12V 12V primary supply via FMC connector N/A N/A +GND Ground connection N/A N/A ++3.3V 3.3V for various digital logic 3.26 3.33 ++1.8V 1.8V for the ADC 1.77 1.81 +VIO 1.8V supply for the ADC digital I/O 1.8 1.87 ++5V 5V for the ADC 5.26 5.4 +REFIN 5V ADC reference input 4.95 5.05 +VAMP+ Positive supply for the amplifiers 5.36 5.47 +VAMP- Negative supply for the amplifiers -3.5 -3.28 +VP1 5.7V at the input of the switcher 5.45 5.75 +REF 5V at the ADC reference output 4.95 5.05 +EN 1.8V enable signal for the power supplies 1.75 1.85 +============ ========================================= ======== ======== + +**Table 1. On-Board Power Supplies** + +Reference Circuit +~~~~~~~~~~~~~~~~~ + +By default, the on-board LT6655 provides a 5 V reference to the AD4630-24, +AD4030-24 & AD4630-16. It drives the REFIN pin of the ADC through an R-C filter +(R=100Ω, C=1μF) that reduces the low frequency noise. The REFIN pin is connected +to an internal buffer, eliminating the need for an external buffer. However, if +the user desires to use an external reference that drives the internal buffer, +it can be attached the EXT REF SMA connector (see figure below). R137 should be +populated with a zero ohm resistor, and R136 should be open. The internal buffer +can be bypassed by attaching an external reference to the REF turret on the +board. To reduce the ADC power consumption, the internal reference buffer can be +disabled (see respective products data sheet). + +|image2| **Figure 3. EVAL-AD4X30-XXFMCZ Reference circuit (AD4630-24 shown. Configuration applies to all parts)** + +Clock Circuit +~~~~~~~~~~~~~ + +The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4630-24, AD4030-24 or AD4630-16. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4X30-XXFMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R55 and connect an external clock source to J1, the CLK IN SMA. **The external clock frequency must be < 100 MHz**. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm. + +|image3| **Figure 4. EVAL-AD4X30-XXFMCZ clock circuit (AD4630-24 shown. Configuration applies to all parts)** + +Analog Front End +~~~~~~~~~~~~~~~~ + +The EVAL-AD4X30-XXFMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 5, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. **Note:** As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity. + +|image4| **Figure 5. Differential Driver AFE (default) (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+---------------------------------------------------------+ +| Function: | Single ended to differential via differential amplifier | ++==============================================+=========================================================+ +| Comments: | Best distortion | ++----------------------------------------------+---------------------------------------------------------+ +| Required changes from default configuration: | No changes required | ++----------------------------------------------+---------------------------------------------------------+ + +**Table 2. EVAL-AD4620-16FMCZ Default AFE Configuration** + +A second topology can be seen in Figure 6. This topology consists of a pair of unity gain buffers, the ADA4896-2. It also can be driven by either a singled-ended or differential source. This network is ideal for observing the best noise performance of the AD4630-16, due to the low voltage and current noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers a common mode input impedance of 10 MΩ and a wide input common mode voltage range of -4.9V to +4.1V (when using +/- 5V supplies). **Note:** This driver circuit also inverts the polarity of the input signal. To preserve polarity when measuring DC voltages, connect a positive voltage to IN_A/B-. Likewise, a negative DC voltage should be connected to IN_A/B+. + +|image5| **// Figure 6. Dual Buffer AFE (AD4630-24 shown. Configuration applies to all parts) //** + ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | Differential input using buffer amplifiers | ++==============================================+=================================================================================================================================================================+ +| Comments: | Best noise & relaxed drive requirement for signal source | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R10, R12,R119, R120, R121 & R122 (Ch. A); R20, R22, R123, R124, R125 & R126 (Ch. B). Install: R31, R33, R47, & R49 (Ch. A); R60, R62, R75 & R78 (Ch. B) | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**Table 3. Unity Gain Dual Buffer Configuration** + +Figure 7 shows a driver network which combines the ADA4896-2 with the ADA4945-1. +This circuit is ideal for applications that require a high input impedance along +with gain to maximize the input range of the ADC. The gain of the ADA4945-1 can +modified by changing either the feedback resistors or input resistors. + +|image6| **Figure 7. High Impedance Buffer with Gain AFE (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+=========================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus signal scaling. | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove:R120, R121 (Ch. A);R124, R125 (Ch. B). Install: R31, R127, R28, R47, R128 & R43 (Ch. A); R60, R129, R57, R78, R130 & R72 (Ch. B) | ++----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 4. High Impedance with Gain Configuration //** + +Figure 8 shows an input configuration that allows the AD4630-16 to be directly +driven from the SMA connectors. This enables testing with alternative driver +configurations mounted on an external PCB. + +|image7| **Figure 8. Direct Driven Inputs (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | Direct input path | ++==============================================+============================================================================================================================================================+ +| Comments: | Supports evaluation with an alternative driver | ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R10, R12, R119 & R122 (Ch A); R20, R22, R123, R126 (Ch B). Install: R28, R29, R120, R121, R43 & R44 (Ch A); R124, R57, R58, R125, R72 & R73 (Ch B) | ++----------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**Table 5. Direct Drive Configuration** + +Evaluation Board Hardware (EVAL-AD4630-24/16FMCZ REV E) +------------------------------------------------------- + +.. image:: https://wiki.analog.com/_media/resources/eval/d_ad4630-24_setup.png + :width: 600 + +**Figure 9. EVAL-AD4630-XXFMCZ Evaluation System** + +Power Supplies +~~~~~~~~~~~~~~ + +The primary 12V supply to the EVAL-AD4X30-XXFMCZ comes from the ZedBoard through +the FMC connector. 12V is regulated down to an intermediate voltage, +7.5V, with +a switcher and then is post regulated down to the various voltage rails. 12V is +also used to generate the negative rails, -3.3V for the buffers and final drive +amplifiers. + +Each of the voltage rails are brought out to turrets so they can be easily measured (see **Figure 1**). A bench supply can be used to drive these turrets to supply the evaluation board manually. This is useful if a current measurement is required. Each supply is decoupled where it enters the board and at each device. A single ground plane is used on this board to minimize the effect of high frequency interference. The voltage ranges listed in the table below represent the expected ranges for the board. If the user desires to connect external supplies to the board, the amplifier data sheets and the `AD4630-24 datasheet `_, `AD4030-24 datasheet `_ or `AD4630-16 datasheet `_ should be consulted to ensure that the external supply values comply with the device requirements. + +============ ========================================= ======== ======== +Power Supply Function Min. (V) Max. (V) +============ ========================================= ======== ======== ++12V 12V primary supply via FMC connector N/A N/A +GND Ground connection N/A N/A ++3.3V 3.3V for various digital logic 3.26 3.33 ++1.8V 1.8V for the ADC 1.77 1.81 +VIO 1.8V supply for the ADC digital I/O 1.77 1.81 ++5.4V 5.4V for the ADC 5.34 5.46 +REFIN 5V ADC reference input 4.95 5.05 +VAMP+ Positive supply for the amplifiers 6.35 6.5 +VAMP- Negative supply for the amplifiers -3.35 -3.28 +VP1 7.5V at the input of the switcher 7.425 7.575 +REF 5V at the ADC reference output 4.95 5.05 +EN 1.8V enable signal for the power supplies 1.75 1.85 +============ ========================================= ======== ======== + +**Table 6. On-Board Power Supplies** + +The following block diagram shows all the different power supplies options available in the new evaluation board. In case necessary, it is possible to supply all the LDOs directly with external power supplies via J7 and J8. There is also two different options to generate the -3.3V although only the LT3093 is mounted on the board. |image8| **Figure 10. Power-tree** + +Reference Circuit +~~~~~~~~~~~~~~~~~ + +By default, the on-board ADR4550 provides a 5 V reference to the AD4630-24 & +AD4630-16. It drives the REFIN pin of the ADC through an R-C filter (R=100Ω, +C=22μF) that reduces the low frequency noise. The REFIN pin is connected to an +internal buffer, eliminating the need for an external buffer. However, if the +user desires to use an external reference that drives the internal buffer, it +can be attached the J5 SMA connector (see figure below). R124 should be +populated with a zero ohm resistor, and R116 and R123 should be open. The +internal buffer can be bypassed by attaching an external reference to the REF +turret on the board. To reduce the ADC power consumption, the internal reference +buffer can be disabled (see respective products data sheet). There is also the +option to mount the LTC6655 or the LTC6655LN reference which is suitable to use +it together with the unbuffered input of the ADC. + +|image9| **Figure 11. EVAL-AD4630-XXFMCZ Reference circuit (AD4630-24 shown. Configuration applies to all parts)** + +Clock Circuit +~~~~~~~~~~~~~ + +The ZedBoard uses a 100MHz reference clock to generate its internal clocks as well as the sample clock for the AD4630-24 or AD4630-16. To simplify system operation an on-board 100MHz, low-jitter crystal oscillator (XO) on the EVAL-AD4630-XXFMCZ board supplies this clock as the default configuration, as shown in the figure below. To use an external clock source, remove R1 and connect an external clock source to J6, the CLK IN SMA. **The external clock frequency must be < 100 MHz**. The user should take care to use a low jitter clock source to achieve best system performance. The external clock level should be 10 to 12 dBm. + +|image10| **Figure 12. EVAL-AD4630-XXFMCZ clock circuit (AD4630-24 shown. Configuration applies to all parts)** + +Analog Front End +~~~~~~~~~~~~~~~~ + +The EVAL-AD4630-XXFMCZ has a flexible driver network that can be configured for a variety topologies. The default network is shown in Figure 13, in which the ADA4945-1 fully differential amplifier is driving the ADC. It can accommodate both single-ended and differential signal sources, and drives the ADC differentially. As populated, it has a unity gain. When using a single-ended source, the unused input should be terminated with the equivalent source impedance. **Note:** As implemented, the AD4945-1 driver on the evaluation board preserves the differential value of IN+ - IN- (with appropriate gain scaling applied), but inverts the signal polarity that is injected to the ADC. Hence, if a positive DC signal is applied to the input, it should be attached to IN_A/B-, and likewise, a negative DC signal should be attached to IN_A/B+ to preserve the signal polarity. + +|image11| **Figure 13. Differential Driver AFE (default) (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+---------------------------------------------------------+ +| Function: | Single ended to differential via differential amplifier | ++==============================================+=========================================================+ +| Comments: | Best distortion | ++----------------------------------------------+---------------------------------------------------------+ +| Required changes from default configuration: | No changes required | ++----------------------------------------------+---------------------------------------------------------+ + +**Table 7. EVAL-AD4620-16FMCZ Default AFE Configuration** + +There is one buffer used to generate common mode voltage, U26. The voltage can +be adjusted from 0V to Vref by selecting correctly the ratio between R98, (or +R122 or R99) and R5. + +|image12| **// Figure 14. Common mode voltage generation //** + +A second topology can be seen in Figure 15. This topology consists of a pair of +unity gain buffers, the ADA4896-2. It also can be driven by either a +singled-ended or differential source. This network is ideal for observing the +best noise performance of the AD4630-16, due to the low voltage and current +noise of the ADA4896-2 (1 nV/rtHz and 2.8 pA/rtHz, respectively). It also offers +a common mode input impedance of 10 MΩ and a wide input common mode voltage +range of -4.9V to +4.1V (when using +/- 5V supplies). To use the full span of +the ADC the input signal of each buffer needs to be centered at 2.5V + +|image13| **// Figure 15. Dual Buffer AFE.//** + ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ +| Function: | Differential input using buffer amplifiers | ++==============================================+===============================================================================================================+ +| Comments: | Best noise & relaxed drive requirement for signal source | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R114, R108, R112, R106, R139, R136, R137 and R134 | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------+ + +**Table 8. Unity Gain Dual Buffer Configuration** + +If the signal generator connected to the inputs of the ADC cannot generate a DC +offset, there is the option to use the VOCM buffer to create an DC offset and +connect it to the non-inverting input of the ADA4896 amplifiers like Figure 16. + +|image14| **Figure 16. High Impedance Buffer with VOCM generated internally** + ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+===============================================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus DC offset. | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R114, R108, R112, R106, R139, R136, R137, R134, R120, R119, R103, R102, R142, R141, R132 and R131 | ++----------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 9. High Impedance Buffer with VOCM //** + +Another option available (Figure 17) on the board is to use the ADA4896 in an +inverting configuration with the possibility of connecting an DC offset on the +non-inverting pin. I this case it is necessary to have two input signals delayed +180º and select the correct resistors values to generate a 2.5V (R98 and R3) as +VOCM. + +|image15| **Figure 17. High Impedance Buffer with VOCM generated internally** + ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function: | High impedance input with gain | ++==============================================+==============================================================================================================================================================+ +| Comments: | Relaxed drive requirements from signal source plus DC offset. | ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R126, R96, R112, R106, R145, R129, R137, R134, R120, R119, R103, R102, R142, R141, R132 and R131 | ++----------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +**// Table 10 High Impedance Buffer with VOCM //** + +Figure 18 shows an input configuration that allows the AD4630-16 to be directly +driven from the SMA connectors. This enables testing with alternative driver +configurations mounted on an external PCB. + +|image16| **Figure 18. Direct Driven Inputs (AD4630-24 shown. Configuration applies to all parts)** + ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ +| Function: | Direct input path | ++==============================================+================================================================================================================+ +| Comments: | Supports evaluation with an alternative driver | ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ +| Required changes from default configuration: | Remove: R17, R23, R19, R25, R42, R45, R44 and R48. Install: R121, R118, R104, R105, R143, R140, R133 and R130. | ++----------------------------------------------+----------------------------------------------------------------------------------------------------------------+ + +**Table 10. Direct Drive Configuration** + +Controller Board +---------------- + +The ZedBoard, which is the system controller board, enables the configuration of +the ADC and capture of data from the evaluation board by the PC via USB (or +Ethernet). The AD4X30-XX family of parts support a multi-lane serial port +interface (SPI) for each data converter channel. The SPI interface for each +channel is connected to the ZedBoard via the FMC connector (P1). The ZedBoard™ +functions as the communication link between the PC and connected evaluation +board. It buffers samples captured from the evaluation board in its DDR3 memory. +The ZedBoard board requires power from a 12V wall adapter (included with the +ZedBoard). It hosts a Xilinx® ZYNQ® 7020 SoC, which contains two ARM® Cortex-A9 +Processors and a Series-7 FPGA with 85k Programmable Logic cells. A Linux OS +runs on the host processor system. It communicates with the PC through either a +USB 2.0 high speed port or a 10/100/1000 Ethernet port. The default software +configuration uses USB. + +EVALUATION HARDWARE SETUP +~~~~~~~~~~~~~~~~~~~~~~~~~ + +When the ACE evaluation software installation is complete, take the following +steps to set up the ZedBoard and the evaluation board together: + +1. Insert the SD card provided with the evaluation board into J12 on the + ZedBoard + +2. Connect the Evaluation board to the FMC connector of the ZedBoard. + +3. Connect the provided power supplies to J20 on the ZedBoard. + +4. Connect the USB cable to the USB OTG (J13) on the ZedBoard and to the + computer + +5. Connect the desired input signal to the appropriate input on the evaluation + board (J2-J5) + +6. Move SW8 to the ON position to start the ZedBoard + +7. Start the ACE evaluation software (Refer to section below). + +Software Support +---------------- + +The ADI ACE application provides a ‘plug and play’ evaluation experience, +enabling users to get up and running quickly with the product evaluation board. +ACE can configure the embedded software on supported controller boards and +provides a quick and easy way to get setup, configure the board and perform data +capture and analysis and/or waveform generation. For ACE installation and +documentation instructions see www.analog.com/ace. Make sure to follow the +instructions to install the necessary evaluation board plug-in support. + +- If the machine that ACE is installed on has internet access, you can find/install/update plug-ins directly from the ACE application. For environments without internet access, you can download these plug-ins from the previous link to portable storage and install them into ACE. +- Note: Product specific documentation for the evaluation software can be found + within the ACE plug-in. + +The controller board supported by ACE with this product evaluation board is the +ZedBoard. + +System Operational Constraints +------------------------------ + +Sampling Frequency +~~~~~~~~~~~~~~~~~~ + +The following table illustrates the maximum sampling rates that can be achieved +based on the device configuration. Note that the FPGA SPI engine only supports +Zone 2 data transfers from the AD4630/AD4030. + +**Table 11. Maximum sampling rate by device configuration **^ Clocking Mode ^ Lane Mode (per channel) ^ Data Rate ^ Data format ^ Max sampling rate ^ \| SPI \| 1 \| Single (SDR) \| 32-bit \| 1.75 MSPS (**note 1**) \| \| \| \| SDR \| 24-bit \| 2 MSPS \| \| \| \| Dual (DDR) \| 32 or 24-bit \| 2 MSPS \| \| \| 2 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| \| 4 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| Echo Clock \| 1 \| SDR \| 32-bit \| 1.75 MSPS (**note 1**) \| + +=== === ========== ============ ====== + SDR 24-bit 2 MSPS + DDR 32 or 24-bit 2 MSPS + 2 SDR or DDR 32 or 24-bit 2 MSPS + 4 SDR or DDR 32 or 24-bit 2 MSPS +=== === ========== ============ ====== + +**Note 1**: The sampling rate in Single lane, 32-bit output formats in SDR mode are limited by the FPGA SPI engine. This is not a limitation of the AD4630/AD4030 device. + +Software Developers Guide +------------------------- + +Analog Devices supports the development of custom applications using the EVAL-AD4X30-XX system and are described in the :doc:`AD463x and AD403x Developer's Guide ` + +.. tip:: + + Visit :doc:`AD463x and AD403x Developer's Guide ` for an overview of the additional software drivers that are provided with the evaluation system + +Evaluation Board Support and Troubleshooting +-------------------------------------------- + +Technical Support +~~~~~~~~~~~~~~~~~ + +Technical support for the evaluation board hardware and software can be obtained by posting a question to ADI's :ez:`EngineerZone ` technical support community for precision ADCs. + +The evaluation board schematic and other board files can be found on the :adi:`EVAL-AD4630-16FMCZ `, :adi:`EVAL-AD4630-24FMCZ ` & :adi:`EVAL-AD4030-24FMCZ ` web pages. + +Troubleshooting +~~~~~~~~~~~~~~~ + +A troubleshooting guide can be found at: :doc:`Troubleshooting Guide for ADI Kuiper Linux for ACE Evaluation `. The latter covers some tips related to ZedBoard startup and the SD card containing the Kuiper Linux image. + +.. |image1| image:: https://wiki.analog.com/_media/resources/eval/adj.png + :width: 100 +.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad4630_ref_ckt.png + :width: 400 +.. |image3| image:: https://wiki.analog.com/_media/resources/eval/eval-ad4630-24_clk_ckt.png + :width: 400 +.. |image4| image:: https://wiki.analog.com/_media/resources/eval/ad4630_fda_ckt.svg + :width: 600 +.. |image5| image:: https://wiki.analog.com/_media/resources/eval/ad4630_dual_buf_ckt.svg + :width: 600 +.. |image6| image:: https://wiki.analog.com/_media/resources/eval/ad4630_cascaded_buf_fda_ckt.svg + :width: 800 +.. |image7| image:: https://wiki.analog.com/_media/resources/eval/ad4630_direct_drive_ckt.png + :width: 600 +.. |image8| image:: https://wiki.analog.com/_media/resources/eval/powertree.png + :width: 600 +.. |image9| image:: https://wiki.analog.com/_media/resources/eval/reference2.png + :width: 600 +.. |image10| image:: https://wiki.analog.com/_media/resources/eval/clock_diagram.png + :width: 600 +.. |image11| image:: https://wiki.analog.com/_media/resources/eval/differential.png + :width: 600 +.. |image12| image:: https://wiki.analog.com/_media/resources/eval/vocm.png + :width: 600 +.. |image13| image:: https://wiki.analog.com/_media/resources/eval/single_ended_config1.png + :width: 600 +.. |image14| image:: https://wiki.analog.com/_media/resources/eval/config2.png + :width: 600 +.. |image15| image:: https://wiki.analog.com/_media/resources/eval/config3.png + :width: 600 +.. |image16| image:: https://wiki.analog.com/_media/resources/eval/ad4630_direct_drive_ckt.png + :width: 600 diff --git a/docs/wiki-migration/resources/eval/ad4630-24-eval-board/ad4630-24-developer-guide.rst b/docs/wiki-migration/resources/eval/ad4630-24-eval-board/ad4630-24-developer-guide.rst new file mode 100644 index 00000000000..286dc24cd11 --- /dev/null +++ b/docs/wiki-migration/resources/eval/ad4630-24-eval-board/ad4630-24-developer-guide.rst @@ -0,0 +1,239 @@ +AD463x and AD403x Developer's Guide +=================================== + +Overview +-------- + +The :adi:`ad4630-24` and :adi:`ad4030-24` are part of a family of 16 and 24-bit SAR analog-to-digital converters that support sampling rates of 2 MSPS and 500 kSPS. This family of ADCs offers market-leading linearity and noise performance, enabling an evolution in the performance of ATE, electronic test and measurement, health care and scientific instrumentation systems. The evaluation boards that support these converters have been designed to work with off-the-shelf 3rd party system boards that can be used to manage the data capture process as well as host embedded applications development. This developer's guide contains information and resource links that are intended to support users that desire to develop a custom application using the `ZedBoard `_. The DUT board may be either the evaluation board for the AD463x/AD403x, or a board that the user has designed. The only requirements for the user designed board are: 1. The board should have an FMC connector. 2. The digital interface through the FMC connector should use the same pin and signal assignments used on the EVAL-AD4630-24FMCZ/EVAL-AD4030-24FMCZ board (see :adi:`EVAL-AD4630-24 ` / :adi:`EVAL-AD4030-24 ` for schematics). Otherwise, changing these assignments will require a modification of the HDL and a recompile. ADI provides the source files for the FPGA HDL, but it cannot support debug of the user modifications to the source. 3. It is recommended that the board provide a reference clock (100 MHz or less, see the :doc:`EVAL-AD4630-24FMCZ User Guide ` for more information on the reference clock requirements. 4. It is recommended to derive the digital IO voltage from the ZedBoard. The EVAL-AD4630-24FMCZ schematics provide an example of this. 5. Optional: The ZedBoard provides a 12 volt supply rail through the FMC connector which can be used to provide the main power supply for the user board. However, the latter may also be powered from a separate external supply. + +The user should consult the relevant EVAL-AD463x/EVAL-AD403x eval board user +guide to access the basic details of the evaluation board hardware. The +evaluation board schematics can be downloaded from the relevant evaluation board +web page. + +Supported Platforms +~~~~~~~~~~~~~~~~~~~ + +ZedBoard +-------- + +The AD463x/AD403x family uses the Digilent ZedBoard as the default system controller. The `ZedBoard `_ web page contains more technical documentation on the board. In addition to the ZedBoard, other 3rd party boards that have an FMC form factor may also be used with the AD463x/AD403x family of boards. As an example, see Arrow's `DataStorm DAQ `_, which uses the Intel Cyclone V SoC. |image1| |image2| \*\* Figure 1. ZedBoard (EVAL-AD463x/AD4030x system board) \*\* + +While ADI provides software that runs within the Linux environment on the ZedBoard, it also offers device drivers that can be used with other system boards, with or without an RTOS. These options will be covered in the **Software** section below. + +Basic HW and SW Architecture +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Hardware +-------- + +The AD463x evaluation board connects to the ZedBoard through an FMC connector. +This connector hosts the following signal groups + +- The digital interface between the ADC and the host processor (SoC). +- The digital I/O power supply rail. +- 12V power from the ZedBoard to the evaluation board. +- A high speed system clock used by the SoC, sourced on the evaluation board. + +The ZedBoard hosts a Xilinx Zynq7000 class SoC with dual ARM Cortex-9 hard processors and FPGA fabric. The board boots from an SD card that is shipped with each evaluation board. The **Software** section below provides more information on the software that is provided with the evaluation system. + +Software +-------- + +Two use cases are supported for developing a custom application using the +EVAL-AD463x system. They are basically distinguished by the nature of the host +processor for the ADC. ADI provides software components that support both use +cases. The following table summarizes the use cases and ADI software components. + +**Table 1. Use cases and supporting SW components** + ++-----------------+-----------------------+----------------------------------------+ +| Host processor | Host Environment | Available SW Components | ++=================+=======================+========================================+ +| SoC + FPGA | Embedded Linux | Linux image, Linux device drivers, HDL | ++-----------------+-----------------------+----------------------------------------+ +| Microcontroller | Embedded RTOS/No RTOS | No OS drivers | ++-----------------+-----------------------+----------------------------------------+ + +| The **SD card** image that ships with the evaluation board contains multiple files that can be used to reconfigure the personality of the system to match one of the valid operating modes of the ADC. The /boot directory contains a Linux image (see below), a boot.bin file which contains the FPGA configuration (among other files), and a device tree file (device.dtb). The latter two files together define the operating configuration of the system. For most user-developed applications, the configuration files provided on the SD card, along with tools that can be used to set the desired configuration, are sufficient, meaning the user should not need to build a unique Linux image, rebuild HDL, or manually modify the devicetree.dtb file. +| The following paragraphs provide additional details on the nature of these files. + +- An ADI-maintained Kuiper **Linux** distribution (uImage). Currently, the version that is installed on the SD card is customized to support product evaluation and has features that enable compatibility with :adi:`ACE `. Like the standard Kuiper Linux image, it also includes IIO support, which consists of: + + - **LibIIO subsystem** - a library of IIO functions that are used to create custom device drivers that run within the Linux system (see :doc:`LibIIO ` for more details). These drivers have already been generated for the AD463x/AD4030x and incorporated in the uImage file. + - **IIOD** - An IIO daemon that exposes IIO devices over a network connection to a remote host. + +(More information on the general Kuiper Linux distribution can be found at **\ :doc:`ADI Kuiper Linux `** + **Device tree file** that describes the attributes of the AD4630/AD4030 configuration. The attributes of the ADC node in the device tree set the clocking mode (SPI or Echo), data rate (single or dual edge), output data format (see data sheet), and number of active lanes per channel (1, 2, or 4). During boot, the system loads the device.dtb file contained in the boot directory. If the operating configuration of the ADC needs to be changed, the device tree must be updated with the new ADC attributes. Instructions for changing the operating configuration of the ADC and HDL are provided in a later section of this guide. + **BOOT.BIN** files that are used to configure the FPGA. The default boot.bin file in the boot directory will correspond to a specific interface operating mode, distinguished by clocking mode (SPI vs. Echo), number of active lanes per channel (1, 2, or 4), and data rate (SDR vs. DDR). **The boot.bin must be synchronized to the ADC attributes in the device tree**. Unique boot.bin files have been pre-generated and stored on the SD card for several different configurations. Table 2 lists the available configurations (boot.bin files) that correspond to clocking modes, lanes, data rate mode. These files are available on the SD card in sub-directories that are labeled according to the configuration. This simplifies the HDL architecture and avoids the introduction of bugs due to unnecessary complexity. + +To change the ADC operating mode, two optional methods are available. See the section below entitled **How to Modify the SD Card Image**. + +**Table 2. BOOT.BIN partitioning for AD4630/AD4030 clocking modes, lane modes and data rates** + ++---------------+-------------------------+--------------+--------------------------+ +| Clocking Mode | Lane Mode (per channel) | Data Rate | Requires unique BOOT.BIN | ++===============+=========================+==============+==========================+ +| SPI | 1 | Single (SDR) | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 2 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 4 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| Echo Clock | 1 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | Dual (DDR) | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 2 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | DDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | 4 | SDR | X | ++---------------+-------------------------+--------------+--------------------------+ +| | | DDR | X | ++---------------+-------------------------+--------------+--------------------------+ + +The following sections will specifically address the Linux driver, No-OS driver, +and HDL for the AD463x family. + +Linux Driver +~~~~~~~~~~~~ + +The user guide for the AD463x family Linux driver can be found here: :doc:`AD463x Linux Driver User Guide `. The user guide provides: + +- links to the driver source code and device tree; +- an overview of the AD463x device tree options and their attributes; +- examples of how to test the driver using console commands; +- examples on how to directly access device registers for debug +- Other links to resources that have more information on IIO usage. + +HDL +~~~ + +The AD463x HDL user guide can be found here: :doc:`AD463x HDL User Guide `. The HDL user guide provides a high level description of the AD4630 HDL architecture, functionality, a link to the source file repository, and how to build a desired boot.bin configuration. Table 2 above lists all of the preconfigured modes, so in most cases it is not necessary for the user to build a unique boot.bin file. **Note:** The currently available boot.bin options only support **Zone 2 capture**, as this enables relaxed timing requirements for the interface. See the ADC data sheet for a description of Zone 2 capture. + +No-OS Drivers +~~~~~~~~~~~~~ + +The No-OS driver can be used in a bare metal application or in a non-Linux RTOS environment. Some customization, or creation of an adaptation layer for the specific platform may be required. The :doc:`AD463x No-OS user guide ` provides a general description of the driver, code documentation, and source code links. + +How to Modify the SD Card Image for alternative operating configurations +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Users that are developing a custom application for the AD4630/AD4030 outside the +ACE environment, using the ZedBoard running Linux, can modify the boot image to +match one of the existing configurations listed in Table 2. Generating the +appropriate boot image can be done using the method below. Once the ACE +Environment method is executed, the boot directory on the SD card will retain +the desired boot configuration until such time that the user performs another +configuration update. + +ACE Environment +--------------- + +The :doc:`AD4630/AD4030 Evaluation Board User Guide ` contains instructions on how to change the operating configuration of the board using ACE. Note that this method assumes that the DUT board is the standard EVAL-AD4630-24FMCZ board (or AD4030-24 version), supported by an ACE plug-in. You can alter the configuration inside of the board view of the AD4630-24 ACE plugin, click apply, wait 30 seconds and the new configuration will load. + +How to Re-image the SD card +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If SD card contents have been corrupted, or the user desires to create another copy of the SD card image, instructions on how to program the SD card with a replacement/new image can be found at :doc:`ADI Kuiper Linux with support for ACE `. + +System Operational Constraints +============================== + +Sampling Frequency +------------------ + +The following table illustrates the maximum sampling rates that can be achieved +based on the device configuration. Note that the FPGA SPI engine only supports +Zone 2 data transfers from the AD4630/AD4030. + +**Table 3. Maximum sampling rate by device configuration **^ Clocking Mode ^ Lane Mode (per channel) ^ Data Rate ^ Data format ^ Max sampling rate ^ \| SPI \| 1 \| Single (SDR) \| 32-bit \| 1.75 MSPS (**note 1**) \| \| \| \| SDR \| 24-bit \| 2 MSPS \| \| \| \| Dual (DDR) \| 32 or 24-bit \| 2 MSPS \| \| \| 2 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| \| 4 \| SDR or DDR \| 32 or 24-bit \| 2 MSPS \| \| Echo Clock \| 1 \| SDR \| 32-bit \| 1.75 MSPS (**note 1**) \| + +=== === ========== ============ ====== + SDR 24-bit 2 MSPS + DDR 32 or 24-bit 2 MSPS + 2 SDR or DDR 32 or 24-bit 2 MSPS + 4 SDR or DDR 32 or 24-bit 2 MSPS +=== === ========== ============ ====== + +**Note 1**: The sampling rate in Single lane, 32-bit output formats in SDR mode are limited by the FPGA SPI engine. This is not a limitation of the AD4630/AD4030 device. + +Application Frameworks +====================== + +Python +------ + +PyADI-IIO is an ADI maintained Python library of device specific abstraction +modules. Each device module supports the simplified development of Python +applications that use IIO by providing an API that takes care of many of the +underlying IIO details. This section of the developer's guide will describe +information on using the PyADI bindings for the AD4630/AD4030 family. + +Installation +------------ + +These instructions assume a fresh installation of all required software + +- Download `latest version `_ of python3. The Python downloader should recognize the host operating system and then download the appropriate installer. If downloading for a different machine select the Python installer accordingly. (Do not run installer yet) +- Run the installer as Administrator. During installation, **check "Add Python 3.x,x to PATH" before clicking "Install Now"** + +|image3| + +- Optional Python install: download and install a Python distribution such as `Anaconda `_. Ensure to select the proper Python version and host operating system. Recommended - install a Python editor (eg. `PyCharm `_ **community version**). One can also use `Spyder `_ that comes with Anaconda. +- Recommended - If using Anaconda, create a virtual environment for each project. Once the environment is created and activated, then: +- Install **pyadi-iio**. If running Anaconda in Windows, run the Anaconda prompt and enter **pip install pyadi-iio**. Detailed py-adi installation guide can be found :doc:`here. ` +- PyADI-IIO updates are published quarterly. It is recommended to run **pip** quarterly to get the latest updates. + +Running the AD463x/AD403x example Python scripts +------------------------------------------------ + +Generic examples for AD463x/AD403x are available in the :git-pyadi-iio:`source repo `. The example code can be used for either AD4630-24 or AD4030-24 (and derivatives). Set the device_name parameter to ensure that channel operations are appropriately handled. Basic documentation can be found at `API documentation `_. + +Note that python does not automatically scan for usb context or an IP address unless a scan is embedded in the python script. If a ZedBoard is connected via an ethernet cable, then the argument passed in the ADC device instantiation statement is **uri="ip:analog.local"** which is the default host name for the ZedBoard (see code example below). If the default hostname of the board has been changed, this should be used instead. If using at USB connection to the board, then pass the IP address for the USB port (see code example for alternative USB connection below). The USB context/IP address can be read from the board by opening a terminal/command-prompt on the PC and entering: + +:: + + iio_info -s + +.. image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ad4630-scan-usb-context.jpg + :width: 800 + +As seen above, the USB argument can be either **"usb:1.17.6"**, or**"ip:169.254.26.1"** to instantiate the device. + +The generic examples can be downloaded and executed, or custom code (see below) +can be created. + +.. code:: python + + # Import library + import adi + + # Setup actual device from ad463x family + device_name = "ad4630-24" # + + #Instantiate ADC if using Ethernet connection + adc = adi.ad4630(uri="ip:analog.local", device_name=device_name) + #ADC instantiation if using USB + #adc = adi.ad4630(uri="usb:1.17.6", device_name=device_name) + # To connect via USB + + # Configure properties + adc.rx_buffer_size = 2**12 # Rx Buffer Size + adc.sample_rate = 2000000 # Sampling Frequency + + # Get data + data = adc.rx() + +Troubleshooting +=============== + +A troubleshooting guide can be found :doc:`here `. The latter covers some tips related to ZedBoard startup and the SD card containing the Kuiper Linux image. + +.. |image1| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/zedboard_image-top.png + :width: 400 +.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/zedboard_image-bottom.png + :width: 400 +.. |image3| image:: https://wiki.analog.com/_media/resources/eval/ad4630-24-eval-board/ad4630-python-installation.png + :width: 800 diff --git a/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad4630.rst b/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad4630.rst new file mode 100644 index 00000000000..4bb213f44a8 --- /dev/null +++ b/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad4630.rst @@ -0,0 +1,346 @@ +AD4630 ADC Linux Driver +======================= + +Supported Devices +----------------- + +- :adi:`AD4030-24` +- :adi:`AD4630-16` +- :adi:`AD4630-24` +- :adi:`ADAQ4216` +- :adi:`ADAQ4220` +- :adi:`ADAQ4224` + +Evaluation Boards +----------------- + +- :adi:`EVAL-AD4630-24 ` + +Status +------ + ++------------------------------------------------------------------------------------------+------------+ +| Source | Mainlined? | ++==========================================================================================+============+ +| :git-linux:`git ` | [No] | ++------------------------------------------------------------------------------------------+------------+ + +Files +----- + ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++=========================+=================================================================================================================================================================================+ +| driver | :git-linux:`master/drivers/iio/adc/ad4630.c ` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree bindings | :git-linux:`Documentation/devicetree/bindings/iio/adc/adi,ad4630.yaml` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree for ad4630 | :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-ad4630-24.dts` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| devicetree for adaq4224 | :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-adaq4224-24.dts` | ++-------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Overview +-------- + +The :adi:`ad4030-24`, :adi:`ad4630-16`, and :adi:`ad4630-24` are 24-bit, 2 MSPS SAR ADCs highly configurable through an extensive configuration register list. + +Enabling the driver +------------------- + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +.. hint:: + + The AD4630 Driver depends on CONFIG_SPI + +:: + + Linux Kernel Configuration + Device Drivers ---> + ... + <*> Industrial I/O support ---> + --- Industrial I/O support + ... + Analog to digital converters ---> + ... + <*> Analog Devices AD4630 ADC driver + ... + ... + ... + +Adding a device tree entry +-------------------------- + +Required properties +~~~~~~~~~~~~~~~~~~~ + +- **compatible**: Must be one of "adi,ad7091r2", "adi,ad7091r4", "adi,ad7091r8". +- **reg**: number of SPI chip select id for the device. +- **clocks**: reference clock phandle +- **clock-names**: name for the reference clock +- **dmas**: phandle for dma-engine +- **dma-names**: name for the dma-engine +- **pwms**: phandles for the PWM device used as conversion start trigger. +- **pwm-names**: name for PWM devices + +Optional properties +~~~~~~~~~~~~~~~~~~~ + +- **vref-supply**: phandle + specifier to a regulator for the external VREF supply. If no external VREF is supplied this attribute should be omitted. + see: Documentation/devicetree/bindings/regulator/regulator.txt + +Device tree example +~~~~~~~~~~~~~~~~~~~ + +:: + + // SPDX-License-Identifier: GPL-2.0 + /* + * Analog Devices AD4630-24 + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2022 Analog Devices Inc. + */ + /dts-v1/; + + #include "zynq-zed.dtsi" + #include "zynq-zed-adv7511.dtsi" + #include + #include + + / { + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_1_8: regulator-vdd-1-8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vio: regulator-vio { + compatible = "regulator-fixed"; + regulator-name = "fixed-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + clocks { + cnv_ext_clk: ext-clk { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + clock-output-names = "cnv_ext_clk"; + }; + }; + }; + + &fpga_axi { + rx_dma: rx-dmac@44a30000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x44a30000 0x1000>; + #dma-cells = <1>; + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-width = <64>; + adi,source-bus-type = <1>; + adi,destination-bus-width = <64>; + adi,destination-bus-type = <0>; + }; + }; + }; + + spi_clk: axi-clkgen@0x44a70000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44a70000 0x10000>; + #clock-cells = <0>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "spi_clk"; + }; + + axi_pwm_gen: axi-pwm-gen@ { + compatible = "adi,axi-pwmgen"; + reg = <0x44b00000 0x1000>; + label = "ad463x_cnv"; + #pwm-cells = <2>; + clocks = <&cnv_ext_clk>; + + }; + + axi_spi_engine: spi@44a00000 { + compatible = "adi,axi-spi-engine-1.00.a"; + reg = <0x44a00000 0x1FF>; + interrupt-parent = <&intc>; + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>, <&spi_clk>; + clock-names = "s_axi_aclk", "spi_clk"; + num-cs = <1>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + + ad463x: ad463x@0 { + compatible = "adi,ad463x"; + reg = <0>; + vdd-supply = <&vref>; + vdd_1_8-supply = <&vdd_1_8>; + vio-supply = <&vio>; + vref-supply = <&vref>; + spi-max-frequency = <80000000>; + reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>; + adi,lane-mode = <0>; + adi,clock-mode = <0>; + adi,out-data-mode = <0>; + adi,spi-trigger; + clocks = <&cnv_ext_clk>; + clock-names = "trigger_clock"; + dmas = <&rx_dma 0>; + dma-names = "rx"; + pwm-names = "spi_trigger", "cnv"; + pwms = <&axi_pwm_gen 0 0>, <&axi_pwm_gen 1 0>; + }; + }; + }; + +Driver testing +============== + +Each and every IIO device, typically a hardware chip, has a device folder under +/sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under +every of these directory folders reside a set of files, depending on the +characteristics and features of the hardware device in question. These files are +consistently generalized and documented in the IIO ABI documentation. In order +to determine which IIO deviceX corresponds to which hardware device, the user +can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the +sequence in which the iio device drivers are loaded/registered is constant, the +numbering is constant and may be known in advance. + +.. tip:: + + \ TIP: An example program whiroot@analog:/sys/bus/iio/devices# ls -lch uses + the interface can be found here: + + + - :doc:`IIO Oscilloscope ` + + +Show device name +---------------- + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/name + adaq4224 + + +Show channel scale +------------------ + +**Description:** Scale to be applied to in_voltageX_raw in order to obtain the measured voltage in millivolts + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_scale + 0.000196695 + + +Show channel list of available scales +------------------------------------- + +**Description:** List of available scales to be applied to in_voltageX_raw in order to obtain the measured voltage in millivolts. This affects the gain applied to the input signal before ADC sampling. This attribute is available for ADAQ devices only. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_scale_available + 0.000196695 0.000333786 0.001323223 0.003975629 + + +Show channel calibration offset +------------------------------- + +**Description:** Hardware applied calibration offset (calibbias). This is a hardware supported offset that can be applied to compensate for variation between different instances of the part. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_calibbias + 0 + + +Show channel calibration scale +------------------------------ + +**Description:** Hardware applied calibration scale factor. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~ $ cat /sys/bus/iio/devices/iio\:device0/in_voltage0_calibscale + 1.000000 + + +More Information +================ + +- IIO mailing list: linux-iio@vger.kernel.org +- `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ +- `IIO Documentation `_ +- :doc:`IIO test and visualization application ` +- :doc:`libiio - IIO system library ` +- :doc:`libiio - Internals ` +- :doc:`Pointers and good books ` +- `IIO High Speed `_ +- `Software Defined Radio using the IIO framework `_ +- + +|libiio introduction| + +*Need Help?* + +- :ez:`Analog Devices Linux Device Drivers Help Forum ` +- `Ask a Question `_ + +.. |libiio introduction| image:: https://wiki.analog.com/_media/software/linux/docs/iio/youtube>p_vntewue24