From 26baa22f92c93bf0a78c1e66323b8e1fcb202752 Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Fri, 27 Mar 2026 16:50:45 +0200 Subject: [PATCH 1/6] reference-designs/eval-ad9083: Add untracked wiki-migration pages Co-Authored-By: Claude Opus 4.6 --- .../reference-designs/eval-ad9083/ad9083.rst | 355 +++++++++++++++++ .../reference-designs/eval-ad9083/index.rst | 8 + docs/wiki-migration/resources/eval/ad9083.rst | 362 ++++++++++++++++++ .../linux-drivers/iio-adc/ad9083.rst | 355 +++++++++++++++++ 4 files changed, 1080 insertions(+) create mode 100644 docs/solutions/reference-designs/eval-ad9083/ad9083.rst create mode 100644 docs/solutions/reference-designs/eval-ad9083/index.rst create mode 100644 docs/wiki-migration/resources/eval/ad9083.rst create mode 100644 docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst diff --git a/docs/solutions/reference-designs/eval-ad9083/ad9083.rst b/docs/solutions/reference-designs/eval-ad9083/ad9083.rst new file mode 100644 index 00000000000..e1acad59624 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9083/ad9083.rst @@ -0,0 +1,355 @@ +AD9083 Linux Driver +=================== + +Supported Devices +----------------- + +- :adi:`AD9083` + +Supported Boards +---------------- + +- :adi:`EVAL-AD9083` + +Supported HDL Cores +------------------- + +- :doc:`AD9083 FMC Card HDL Reference Design ` + +Description +----------- + +The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. +The device features an on-chip, programmable, single-pole antialiasing filter +and termination resistor that is designed for low power, small size, and ease of +use. The 16 ADC cores features a first-order, CTSD modulator architecture with +integrated, background nonlinearity correction logic and self cancelling dither. +Each ADC features wide bandwidth inputs supporting a variety of user-selectable +input ranges. An integrated voltage reference eases design considerations. The +analog input and clock signals are differential inputs. Each ADC has a signal +processing tile to filter out of band shaped noise from the Σ-Δ ADC and reduce +the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a +quadrature digital downconverter (DDC) with multiple finite input response (FIR) +decimation filters (decimate by J block), or up to three quadrature DDC channels +with averaging decimation filters for data gating applications. Users can +configure the Subclass 1 JESD204B based, high speed serialized output in a +variety of lane configurations (up to four), depending on the DDC configuration +and the acceptable lane rate of the receiving logic device. Multiple device +synchronization is supported through the SYSREF±, TRIG±, and SYNCINB± input +pins. The AD9083 has flexible power-down options that allow significant power +savings when desired. All of these features can be programmed using a 1.8 V +capable 3-wire serial port interface (SPI). The AD9083 is available in a +Pb-free, 100-ball CSP_BGA and is specified over the −40°C to +85°C industrial +temperature range. + +Source Code +=========== + +Files +----- + ++------------+---------------------------------------------------------------------------------------------------------------+ +| Function | File | ++============+===============================================================================================================+ +| driver | :git-linux:`drivers/iio/adc/ad9083.c` | ++------------+---------------------------------------------------------------------------------------------------------------+ +| API driver | :git-linux:`drivers/iio/adc/ad9083` | ++------------+---------------------------------------------------------------------------------------------------------------+ + +Example device trees +~~~~~~~~~~~~~~~~~~~~ + ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++===============+======================================================================================================================================================================+ +| dtsi | :git-linux:`arch/arm64/boot/dts/xilinx/adi-ad9083-fmc-ebz.dtsi` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| dts | :git-linux:`arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Documentation | :git-linux:`Documentation/devicetree/bindings/iio/adc/adi,ad9083.yaml` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Interrelated Device Drivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :doc:`JESD204 (FSM) Interface Linux Kernel Framework ` +- :doc:`JESD204 Interface Framework ` + +Transport Layer Receive AXI-ADC driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+===============================================================================================================================================+ +| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_core.c` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_ring_stream.c` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| include | :git-linux:`drivers/iio/adc/cf_axi_adc.h` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** :doc:`AXI ADC HDL Linux Driver ` + +Link Layer AXI JESD204B HDL driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+=======================================================================================================================================+ +| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_rx.c` | ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ +| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_tx.c` | ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** + +- `JESD204B/C Transmit Linux Driver `_ +- :doc:`JESD204B/C Receive Linux Driver ` + +PHY Layer AXI JESD204B GT (Gigabit Tranceiver) HDL driver (XILINX/ALTERA-INTEL) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+-------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+===============================================================================================================================+ +| driver | :git-linux:`drivers/iio/jesd204/axi_adxcvr.c` | ++----------+-------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** + +- :doc:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` + +Enabling Linux driver support +============================= + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +.. hint:: + + The AD9083 driver depends on CONFIG_SPI + +Adding Linux driver support +=========================== + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +:: + + Linux Kernel Configuration + Device Drivers ---> + <*> Industrial I/O support ---> + --- Industrial I/O support + - *- Enable ring buffer support within IIO + - *- Industrial I/O lock free software ring + - *- Enable triggered sampling support + + Direct Digital Synthesis + [--snip--] + + <*> Analog Devices CoreFPGA AXI DDS driver + <*> Analog Devices AD9083 16-Channel, 125 MHz Bandwidth, JESD204B ADC + + [--snip--] + +Device Tree Example +------------------- + +.. code:: dts + + #include + &spi0 { + adc0_ad9083: ad9083@0 { + compatible = "adi,ad9083"; + reg = <0>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; + jesd204-link-ids = <0>; + jesd204-inputs = <&axi_ad9083_core_rx 0 0>; + + spi-max-frequency = <1000000>; + clocks = <&ad9528 13>; + clock-names = "adc_ref_clk"; + adi,adc-frequency-hz= /bits/ 64 <2000000000>; /* 2 GHz */ + + /* adi_ad9083 config */ + + adi,vmax-microvolt = <1800>; + adi,fc-hz = /bits/ 64 <800000000>; + adi,rterm-ohms = <100>; + adi,backoff = <0>; + adi,finmax-hz = /bits/ 64 <100000000>; + adi,nco0_freq-hz = /bits/ 64 <0>; + adi,nco1_freq-hz = /bits/ 64 <0>; + adi,nco2_freq-hz = /bits/ 64 <0>; + adi,cic_decimation = /bits/ 8 ; + adi,j_decimation = /bits/ 8 ; + adi,g_decimation = /bits/ 8 <0>; + adi,h_decimation = /bits/ 8 <0>; + adi,nco0_datapath_mode = /bits/ 8 ; + + /* JESD204 parameters */ + + adi,octets-per-frame = <8>; + adi,frames-per-multiframe = <32>; + adi,converter-resolution = <16>; + adi,bits-per-sample = <16>; + adi,converters-per-device = <16>; + adi,control-bits-per-sample = <0>; + adi,lanes-per-device = <4>; + adi,subclass = <0>; + }; + }; + +Driver testing +============== + +In case the driver probes successfully and the device gets instantiated. Your +systems kernel messages should include some line, which may look like the one +shown below. + +:: + + [ 8.404405] ad9083 spi1.0: AD9083 Rev. 1 Grade 0 (API 1.0.1) probed + +Each and every IIO device, typically a hardware chip, has a device folder under +/sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under +every of these directory folders reside a set of files, depending on the +characteristics and features of the hardware device in question. These files are +consistently generalized and documented in the IIO ABI documentation. In order +to determine which IIO deviceX corresponds to which hardware device, the user +can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the +sequence in which the iio device drivers are loaded/registered is constant, the +numbering is constant and may be known in advance. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/bus/iio/devices# ls + iio:device0 iio:device1 iio:device2 iio_sysfs_trigger + + root@analog:/sys/bus/iio/devices# cd iio:device2 + root@analog:/sys/bus/iio/devices/iio:device2# cat name + axi-ad9083-rx-hpc + root@analog:/sys/bus/iio/devices/iio:device2# ls -l + total 0 + drwxr-xr-x 2 root root 0 Jun 23 08:02 buffer + -r--r--r-- 1 root root 4096 Jun 23 08:02 dev + -rw-r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_ctrl + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_error + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_paused + --w------- 1 root root 4096 Jun 23 08:02 jesd204_fsm_resume + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_state + -r--r--r-- 1 root root 4096 Jun 23 08:02 name + lrwxrwxrwx 1 root root 0 Jun 23 08:02 of_node -> ../../../../../firmware/devicetree/base/fpga-axi0 + drwxr-xr-x 2 root root 0 Jun 23 08:02 power + drwxr-xr-x 2 root root 0 Jun 23 08:02 scan_elements + lrwxrwxrwx 1 root root 0 Jun 23 08:02 subsystem -> ../../../../../bus/iio + -rw-r--r-- 1 root root 4096 Jun 23 08:02 uevent + + +Low level register access via debugfs (direct_reg_access) +========================================================= + +Some IIO drivers feature an optional debug facility, allowing users to read or +write registers directly. Special care needs to be taken when using this +feature, since you can modify registers on the back of the driver. Accessing +debugfs requires root privileges. + +In order to identify if the IIO device in question feature this option you first +need to identify the IIO device number. + +Therefore read the name attribute of each IIO device + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/bus/iio/devices# ls + iio:device0 iio:device1 iio:device2 iio_sysfs_trigger + root@analog:/sys/bus/iio/devices# cd iio:device2 + root@analog:/sys/bus/iio/devices/iio:device2# cat name + axi-ad9083-rx-hpc + + +Change directory to /sys/kernel/debug/iio/iio:deviceX and check if the +direct_reg_access file exists. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~# cd /sys/kernel/debug/iio/iio\:device2/ + root@analog:/sys/kernel/debug/iio/iio:device2# ls direct_reg_access + ls direct_reg_access + root@analog:/sys/kernel/debug/iio/iio:device2# + + +Reading + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x0 > direct_reg_access + + root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access + 0xAD + root@analog:/sys/kernel/debug/iio/iio:device2# + + +Writing + +Write ADDRESS VALUE + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x3D 0x80 > direct_reg_access + root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access + 0x80 + root@analog:/sys/kernel/debug/iio/iio:device2# + + +More Information +================ + +- IIO mailing list: linux-iio@vger.kernel.org +- `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ +- `IIO Documentation `_ +- :doc:`IIO test and visualization application ` +- :doc:`libiio - IIO system library ` +- :doc:`libiio - Internals ` +- :doc:`Pointers and good books ` +- `IIO High Speed `_ +- `Software Defined Radio using the IIO framework `_ +- + +|libiio introduction| + +*Need Help?* + +- :ez:`Analog Devices Linux Device Drivers Help Forum ` +- `Ask a Question `_ + +.. |libiio introduction| image:: https://wiki.analog.com/_media/software/linux/docs/iio/youtube>p_vntewue24 diff --git a/docs/solutions/reference-designs/eval-ad9083/index.rst b/docs/solutions/reference-designs/eval-ad9083/index.rst new file mode 100644 index 00000000000..8ddebf4100e --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9083/index.rst @@ -0,0 +1,8 @@ +AD9083 EVB +========== + +.. toctree:: + :hidden: + + ad9083 + ad9083 diff --git a/docs/wiki-migration/resources/eval/ad9083.rst b/docs/wiki-migration/resources/eval/ad9083.rst new file mode 100644 index 00000000000..ad739b28d42 --- /dev/null +++ b/docs/wiki-migration/resources/eval/ad9083.rst @@ -0,0 +1,362 @@ +Quick Start Guide for Evaluating the AD9083 ADC Evaluation Board Using the ADS8-V3EBZ FPGA-Based Capture Board +============================================================================================================== + +Typical Setup +------------- + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083ebz-ads8-v3ebztop-ethernet.jpg + :width: 650 + +*Figure 1. AD9083EBZ Evaluation Board and ADS8-V3EBZ Data Capture Board* + +Equipment Needed +---------------- + +- High Quality Analog Signal Source. +- Bandpass filter for the Analog Signal Source. +- The AD9083 PLL Reference Clock, FPGA Reference Clock and FPGA Global Clock are provided by the on-board AD9528 JESD204B Clock Generator. +- PC running Windows® with admin privileges and an available ethernet and USB + port. Windows® 7 and Windows® 10 are currently supported by ACE. + +Hardware Needed +--------------- + +- AD9083EBZ Evaluation Board +- `ads8-v3ebz `_ High Speed Carrier Card + +Software Needed +--------------- + +- :doc:`ACE ` + +Helpful Documents +----------------- + +- :adi:`AD9083 Data Sheet ` +- `ACE Manual `_ +- :adi:`Understanding High Speed ADC Testing and Evaluation - AN-835 ` + +Board Design and Integration Files +---------------------------------- + +- `Schematics `_ +- `Layout files `_ +- `Bill of materials `_ + +Set Up MicroZed™ Connection +--------------------------- + +Before performing the evaluation of the AD9083, the Ethernet interface to the +MicroZed™ board must be set up by configuring the network interface between the +PC and the MicroZed™ board. + +**MicroSD Card for the MicroZed™ Board** + +To ensure proper connection between the microSD card and the MicroZed™ board, +follow these steps: + +:: + + -Locate the microSD card labeled ADS8-HSx from the contents of ADS8-V3EBZ packaging. + -Connect the microSD card to the MicroZed™ board (the contacts of the microSD card are face up). + -As a precaution, ensure that the MicroZed™ board is seated properly on the ADS8-V3EBZ. Only a visual inspection is needed. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/sd-card-location.jpg + :width: 400 + +*Figure 2. MicroSD Card Slot in MicroZed Board **Configure the Network Interface to the MicroZed™ Board** + +To configure the network interface to the MicroZed™ board, follow these steps: + +:: + + -Ensure that the connections to ADS8-V3EBZ are as shown in Figure 1. It is not necessary to connect the AD9083EBZ evaluation board. + -One end of the Ethernet cable can be connected directly to the PC Ethernet port or to a USB to Ethernet adapter, with the other end connected to the MicroZed™ board. + -Power on the ADS8-V3EBZ board. Allow up to 10 sec for the MicroZed™ board to boot up. + -Open the local area connection settings. On Windows 7: Start Menu > Control Panel > Network and Sharing Center > Change adapter settings. On Windows 10: Start Menu > Settings > Network & Internet > Change adapter options. + -If the Local Area Connection icon does not appear in the Network Connections window, unplug the Ethernet connection from the MicroZed™ board and then reconnect it. + -Double click the Local Area Connection icon that appears. + -Click Properties. + -Select Internet Protocol Version 4 (TCP/IPv4). + -Click Properties. + -Enter 192.168.0.1 in the IP address field. + -Ensure the Subnet mask field shows 255.255.255.0. + -Click OK. + +Evaluation Software Configuration +--------------------------------- + +Download and run the ACE installer from the :adi:`ACE web page ` . After the ACE software is installed, the user must install the plugin for the AD9083 evaluation board. There are two options for installing the plugin, as described in the following sections. + +**Plugin Installation from ACE** + +Installing plugins can be performed using the Plug-in Marketplace feature in the +ACE software as described in this section. Plugins can also be downloaded from +the ACE software page by searching for the relevant device number within the ACE +software. + +To install a plugin from ACE, follow these steps: + +:: + + -From the Start menu, click All Programs > Analog Devices > ACE to open the main ACE software window. + -In the left pane, click Plug-in Manager. The Manage Plug-ins window opens, as shown in Figure 2. + -Click the Available Packages dropdown menu on the left side of the software window. + -Enter the AD9083 in the search bar on the right side of the window to search for the device that is intended for evaluation and find the appropriate board plugin. + -Select the AD9083 plugin and click Install Selected. + -Click Close. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/manage_plugins.png + :width: 600 + +*Figure 3. ACE Manage Plug-ins Window **Plugin Installation from the Web** + +To install the plugin from the web, follow these steps: + +- Ensure that the ACE software is installed. +- From the ACE software page on the Analog Devices, Inc.,:adi:`ACE web page `, navigate to the ACE Evaluation Board Plug-ins section and search for the device to evaluate. +- Click the AD9083 board plugin. The board plugin automatically downloads to the PC. When the download is complete, locate the downloaded file. Note that if the browser used for the plugin download is Internet Explorer, the file extension of the plugin file is .zip. If this occurs, right click the file and rename the file extension to .acezip. +- Double click the .acezip file to automatically install the plugin. +- The plugin installation process open the ACE software. Close ACE after plugin + installation completes. + +Introduction to the AD9083 Plugin +--------------------------------- + +The AD9083 plugin allows the user to evaluate the AD9083 chip via the AD9083EBZ +evaluation board. The AD9083EBZ provides the power and clocking necessary to +evaluate the AD9083 16-Channel ADC. The Power Delivery Network is powered by a +LTM8074 1.2A Silent Switcher µModule Regulator and clocking is provided by a +AD9528 JESD204B Clock Generator. The reference for the AD9528 is a on-board 100 +MHz VCXO. + +The AD9083EBZ Plugin will configure the AD9083 using the API. The Plugin +generates the API commands, which are then downloaded to the MicroZed™, which in +turn configures the AD9083. + +The Plugin will also configure the AD9528 using the clocking requirements from +the Startup Wizard. + +To start using the AD9083EBZ, first ensure the board is connected as shown in +Figure 1. Next, ensure that the ADS8-V3EBZ board is powered on before opening +ACE. When the user opens the ACE software, the plugin appears in the Attached +Hardware section of the ACE GUI (see Figure 3). + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/attached-hardware.png + :width: 600 + +*Figure 4. AD9083EBZ Evaluation Board and ADS8-V3EBZ Data Capture Board **Board View** + +Double clicking the board icon in the Attached Hardware section in ACE opens the +AD9083EBZ board view. + +The board view tab enables the user to quickly set up the AD9083. Figure 4 shows +the STARTUP WIZARD pane within the AD9083EBZ board view. It may take several +moments for the board view to initialize. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_-_2_narrow_bw_mode_startup_wizzard.png + :width: 800 + +*Figure 5. AD9083EBZ Evaluation Board Quick Configuration **Chip View** + +Double clicking the AD9083 icon in the board view opens the chip view. The chip +view enables the user to customize the AD9083 beyond the functions available in +the board view. + +.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_-_4_narrow_bw_mode_ad9083.png + :width: 600 + +*Figure 6. AD9083EBZ Evaluation Board Quick Configuration* + +Evaluation +---------- + +The AD9083 can be configured in many different ways. We will provide examples +for several configurations here. + +**Wide Bandwidth Real Output Mode** + +Parameters: + +- Sample rate = 2 GSPS. +- On-chip PLL reference = 250 MHz.(Provided by the on-board AD9528) +- fINMAX = 100 MHz (sample rate/20). +- fC = 800 MHz. +- VMAX = 2.0 V. +- RTERM = 100 Ω. +- EN_HP = 0 +- Backoff = 0 +- CIC decimator = bypass. +- Use mixer? = No. +- Decimate by J = 8. +- Transport parameters L, M, F, S, N’, K = 4, 16, 6, 1, 12, 32. +- 4 lanes at 15 Gbps each + +:: + + -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. + -Click "Apply". It will take several moments for the configuration to complete. + -Navigate to Analysis + -Click "Run Once" + +You should see an FFT after setting up the board as shown and running the macro. + +|Figure 6. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT| + +*Figure 7. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT **Narrow Bandwidth Complex Output Mode** + +This configuration is suitable for applications such as phased-array radar. The +output bandwidth is ± 12.7187 MHz. This example uses an Analog input frequency +of 70.5MHz and the NCO frequency is 70.3125 MHz. Using the AD9083EBZ Startup +Wizard, configure the AD9083 using the parameters below. + +Parameters: + +- Sample rate = 2 GSPS. +- On-chip PLL reference = 250 MHz.(Provided by the on-board AD9528) +- fINMAX = 100 MHz (sample rate/20). +- fC = 800 MHz. +- VMAX = 2.0 V. +- RTERM = 100 Ω. +- EN_HP = 0 +- Backoff = 0 +- NCO0/mixer (complex data), FTW = 70.3125 MHz. +- CIC decimator = 4. +- Decimate by J = 16. +- Transport parameters L, M, F, S, N’, K = 2, 32, 32, 1, 16, 32. +- 2 lanes at 10 Gbps each. + +:: + + -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. + -Click "Apply". It will take several moments for the configuration to complete. + -Navigate to Analysis + -Click "Run Once" + +You should see an FFT after setting up the board as shown and running the macro. + +|Figure 6. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT| + +*Figure 8. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT **Precision Time Domain Mode** + +Parameters: + +- Sample rate = 1 GSPS. +- On-chip PLL reference = 125 MHz.(Provided by the on-board AD9528) +- VMAX = 1.8 V. +- RTERM = 100 Ω. +- fC = 800 MHz. +- High Performance Mode = False +- Fin Max = 50 MHz (sample rate/20). +- Backoff = 0 +- # ADC Channels = 16 +- Bypass CIC = False +- CIC decimator = 8. +- Use Mixer? = False +- Decimate by J = Bypass (Decimate by 1) +- jtx_subclasv_cfg = 0 +- Lanes (L) = 3 +- Virtual Converters (M) = 16 +- (Octets/Frame)/Lane(F) = 8 +- Bits Packed (NP) = 12 +- Resolution Bits (N) = 12 +- Frames in a multi-frame (K) = 32 +- 3 lanes at 10 Gbps each. + +:: + + -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. + -Click "Apply". It will take several moments for the configuration to complete. + -Navigate to Analysis + -Click "Run Once" + +You should see an FFT after setting up the board as shown and running the macro. + +|image1| + +*Figure 9. AD9083EBZ Precision Time Domain Mode Typical FFT* + +External Trigger +---------------- + +SMA connector J2 on the ADS8v3 can be used as an optional trigger so that the +data capture start time can be controlled. The trigger requires a 1.8V active +high pulse width that is longer than the FPGA internal peripheral clock, which +has a frequency of 50 MHz. To enable the external trigger: + +1. Click on "Navigate to FPGA SPI" on the block diagram of the AD9083 Chip View + +|image2| + +2. Click on the "+" sign next to Address (Hex) 0106. + +|image3| + +3. Click on the "0" that is on the same row as "ext_trig_en". The 0 will change + to a 1. + +|image4| + +4. Click "Apply Changes" + +|image5| + +SMA connector J3 is normally used as a system ready indicator. It indicates that +the FPGA is ready to accept an external trigger. + +To capture data, click on "Run Once" as normal. Capture will begin once 1.8V is +detected on connector J2 of the ADS8v3. + +Troubleshooting Notes +--------------------- + +**Evaluation Board is not Functioning Properly** + +:: + + *It is possible that a board component has been rendered inoperable by ESD, removing a jumper during powered operation, accidental shorting while probing, etc. Try checking the supply domain voltages of the power adapter board while it is powered. They should be as follows: + +====== ========== =============== +Domain Test Point Approx. Voltage +====== ========== =============== +12V_IN TP19 12V +V1P0V TP6 1V +V1P8V TP14 1.8V +====== ========== =============== + +**Evaluation Board is not Communicating with the ADS8-V3 / No SPI Communication** + +:: + + *Make sure the USB cable is making good connection on the ADS8-V3EBZ board and the PC. Try another USB port on the PC if needed. Some PCs work best with a SuperSpeed USB 3.0 port. + *The ADS8-V3EBZ should show up on the PC Device Manager + *Make sure that the FPGA on the ADS8-V3 has been programmed - a lit FPGA_DONE LED DS15 on the top of the ADS8-V3 and a powered fan are good indicators of the FPGA being programmed. + *Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly 0.5V. On the ADS8-V3, the common mode voltage should be around 0.8V. + *To test SPI operation, attempt to both read and write to register 0x000A (Scratch Pad Register) using ACE's Register Debugger. If the register reads back the same value written to it, SPI is operational. + *All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication. + *Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS8-V3 not being programmed. + +**Evaluation Board Fails to Capture Data** + +:: + + *Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips. + *Check the signal generator input on connector J20. Using SPI, read the On-Chip PLL lock Detect register 0xD44 to see if the on-chip PLL is locked. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. + *Check the JESD204B PLL Locked indicator or register 0x301F (PLL Status). If the light in the plugin chip view is green / if the register reads back 0x80, the PLL is locked. If it is not locked: + *Restart the evaluation board setup (power cycle FPGA, start a new session in ACE) by following the instructions from the start + *Make sure P3 (Power Down / Standby Jumper) is not jumped. + +.. |Figure 6. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT| image:: https://wiki.analog.com/_media/resources/eval/ad9083/wide_bw_mode.png + :width: 600 +.. |Figure 6. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT| image:: https://wiki.analog.com/_media/resources/eval/ad9083/narrow_bw_mode.png + :width: 600 +.. |image1| image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_ptd.png + :width: 600 +.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad9083/navigate_to_fpga_spi.png + :width: 396 +.. |image3| image:: https://wiki.analog.com/_media/resources/eval/ad9083/0106.png + :width: 555 +.. |image4| image:: https://wiki.analog.com/_media/resources/eval/ad9083/ext_trig_en.png + :width: 1652 +.. |image5| image:: https://wiki.analog.com/_media/resources/eval/ad9083/apply_changes.png + :width: 94 diff --git a/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst b/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst new file mode 100644 index 00000000000..e1acad59624 --- /dev/null +++ b/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst @@ -0,0 +1,355 @@ +AD9083 Linux Driver +=================== + +Supported Devices +----------------- + +- :adi:`AD9083` + +Supported Boards +---------------- + +- :adi:`EVAL-AD9083` + +Supported HDL Cores +------------------- + +- :doc:`AD9083 FMC Card HDL Reference Design ` + +Description +----------- + +The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. +The device features an on-chip, programmable, single-pole antialiasing filter +and termination resistor that is designed for low power, small size, and ease of +use. The 16 ADC cores features a first-order, CTSD modulator architecture with +integrated, background nonlinearity correction logic and self cancelling dither. +Each ADC features wide bandwidth inputs supporting a variety of user-selectable +input ranges. An integrated voltage reference eases design considerations. The +analog input and clock signals are differential inputs. Each ADC has a signal +processing tile to filter out of band shaped noise from the Σ-Δ ADC and reduce +the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a +quadrature digital downconverter (DDC) with multiple finite input response (FIR) +decimation filters (decimate by J block), or up to three quadrature DDC channels +with averaging decimation filters for data gating applications. Users can +configure the Subclass 1 JESD204B based, high speed serialized output in a +variety of lane configurations (up to four), depending on the DDC configuration +and the acceptable lane rate of the receiving logic device. Multiple device +synchronization is supported through the SYSREF±, TRIG±, and SYNCINB± input +pins. The AD9083 has flexible power-down options that allow significant power +savings when desired. All of these features can be programmed using a 1.8 V +capable 3-wire serial port interface (SPI). The AD9083 is available in a +Pb-free, 100-ball CSP_BGA and is specified over the −40°C to +85°C industrial +temperature range. + +Source Code +=========== + +Files +----- + ++------------+---------------------------------------------------------------------------------------------------------------+ +| Function | File | ++============+===============================================================================================================+ +| driver | :git-linux:`drivers/iio/adc/ad9083.c` | ++------------+---------------------------------------------------------------------------------------------------------------+ +| API driver | :git-linux:`drivers/iio/adc/ad9083` | ++------------+---------------------------------------------------------------------------------------------------------------+ + +Example device trees +~~~~~~~~~~~~~~~~~~~~ + ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++===============+======================================================================================================================================================================+ +| dtsi | :git-linux:`arch/arm64/boot/dts/xilinx/adi-ad9083-fmc-ebz.dtsi` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| dts | :git-linux:`arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Documentation | :git-linux:`Documentation/devicetree/bindings/iio/adc/adi,ad9083.yaml` | ++---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Interrelated Device Drivers +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :doc:`JESD204 (FSM) Interface Linux Kernel Framework ` +- :doc:`JESD204 Interface Framework ` + +Transport Layer Receive AXI-ADC driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+===============================================================================================================================================+ +| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_core.c` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_ring_stream.c` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +| include | :git-linux:`drivers/iio/adc/cf_axi_adc.h` | ++----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** :doc:`AXI ADC HDL Linux Driver ` + +Link Layer AXI JESD204B HDL driver +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+=======================================================================================================================================+ +| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_rx.c` | ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ +| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_tx.c` | ++----------+---------------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** + +- `JESD204B/C Transmit Linux Driver `_ +- :doc:`JESD204B/C Receive Linux Driver ` + +PHY Layer AXI JESD204B GT (Gigabit Tranceiver) HDL driver (XILINX/ALTERA-INTEL) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + ++----------+-------------------------------------------------------------------------------------------------------------------------------+ +| Function | File | ++==========+===============================================================================================================================+ +| driver | :git-linux:`drivers/iio/jesd204/axi_adxcvr.c` | ++----------+-------------------------------------------------------------------------------------------------------------------------------+ + +**Documentation:** + +- :doc:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` + +Enabling Linux driver support +============================= + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +.. hint:: + + The AD9083 driver depends on CONFIG_SPI + +Adding Linux driver support +=========================== + +Configure kernel with "make menuconfig" (alternatively use "make xconfig" or +"make qconfig") + +:: + + Linux Kernel Configuration + Device Drivers ---> + <*> Industrial I/O support ---> + --- Industrial I/O support + - *- Enable ring buffer support within IIO + - *- Industrial I/O lock free software ring + - *- Enable triggered sampling support + + Direct Digital Synthesis + [--snip--] + + <*> Analog Devices CoreFPGA AXI DDS driver + <*> Analog Devices AD9083 16-Channel, 125 MHz Bandwidth, JESD204B ADC + + [--snip--] + +Device Tree Example +------------------- + +.. code:: dts + + #include + &spi0 { + adc0_ad9083: ad9083@0 { + compatible = "adi,ad9083"; + reg = <0>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; + jesd204-link-ids = <0>; + jesd204-inputs = <&axi_ad9083_core_rx 0 0>; + + spi-max-frequency = <1000000>; + clocks = <&ad9528 13>; + clock-names = "adc_ref_clk"; + adi,adc-frequency-hz= /bits/ 64 <2000000000>; /* 2 GHz */ + + /* adi_ad9083 config */ + + adi,vmax-microvolt = <1800>; + adi,fc-hz = /bits/ 64 <800000000>; + adi,rterm-ohms = <100>; + adi,backoff = <0>; + adi,finmax-hz = /bits/ 64 <100000000>; + adi,nco0_freq-hz = /bits/ 64 <0>; + adi,nco1_freq-hz = /bits/ 64 <0>; + adi,nco2_freq-hz = /bits/ 64 <0>; + adi,cic_decimation = /bits/ 8 ; + adi,j_decimation = /bits/ 8 ; + adi,g_decimation = /bits/ 8 <0>; + adi,h_decimation = /bits/ 8 <0>; + adi,nco0_datapath_mode = /bits/ 8 ; + + /* JESD204 parameters */ + + adi,octets-per-frame = <8>; + adi,frames-per-multiframe = <32>; + adi,converter-resolution = <16>; + adi,bits-per-sample = <16>; + adi,converters-per-device = <16>; + adi,control-bits-per-sample = <0>; + adi,lanes-per-device = <4>; + adi,subclass = <0>; + }; + }; + +Driver testing +============== + +In case the driver probes successfully and the device gets instantiated. Your +systems kernel messages should include some line, which may look like the one +shown below. + +:: + + [ 8.404405] ad9083 spi1.0: AD9083 Rev. 1 Grade 0 (API 1.0.1) probed + +Each and every IIO device, typically a hardware chip, has a device folder under +/sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under +every of these directory folders reside a set of files, depending on the +characteristics and features of the hardware device in question. These files are +consistently generalized and documented in the IIO ABI documentation. In order +to determine which IIO deviceX corresponds to which hardware device, the user +can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the +sequence in which the iio device drivers are loaded/registered is constant, the +numbering is constant and may be known in advance. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/bus/iio/devices# ls + iio:device0 iio:device1 iio:device2 iio_sysfs_trigger + + root@analog:/sys/bus/iio/devices# cd iio:device2 + root@analog:/sys/bus/iio/devices/iio:device2# cat name + axi-ad9083-rx-hpc + root@analog:/sys/bus/iio/devices/iio:device2# ls -l + total 0 + drwxr-xr-x 2 root root 0 Jun 23 08:02 buffer + -r--r--r-- 1 root root 4096 Jun 23 08:02 dev + -rw-r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_ctrl + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_error + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_paused + --w------- 1 root root 4096 Jun 23 08:02 jesd204_fsm_resume + -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_state + -r--r--r-- 1 root root 4096 Jun 23 08:02 name + lrwxrwxrwx 1 root root 0 Jun 23 08:02 of_node -> ../../../../../firmware/devicetree/base/fpga-axi0 + drwxr-xr-x 2 root root 0 Jun 23 08:02 power + drwxr-xr-x 2 root root 0 Jun 23 08:02 scan_elements + lrwxrwxrwx 1 root root 0 Jun 23 08:02 subsystem -> ../../../../../bus/iio + -rw-r--r-- 1 root root 4096 Jun 23 08:02 uevent + + +Low level register access via debugfs (direct_reg_access) +========================================================= + +Some IIO drivers feature an optional debug facility, allowing users to read or +write registers directly. Special care needs to be taken when using this +feature, since you can modify registers on the back of the driver. Accessing +debugfs requires root privileges. + +In order to identify if the IIO device in question feature this option you first +need to identify the IIO device number. + +Therefore read the name attribute of each IIO device + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/bus/iio/devices# ls + iio:device0 iio:device1 iio:device2 iio_sysfs_trigger + root@analog:/sys/bus/iio/devices# cd iio:device2 + root@analog:/sys/bus/iio/devices/iio:device2# cat name + axi-ad9083-rx-hpc + + +Change directory to /sys/kernel/debug/iio/iio:deviceX and check if the +direct_reg_access file exists. + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:~# cd /sys/kernel/debug/iio/iio\:device2/ + root@analog:/sys/kernel/debug/iio/iio:device2# ls direct_reg_access + ls direct_reg_access + root@analog:/sys/kernel/debug/iio/iio:device2# + + +Reading + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x0 > direct_reg_access + + root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access + 0xAD + root@analog:/sys/kernel/debug/iio/iio:device2# + + +Writing + +Write ADDRESS VALUE + +.. container:: box bggreen + + This specifies any shell prompt running on the target + + + :: + + root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x3D 0x80 > direct_reg_access + root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access + 0x80 + root@analog:/sys/kernel/debug/iio/iio:device2# + + +More Information +================ + +- IIO mailing list: linux-iio@vger.kernel.org +- `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ +- `IIO Documentation `_ +- :doc:`IIO test and visualization application ` +- :doc:`libiio - IIO system library ` +- :doc:`libiio - Internals ` +- :doc:`Pointers and good books ` +- `IIO High Speed `_ +- `Software Defined Radio using the IIO framework `_ +- + +|libiio introduction| + +*Need Help?* + +- :ez:`Analog Devices Linux Device Drivers Help Forum ` +- `Ask a Question `_ + +.. |libiio introduction| image:: https://wiki.analog.com/_media/software/linux/docs/iio/youtube>p_vntewue24 From 5fdf4ced14ce704edd236610655cfec1ff5c9c7c Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Thu, 2 Apr 2026 13:16:37 +0300 Subject: [PATCH 2/6] Replace stub index.rst with template Co-Authored-By: Claude Opus 4.6 --- .../reference-designs/eval-ad9083/index.rst | 42 ++++++++++++++++++- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/docs/solutions/reference-designs/eval-ad9083/index.rst b/docs/solutions/reference-designs/eval-ad9083/index.rst index 8ddebf4100e..1d50a63a93f 100644 --- a/docs/solutions/reference-designs/eval-ad9083/index.rst +++ b/docs/solutions/reference-designs/eval-ad9083/index.rst @@ -1,8 +1,46 @@ -AD9083 EVB -========== +.. _eval_ad9083 eval: + +EVAL AD9083 +=================================================================== + +.. TODO: Add a picture of the chip/board + +Overview +------------------------------------------------------------------------------- + +.. TODO: Describe in max 10 rows the main features and applications. + +Features: + +- feature 1 +- feature 2 + +Applications: + +- application 1 +- application 2 .. toctree:: :hidden: ad9083 ad9083 + +Recommendations +------------------------------------------------------------------------------- + +People who follow the flow that is outlined, have a much better experience with +things. However, like many things, documentation is never as complete as it +should be. If you have any questions, feel free to ask on our +:ref:`EngineerZone forums `, but before that, please make +sure you read our documentation thoroughly. + +Warning +------------------------------------------------------------------------------- + +.. esd-warning:: + +Help and support +------------------------------------------------------------------------------- + +Please go to :ref:`Help and Support ` page. From dfc274127fb78ce8884d5caa3c7cd545bf8422fa Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Tue, 7 Apr 2026 13:22:19 +0300 Subject: [PATCH 3/6] Fix build: remove leaked wiki-migration source files, fix index.rst Co-Authored-By: Claude Opus 4.6 --- docs/wiki-migration/resources/eval/ad9083.rst | 362 ------------------ .../linux-drivers/iio-adc/ad9083.rst | 355 ----------------- 2 files changed, 717 deletions(-) delete mode 100644 docs/wiki-migration/resources/eval/ad9083.rst delete mode 100644 docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst diff --git a/docs/wiki-migration/resources/eval/ad9083.rst b/docs/wiki-migration/resources/eval/ad9083.rst deleted file mode 100644 index ad739b28d42..00000000000 --- a/docs/wiki-migration/resources/eval/ad9083.rst +++ /dev/null @@ -1,362 +0,0 @@ -Quick Start Guide for Evaluating the AD9083 ADC Evaluation Board Using the ADS8-V3EBZ FPGA-Based Capture Board -============================================================================================================== - -Typical Setup -------------- - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083ebz-ads8-v3ebztop-ethernet.jpg - :width: 650 - -*Figure 1. AD9083EBZ Evaluation Board and ADS8-V3EBZ Data Capture Board* - -Equipment Needed ----------------- - -- High Quality Analog Signal Source. -- Bandpass filter for the Analog Signal Source. -- The AD9083 PLL Reference Clock, FPGA Reference Clock and FPGA Global Clock are provided by the on-board AD9528 JESD204B Clock Generator. -- PC running Windows® with admin privileges and an available ethernet and USB - port. Windows® 7 and Windows® 10 are currently supported by ACE. - -Hardware Needed ---------------- - -- AD9083EBZ Evaluation Board -- `ads8-v3ebz `_ High Speed Carrier Card - -Software Needed ---------------- - -- :doc:`ACE ` - -Helpful Documents ------------------ - -- :adi:`AD9083 Data Sheet ` -- `ACE Manual `_ -- :adi:`Understanding High Speed ADC Testing and Evaluation - AN-835 ` - -Board Design and Integration Files ----------------------------------- - -- `Schematics `_ -- `Layout files `_ -- `Bill of materials `_ - -Set Up MicroZed™ Connection ---------------------------- - -Before performing the evaluation of the AD9083, the Ethernet interface to the -MicroZed™ board must be set up by configuring the network interface between the -PC and the MicroZed™ board. - -**MicroSD Card for the MicroZed™ Board** - -To ensure proper connection between the microSD card and the MicroZed™ board, -follow these steps: - -:: - - -Locate the microSD card labeled ADS8-HSx from the contents of ADS8-V3EBZ packaging. - -Connect the microSD card to the MicroZed™ board (the contacts of the microSD card are face up). - -As a precaution, ensure that the MicroZed™ board is seated properly on the ADS8-V3EBZ. Only a visual inspection is needed. - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/sd-card-location.jpg - :width: 400 - -*Figure 2. MicroSD Card Slot in MicroZed Board **Configure the Network Interface to the MicroZed™ Board** - -To configure the network interface to the MicroZed™ board, follow these steps: - -:: - - -Ensure that the connections to ADS8-V3EBZ are as shown in Figure 1. It is not necessary to connect the AD9083EBZ evaluation board. - -One end of the Ethernet cable can be connected directly to the PC Ethernet port or to a USB to Ethernet adapter, with the other end connected to the MicroZed™ board. - -Power on the ADS8-V3EBZ board. Allow up to 10 sec for the MicroZed™ board to boot up. - -Open the local area connection settings. On Windows 7: Start Menu > Control Panel > Network and Sharing Center > Change adapter settings. On Windows 10: Start Menu > Settings > Network & Internet > Change adapter options. - -If the Local Area Connection icon does not appear in the Network Connections window, unplug the Ethernet connection from the MicroZed™ board and then reconnect it. - -Double click the Local Area Connection icon that appears. - -Click Properties. - -Select Internet Protocol Version 4 (TCP/IPv4). - -Click Properties. - -Enter 192.168.0.1 in the IP address field. - -Ensure the Subnet mask field shows 255.255.255.0. - -Click OK. - -Evaluation Software Configuration ---------------------------------- - -Download and run the ACE installer from the :adi:`ACE web page ` . After the ACE software is installed, the user must install the plugin for the AD9083 evaluation board. There are two options for installing the plugin, as described in the following sections. - -**Plugin Installation from ACE** - -Installing plugins can be performed using the Plug-in Marketplace feature in the -ACE software as described in this section. Plugins can also be downloaded from -the ACE software page by searching for the relevant device number within the ACE -software. - -To install a plugin from ACE, follow these steps: - -:: - - -From the Start menu, click All Programs > Analog Devices > ACE to open the main ACE software window. - -In the left pane, click Plug-in Manager. The Manage Plug-ins window opens, as shown in Figure 2. - -Click the Available Packages dropdown menu on the left side of the software window. - -Enter the AD9083 in the search bar on the right side of the window to search for the device that is intended for evaluation and find the appropriate board plugin. - -Select the AD9083 plugin and click Install Selected. - -Click Close. - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/manage_plugins.png - :width: 600 - -*Figure 3. ACE Manage Plug-ins Window **Plugin Installation from the Web** - -To install the plugin from the web, follow these steps: - -- Ensure that the ACE software is installed. -- From the ACE software page on the Analog Devices, Inc.,:adi:`ACE web page `, navigate to the ACE Evaluation Board Plug-ins section and search for the device to evaluate. -- Click the AD9083 board plugin. The board plugin automatically downloads to the PC. When the download is complete, locate the downloaded file. Note that if the browser used for the plugin download is Internet Explorer, the file extension of the plugin file is .zip. If this occurs, right click the file and rename the file extension to .acezip. -- Double click the .acezip file to automatically install the plugin. -- The plugin installation process open the ACE software. Close ACE after plugin - installation completes. - -Introduction to the AD9083 Plugin ---------------------------------- - -The AD9083 plugin allows the user to evaluate the AD9083 chip via the AD9083EBZ -evaluation board. The AD9083EBZ provides the power and clocking necessary to -evaluate the AD9083 16-Channel ADC. The Power Delivery Network is powered by a -LTM8074 1.2A Silent Switcher µModule Regulator and clocking is provided by a -AD9528 JESD204B Clock Generator. The reference for the AD9528 is a on-board 100 -MHz VCXO. - -The AD9083EBZ Plugin will configure the AD9083 using the API. The Plugin -generates the API commands, which are then downloaded to the MicroZed™, which in -turn configures the AD9083. - -The Plugin will also configure the AD9528 using the clocking requirements from -the Startup Wizard. - -To start using the AD9083EBZ, first ensure the board is connected as shown in -Figure 1. Next, ensure that the ADS8-V3EBZ board is powered on before opening -ACE. When the user opens the ACE software, the plugin appears in the Attached -Hardware section of the ACE GUI (see Figure 3). - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/attached-hardware.png - :width: 600 - -*Figure 4. AD9083EBZ Evaluation Board and ADS8-V3EBZ Data Capture Board **Board View** - -Double clicking the board icon in the Attached Hardware section in ACE opens the -AD9083EBZ board view. - -The board view tab enables the user to quickly set up the AD9083. Figure 4 shows -the STARTUP WIZARD pane within the AD9083EBZ board view. It may take several -moments for the board view to initialize. - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_-_2_narrow_bw_mode_startup_wizzard.png - :width: 800 - -*Figure 5. AD9083EBZ Evaluation Board Quick Configuration **Chip View** - -Double clicking the AD9083 icon in the board view opens the chip view. The chip -view enables the user to customize the AD9083 beyond the functions available in -the board view. - -.. image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_-_4_narrow_bw_mode_ad9083.png - :width: 600 - -*Figure 6. AD9083EBZ Evaluation Board Quick Configuration* - -Evaluation ----------- - -The AD9083 can be configured in many different ways. We will provide examples -for several configurations here. - -**Wide Bandwidth Real Output Mode** - -Parameters: - -- Sample rate = 2 GSPS. -- On-chip PLL reference = 250 MHz.(Provided by the on-board AD9528) -- fINMAX = 100 MHz (sample rate/20). -- fC = 800 MHz. -- VMAX = 2.0 V. -- RTERM = 100 Ω. -- EN_HP = 0 -- Backoff = 0 -- CIC decimator = bypass. -- Use mixer? = No. -- Decimate by J = 8. -- Transport parameters L, M, F, S, N’, K = 4, 16, 6, 1, 12, 32. -- 4 lanes at 15 Gbps each - -:: - - -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. - -Click "Apply". It will take several moments for the configuration to complete. - -Navigate to Analysis - -Click "Run Once" - -You should see an FFT after setting up the board as shown and running the macro. - -|Figure 6. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT| - -*Figure 7. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT **Narrow Bandwidth Complex Output Mode** - -This configuration is suitable for applications such as phased-array radar. The -output bandwidth is ± 12.7187 MHz. This example uses an Analog input frequency -of 70.5MHz and the NCO frequency is 70.3125 MHz. Using the AD9083EBZ Startup -Wizard, configure the AD9083 using the parameters below. - -Parameters: - -- Sample rate = 2 GSPS. -- On-chip PLL reference = 250 MHz.(Provided by the on-board AD9528) -- fINMAX = 100 MHz (sample rate/20). -- fC = 800 MHz. -- VMAX = 2.0 V. -- RTERM = 100 Ω. -- EN_HP = 0 -- Backoff = 0 -- NCO0/mixer (complex data), FTW = 70.3125 MHz. -- CIC decimator = 4. -- Decimate by J = 16. -- Transport parameters L, M, F, S, N’, K = 2, 32, 32, 1, 16, 32. -- 2 lanes at 10 Gbps each. - -:: - - -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. - -Click "Apply". It will take several moments for the configuration to complete. - -Navigate to Analysis - -Click "Run Once" - -You should see an FFT after setting up the board as shown and running the macro. - -|Figure 6. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT| - -*Figure 8. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT **Precision Time Domain Mode** - -Parameters: - -- Sample rate = 1 GSPS. -- On-chip PLL reference = 125 MHz.(Provided by the on-board AD9528) -- VMAX = 1.8 V. -- RTERM = 100 Ω. -- fC = 800 MHz. -- High Performance Mode = False -- Fin Max = 50 MHz (sample rate/20). -- Backoff = 0 -- # ADC Channels = 16 -- Bypass CIC = False -- CIC decimator = 8. -- Use Mixer? = False -- Decimate by J = Bypass (Decimate by 1) -- jtx_subclasv_cfg = 0 -- Lanes (L) = 3 -- Virtual Converters (M) = 16 -- (Octets/Frame)/Lane(F) = 8 -- Bits Packed (NP) = 12 -- Resolution Bits (N) = 12 -- Frames in a multi-frame (K) = 32 -- 3 lanes at 10 Gbps each. - -:: - - -Configure the AD9083 and AD9528 using the AD9083EBZSTARTUP WIZARD using the parameters listed above. - -Click "Apply". It will take several moments for the configuration to complete. - -Navigate to Analysis - -Click "Run Once" - -You should see an FFT after setting up the board as shown and running the macro. - -|image1| - -*Figure 9. AD9083EBZ Precision Time Domain Mode Typical FFT* - -External Trigger ----------------- - -SMA connector J2 on the ADS8v3 can be used as an optional trigger so that the -data capture start time can be controlled. The trigger requires a 1.8V active -high pulse width that is longer than the FPGA internal peripheral clock, which -has a frequency of 50 MHz. To enable the external trigger: - -1. Click on "Navigate to FPGA SPI" on the block diagram of the AD9083 Chip View - -|image2| - -2. Click on the "+" sign next to Address (Hex) 0106. - -|image3| - -3. Click on the "0" that is on the same row as "ext_trig_en". The 0 will change - to a 1. - -|image4| - -4. Click "Apply Changes" - -|image5| - -SMA connector J3 is normally used as a system ready indicator. It indicates that -the FPGA is ready to accept an external trigger. - -To capture data, click on "Run Once" as normal. Capture will begin once 1.8V is -detected on connector J2 of the ADS8v3. - -Troubleshooting Notes ---------------------- - -**Evaluation Board is not Functioning Properly** - -:: - - *It is possible that a board component has been rendered inoperable by ESD, removing a jumper during powered operation, accidental shorting while probing, etc. Try checking the supply domain voltages of the power adapter board while it is powered. They should be as follows: - -====== ========== =============== -Domain Test Point Approx. Voltage -====== ========== =============== -12V_IN TP19 12V -V1P0V TP6 1V -V1P8V TP14 1.8V -====== ========== =============== - -**Evaluation Board is not Communicating with the ADS8-V3 / No SPI Communication** - -:: - - *Make sure the USB cable is making good connection on the ADS8-V3EBZ board and the PC. Try another USB port on the PC if needed. Some PCs work best with a SuperSpeed USB 3.0 port. - *The ADS8-V3EBZ should show up on the PC Device Manager - *Make sure that the FPGA on the ADS8-V3 has been programmed - a lit FPGA_DONE LED DS15 on the top of the ADS8-V3 and a powered fan are good indicators of the FPGA being programmed. - *Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly 0.5V. On the ADS8-V3, the common mode voltage should be around 0.8V. - *To test SPI operation, attempt to both read and write to register 0x000A (Scratch Pad Register) using ACE's Register Debugger. If the register reads back the same value written to it, SPI is operational. - *All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication. - *Register 0x0000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS8-V3 not being programmed. - -**Evaluation Board Fails to Capture Data** - -:: - - *Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips. - *Check the signal generator input on connector J20. Using SPI, read the On-Chip PLL lock Detect register 0xD44 to see if the on-chip PLL is locked. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip. - *Check the JESD204B PLL Locked indicator or register 0x301F (PLL Status). If the light in the plugin chip view is green / if the register reads back 0x80, the PLL is locked. If it is not locked: - *Restart the evaluation board setup (power cycle FPGA, start a new session in ACE) by following the instructions from the start - *Make sure P3 (Power Down / Standby Jumper) is not jumped. - -.. |Figure 6. AD9083EBZ Wide Bandwidth Real Output Mode Typical FFT| image:: https://wiki.analog.com/_media/resources/eval/ad9083/wide_bw_mode.png - :width: 600 -.. |Figure 6. AD9083EBZ Narrow Bandwidth Complex Output Mode Typical FFT| image:: https://wiki.analog.com/_media/resources/eval/ad9083/narrow_bw_mode.png - :width: 600 -.. |image1| image:: https://wiki.analog.com/_media/resources/eval/ad9083/ad9083_ptd.png - :width: 600 -.. |image2| image:: https://wiki.analog.com/_media/resources/eval/ad9083/navigate_to_fpga_spi.png - :width: 396 -.. |image3| image:: https://wiki.analog.com/_media/resources/eval/ad9083/0106.png - :width: 555 -.. |image4| image:: https://wiki.analog.com/_media/resources/eval/ad9083/ext_trig_en.png - :width: 1652 -.. |image5| image:: https://wiki.analog.com/_media/resources/eval/ad9083/apply_changes.png - :width: 94 diff --git a/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst b/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst deleted file mode 100644 index e1acad59624..00000000000 --- a/docs/wiki-migration/resources/tools-software/linux-drivers/iio-adc/ad9083.rst +++ /dev/null @@ -1,355 +0,0 @@ -AD9083 Linux Driver -=================== - -Supported Devices ------------------ - -- :adi:`AD9083` - -Supported Boards ----------------- - -- :adi:`EVAL-AD9083` - -Supported HDL Cores -------------------- - -- :doc:`AD9083 FMC Card HDL Reference Design ` - -Description ------------ - -The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. -The device features an on-chip, programmable, single-pole antialiasing filter -and termination resistor that is designed for low power, small size, and ease of -use. The 16 ADC cores features a first-order, CTSD modulator architecture with -integrated, background nonlinearity correction logic and self cancelling dither. -Each ADC features wide bandwidth inputs supporting a variety of user-selectable -input ranges. An integrated voltage reference eases design considerations. The -analog input and clock signals are differential inputs. Each ADC has a signal -processing tile to filter out of band shaped noise from the Σ-Δ ADC and reduce -the sample rate. Each tile contains a cascaded integrator comb (CIC) filter, a -quadrature digital downconverter (DDC) with multiple finite input response (FIR) -decimation filters (decimate by J block), or up to three quadrature DDC channels -with averaging decimation filters for data gating applications. Users can -configure the Subclass 1 JESD204B based, high speed serialized output in a -variety of lane configurations (up to four), depending on the DDC configuration -and the acceptable lane rate of the receiving logic device. Multiple device -synchronization is supported through the SYSREF±, TRIG±, and SYNCINB± input -pins. The AD9083 has flexible power-down options that allow significant power -savings when desired. All of these features can be programmed using a 1.8 V -capable 3-wire serial port interface (SPI). The AD9083 is available in a -Pb-free, 100-ball CSP_BGA and is specified over the −40°C to +85°C industrial -temperature range. - -Source Code -=========== - -Files ------ - -+------------+---------------------------------------------------------------------------------------------------------------+ -| Function | File | -+============+===============================================================================================================+ -| driver | :git-linux:`drivers/iio/adc/ad9083.c` | -+------------+---------------------------------------------------------------------------------------------------------------+ -| API driver | :git-linux:`drivers/iio/adc/ad9083` | -+------------+---------------------------------------------------------------------------------------------------------------+ - -Example device trees -~~~~~~~~~~~~~~~~~~~~ - -+---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Function | File | -+===============+======================================================================================================================================================================+ -| dtsi | :git-linux:`arch/arm64/boot/dts/xilinx/adi-ad9083-fmc-ebz.dtsi` | -+---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| dts | :git-linux:`arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9083-fmc-ebz.dts` | -+---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Documentation | :git-linux:`Documentation/devicetree/bindings/iio/adc/adi,ad9083.yaml` | -+---------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - -Interrelated Device Drivers -~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -- :doc:`JESD204 (FSM) Interface Linux Kernel Framework ` -- :doc:`JESD204 Interface Framework ` - -Transport Layer Receive AXI-ADC driver -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -| Function | File | -+==========+===============================================================================================================================================+ -| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_core.c` | -+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -| driver | :git-linux:`drivers/iio/adc/cf_axi_adc_ring_stream.c` | -+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -| include | :git-linux:`drivers/iio/adc/cf_axi_adc.h` | -+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ - -**Documentation:** :doc:`AXI ADC HDL Linux Driver ` - -Link Layer AXI JESD204B HDL driver -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -+----------+---------------------------------------------------------------------------------------------------------------------------------------+ -| Function | File | -+==========+=======================================================================================================================================+ -| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_rx.c` | -+----------+---------------------------------------------------------------------------------------------------------------------------------------+ -| driver | :git-linux:`drivers/iio/jesd204/axi_jesd204_tx.c` | -+----------+---------------------------------------------------------------------------------------------------------------------------------------+ - -**Documentation:** - -- `JESD204B/C Transmit Linux Driver `_ -- :doc:`JESD204B/C Receive Linux Driver ` - -PHY Layer AXI JESD204B GT (Gigabit Tranceiver) HDL driver (XILINX/ALTERA-INTEL) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -+----------+-------------------------------------------------------------------------------------------------------------------------------+ -| Function | File | -+==========+===============================================================================================================================+ -| driver | :git-linux:`drivers/iio/jesd204/axi_adxcvr.c` | -+----------+-------------------------------------------------------------------------------------------------------------------------------+ - -**Documentation:** - -- :doc:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` - -Enabling Linux driver support -============================= - -Configure kernel with "make menuconfig" (alternatively use "make xconfig" or -"make qconfig") - -.. hint:: - - The AD9083 driver depends on CONFIG_SPI - -Adding Linux driver support -=========================== - -Configure kernel with "make menuconfig" (alternatively use "make xconfig" or -"make qconfig") - -:: - - Linux Kernel Configuration - Device Drivers ---> - <*> Industrial I/O support ---> - --- Industrial I/O support - - *- Enable ring buffer support within IIO - - *- Industrial I/O lock free software ring - - *- Enable triggered sampling support - - Direct Digital Synthesis - [--snip--] - - <*> Analog Devices CoreFPGA AXI DDS driver - <*> Analog Devices AD9083 16-Channel, 125 MHz Bandwidth, JESD204B ADC - - [--snip--] - -Device Tree Example -------------------- - -.. code:: dts - - #include - &spi0 { - adc0_ad9083: ad9083@0 { - compatible = "adi,ad9083"; - reg = <0>; - - jesd204-device; - #jesd204-cells = <2>; - jesd204-top-device = <0>; - jesd204-link-ids = <0>; - jesd204-inputs = <&axi_ad9083_core_rx 0 0>; - - spi-max-frequency = <1000000>; - clocks = <&ad9528 13>; - clock-names = "adc_ref_clk"; - adi,adc-frequency-hz= /bits/ 64 <2000000000>; /* 2 GHz */ - - /* adi_ad9083 config */ - - adi,vmax-microvolt = <1800>; - adi,fc-hz = /bits/ 64 <800000000>; - adi,rterm-ohms = <100>; - adi,backoff = <0>; - adi,finmax-hz = /bits/ 64 <100000000>; - adi,nco0_freq-hz = /bits/ 64 <0>; - adi,nco1_freq-hz = /bits/ 64 <0>; - adi,nco2_freq-hz = /bits/ 64 <0>; - adi,cic_decimation = /bits/ 8 ; - adi,j_decimation = /bits/ 8 ; - adi,g_decimation = /bits/ 8 <0>; - adi,h_decimation = /bits/ 8 <0>; - adi,nco0_datapath_mode = /bits/ 8 ; - - /* JESD204 parameters */ - - adi,octets-per-frame = <8>; - adi,frames-per-multiframe = <32>; - adi,converter-resolution = <16>; - adi,bits-per-sample = <16>; - adi,converters-per-device = <16>; - adi,control-bits-per-sample = <0>; - adi,lanes-per-device = <4>; - adi,subclass = <0>; - }; - }; - -Driver testing -============== - -In case the driver probes successfully and the device gets instantiated. Your -systems kernel messages should include some line, which may look like the one -shown below. - -:: - - [ 8.404405] ad9083 spi1.0: AD9083 Rev. 1 Grade 0 (API 1.0.1) probed - -Each and every IIO device, typically a hardware chip, has a device folder under -/sys/bus/iio/devices/iio:deviceX. Where X is the IIO index of the device. Under -every of these directory folders reside a set of files, depending on the -characteristics and features of the hardware device in question. These files are -consistently generalized and documented in the IIO ABI documentation. In order -to determine which IIO deviceX corresponds to which hardware device, the user -can read the name file /sys/bus/iio/devices/iio:deviceX/name. In case the -sequence in which the iio device drivers are loaded/registered is constant, the -numbering is constant and may be known in advance. - -.. container:: box bggreen - - This specifies any shell prompt running on the target - - - :: - - root@analog:/sys/bus/iio/devices# ls - iio:device0 iio:device1 iio:device2 iio_sysfs_trigger - - root@analog:/sys/bus/iio/devices# cd iio:device2 - root@analog:/sys/bus/iio/devices/iio:device2# cat name - axi-ad9083-rx-hpc - root@analog:/sys/bus/iio/devices/iio:device2# ls -l - total 0 - drwxr-xr-x 2 root root 0 Jun 23 08:02 buffer - -r--r--r-- 1 root root 4096 Jun 23 08:02 dev - -rw-r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_ctrl - -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_error - -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_paused - --w------- 1 root root 4096 Jun 23 08:02 jesd204_fsm_resume - -r--r--r-- 1 root root 4096 Jun 23 08:02 jesd204_fsm_state - -r--r--r-- 1 root root 4096 Jun 23 08:02 name - lrwxrwxrwx 1 root root 0 Jun 23 08:02 of_node -> ../../../../../firmware/devicetree/base/fpga-axi0 - drwxr-xr-x 2 root root 0 Jun 23 08:02 power - drwxr-xr-x 2 root root 0 Jun 23 08:02 scan_elements - lrwxrwxrwx 1 root root 0 Jun 23 08:02 subsystem -> ../../../../../bus/iio - -rw-r--r-- 1 root root 4096 Jun 23 08:02 uevent - - -Low level register access via debugfs (direct_reg_access) -========================================================= - -Some IIO drivers feature an optional debug facility, allowing users to read or -write registers directly. Special care needs to be taken when using this -feature, since you can modify registers on the back of the driver. Accessing -debugfs requires root privileges. - -In order to identify if the IIO device in question feature this option you first -need to identify the IIO device number. - -Therefore read the name attribute of each IIO device - -.. container:: box bggreen - - This specifies any shell prompt running on the target - - - :: - - root@analog:/sys/bus/iio/devices# ls - iio:device0 iio:device1 iio:device2 iio_sysfs_trigger - root@analog:/sys/bus/iio/devices# cd iio:device2 - root@analog:/sys/bus/iio/devices/iio:device2# cat name - axi-ad9083-rx-hpc - - -Change directory to /sys/kernel/debug/iio/iio:deviceX and check if the -direct_reg_access file exists. - -.. container:: box bggreen - - This specifies any shell prompt running on the target - - - :: - - root@analog:~# cd /sys/kernel/debug/iio/iio\:device2/ - root@analog:/sys/kernel/debug/iio/iio:device2# ls direct_reg_access - ls direct_reg_access - root@analog:/sys/kernel/debug/iio/iio:device2# - - -Reading - -.. container:: box bggreen - - This specifies any shell prompt running on the target - - - :: - - root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x0 > direct_reg_access - - root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access - 0xAD - root@analog:/sys/kernel/debug/iio/iio:device2# - - -Writing - -Write ADDRESS VALUE - -.. container:: box bggreen - - This specifies any shell prompt running on the target - - - :: - - root@analog:/sys/kernel/debug/iio/iio:device2# echo 0x3D 0x80 > direct_reg_access - root@analog:/sys/kernel/debug/iio/iio:device2# cat direct_reg_access - 0x80 - root@analog:/sys/kernel/debug/iio/iio:device2# - - -More Information -================ - -- IIO mailing list: linux-iio@vger.kernel.org -- `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ -- `IIO Documentation `_ -- :doc:`IIO test and visualization application ` -- :doc:`libiio - IIO system library ` -- :doc:`libiio - Internals ` -- :doc:`Pointers and good books ` -- `IIO High Speed `_ -- `Software Defined Radio using the IIO framework `_ -- - -|libiio introduction| - -*Need Help?* - -- :ez:`Analog Devices Linux Device Drivers Help Forum ` -- `Ask a Question `_ - -.. |libiio introduction| image:: https://wiki.analog.com/_media/software/linux/docs/iio/youtube>p_vntewue24 From af4809f043b8c94000c5a2915c2d210a33877961 Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Tue, 7 Apr 2026 13:47:11 +0300 Subject: [PATCH 4/6] Fix :doc: refs to wiki-migration paths and RST errors Co-Authored-By: Claude Opus 4.6 --- .../reference-designs/eval-ad9083/ad9083.rst | 20 +++++++++---------- .../reference-designs/eval-ad9083/index.rst | 4 +--- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/docs/solutions/reference-designs/eval-ad9083/ad9083.rst b/docs/solutions/reference-designs/eval-ad9083/ad9083.rst index e1acad59624..46f8ddd5ab9 100644 --- a/docs/solutions/reference-designs/eval-ad9083/ad9083.rst +++ b/docs/solutions/reference-designs/eval-ad9083/ad9083.rst @@ -14,7 +14,7 @@ Supported Boards Supported HDL Cores ------------------- -- :doc:`AD9083 FMC Card HDL Reference Design ` +- `AD9083 FMC Card HDL Reference Design `_ Description ----------- @@ -72,8 +72,8 @@ Example device trees Interrelated Device Drivers ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :doc:`JESD204 (FSM) Interface Linux Kernel Framework ` -- :doc:`JESD204 Interface Framework ` +- `JESD204 (FSM) Interface Linux Kernel Framework `_ +- `JESD204 Interface Framework `_ Transport Layer Receive AXI-ADC driver ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -88,7 +88,7 @@ Transport Layer Receive AXI-ADC driver | include | :git-linux:`drivers/iio/adc/cf_axi_adc.h` | +----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -**Documentation:** :doc:`AXI ADC HDL Linux Driver ` +**Documentation:** `AXI ADC HDL Linux Driver `_ Link Layer AXI JESD204B HDL driver ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -104,7 +104,7 @@ Link Layer AXI JESD204B HDL driver **Documentation:** - `JESD204B/C Transmit Linux Driver `_ -- :doc:`JESD204B/C Receive Linux Driver ` +- `JESD204B/C Receive Linux Driver `_ PHY Layer AXI JESD204B GT (Gigabit Tranceiver) HDL driver (XILINX/ALTERA-INTEL) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -117,7 +117,7 @@ PHY Layer AXI JESD204B GT (Gigabit Tranceiver) HDL driver (XILINX/ALTERA-INTEL) **Documentation:** -- :doc:`JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver ` +- `JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver `_ Enabling Linux driver support ============================= @@ -337,10 +337,10 @@ More Information - IIO mailing list: linux-iio@vger.kernel.org - `IIO Linux Kernel Documentation sysfs-bus-iio-\* `_ - `IIO Documentation `_ -- :doc:`IIO test and visualization application ` -- :doc:`libiio - IIO system library ` -- :doc:`libiio - Internals ` -- :doc:`Pointers and good books ` +- `IIO test and visualization application `_ +- `libiio - IIO system library `_ +- `libiio - Internals `_ +- `Pointers and good books `_ - `IIO High Speed `_ - `Software Defined Radio using the IIO framework `_ - diff --git a/docs/solutions/reference-designs/eval-ad9083/index.rst b/docs/solutions/reference-designs/eval-ad9083/index.rst index 1d50a63a93f..06a868b564c 100644 --- a/docs/solutions/reference-designs/eval-ad9083/index.rst +++ b/docs/solutions/reference-designs/eval-ad9083/index.rst @@ -24,9 +24,7 @@ Applications: :hidden: ad9083 - ad9083 - -Recommendations + Recommendations ------------------------------------------------------------------------------- People who follow the flow that is outlined, have a much better experience with From 722e8253a93daa6840652444683b269fe4bb4c47 Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Tue, 7 Apr 2026 15:32:32 +0300 Subject: [PATCH 5/6] Fix remaining build errors (includes, tables, toctree) Co-Authored-By: Claude Opus 4.6 --- docs/solutions/reference-designs/eval-ad9083/index.rst | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/solutions/reference-designs/eval-ad9083/index.rst b/docs/solutions/reference-designs/eval-ad9083/index.rst index 06a868b564c..8a8aef1323e 100644 --- a/docs/solutions/reference-designs/eval-ad9083/index.rst +++ b/docs/solutions/reference-designs/eval-ad9083/index.rst @@ -24,7 +24,6 @@ Applications: :hidden: ad9083 - Recommendations ------------------------------------------------------------------------------- People who follow the flow that is outlined, have a much better experience with From 0f8aa915c441e347d1aab6459986cf0354845653 Mon Sep 17 00:00:00 2001 From: Vicentiu Neagoe Date: Tue, 7 Apr 2026 15:57:17 +0300 Subject: [PATCH 6/6] Fix build: index.rst blank line before section heading Co-Authored-By: Claude Opus 4.6 --- docs/solutions/reference-designs/eval-ad9083/index.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/solutions/reference-designs/eval-ad9083/index.rst b/docs/solutions/reference-designs/eval-ad9083/index.rst index 8a8aef1323e..7dc9e71cb9f 100644 --- a/docs/solutions/reference-designs/eval-ad9083/index.rst +++ b/docs/solutions/reference-designs/eval-ad9083/index.rst @@ -24,6 +24,7 @@ Applications: :hidden: ad9083 + ------------------------------------------------------------------------------- People who follow the flow that is outlined, have a much better experience with