diff --git a/docs/solutions/reference-designs/eval-ad9694/ad9694-500ebz.rst b/docs/solutions/reference-designs/eval-ad9694/ad9694-500ebz.rst new file mode 100644 index 00000000000..202aeeddaf0 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/ad9694-500ebz.rst @@ -0,0 +1,587 @@ +.. _ad9694 evaluating: + +EVALUATING THE AD9694 QUAD CHANNEL 500 MSPS ADC +=============================================== + +Preface +------- + +This user guide describes the :adi:`AD9694` evaluation board :adi:`AD9694-500EBZ +` which provides all of the support circuitry required to operate the +ADC in its various modes and configurations. The application software used to +interface with the devices is also described. The user guide wiki applies to the +follow evaluation boards: + ++------------------------------+---------------------------------+----------------+ +| Evaluation Board Part Number | Description | Board Revision | ++==============================+=================================+================+ +| AD9694-500EBZ | Evaluation board for AD9694-500 | 9694CE04A | ++------------------------------+---------------------------------+----------------+ + +| The :adi:`AD9694` data sheet provides additional information and should be + consulted when using the evaluation board. All documents and software tools + are available at :adi:`www.analog.com/hsadcevalboard `. For + additional information or questions, send an email to + highspeed.converters@analog.com. + +AD9694 Evaluation Board +----------------------- + +The images below show the location and position of the jumpers on the old (first +image) and new (second image) versions of the :adi:`AD9694-500EBZ `. + +|image1| + +.. container:: centeralign + + :adi:`AD9694` *Evaluation Board (old version)*\ + + |image2| + +.. container:: centeralign + + :adi:`AD9694` *Evaluation Board (new version)*\ + +Typical Measurement Setup +------------------------- + +The :adi:`AD9694-500EBZ ` can be evaluated using the `ADS7-V2EBZ +`_ FPGA data capture board. The figures below +show the :adi:`AD9694-500EBZ ` connected to the `ADS7-V2EBZ +`_. If using the old version of the board, +refer to the first image for connections, otherwise if using the new version of +the board, refer to the second image. + +|image3| + +.. container:: centeralign + + *(Old) Evaluation Board Connection—*\ :adi:`AD9694-500EBZ ` + + |image4| + +.. container:: centeralign + + *(New) Evaluation Board Connection—*\ :adi:`AD9694-500EBZ ` + +Features +-------- + +- Full featured evaluation board for the :adi:`AD9694` +- SPI interface for setup and control +- Wide band Balun driven input +- External supply powered but may also use 12V-1A and 3.3V-3A supplies from FMC +- VisualAnalog® and SPI controller software interfaces + +Helpful Documents +----------------- + +- :adi:`AD9694` Data Sheet +- ADS7-V2EBZ evaluation kit (`ADS7-V2EBZ `_) +- :adi:`AN-905 Application Note `, *VisualAnalog Converter Evaluation + Tool Version 1.0 User Manual* +- :adi:`AN-878 Application Note `, *High Speed ADC SPI Control + Software* +- `ADI SPI Application Note + `_ // ADI Serial + Control Interface Standard// +- :adi:`AN-835 Application Note `, *Understanding ADC Testing and + Evaluation* + +Software Needed +--------------- + +- VisualAnalog `visualanalog_setup.exe + `_ +- ACE `ace `_ + +Design and Integration Files +---------------------------- + +- `AD9694CE04A schematic, BOM, layout files + `_ + +Equipment Needed +---------------- + +- Analog signal source and antialiasing filter +- Sample clock source +- 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 + supplied with `ADS7-V2EBZ `_/`ADS7-V1EBZ + `_) +- PC running Windows® +- USB 2.0 port +- :adi:`AD9694-500EBZ ` board +- `ADS7-V2EBZ `_ FPGA-based data capture kit + +Getting Started +--------------- + +This section provides quick start procedures for using the evaluation board for +AD9694. + +Configuring the Board +~~~~~~~~~~~~~~~~~~~~~ + +Before using the software for testing, configure the evaluation board as +follows: + +- Connect the evaluation board to the `ADS7-V2EBZ + `_ data capture board, as shown in the + figure for the **Evaluation Board Connection**. +- Make sure the jumpers are placed on the evaluation board as highlighted in + green in the figure **AD9694 Evaluation Board**. +- Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 + supplied) to P4 on the `ADS7-V2EBZ `_ board. + Connect the Standard-B USB port of the `ADS7-V2EBZ + `_ board to the PC with the supplied USB + cable. +- Turn on the `ADS7-V2EBZ `_. +- The `ADS7-V2EBZ `_ will appear in the Device + Manager. + +.. image:: images/9694_ads7v2_devmgr.png + :align: center + :width: 300 + +.. container:: centeralign + + \ *Device Manager showing* `ADS7-V2EBZ `_\ + +- If the Device Manager does not show the `ADS7-V2EBZ + `_ listed, unplug all USB devices from the + PC, uninstall and re-install SPIController and VisualAnalog and restart the + hardware setup from step 1. +- On the ADC evaluation board, provide a clean, low jitter 1GHz clock source to + connector J203 and set the amplitude to 14dBm. This is the ADC Sample Clock. +- On the `ADS7-V2EBZ `_ data capture board, + provide a clean, low jitter clock source to connector J3 and set the + amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers + in the FPGA. The REFCLK frequency can be calculated using the following + empirical formulae: + +.. container:: centeralign + + :math:`\displaystyle LaneLineRate=M \times Nprime \times (\frac{10}{8}) + \times f_{out}/L` bps/lane, where + +.. container:: centeralign + + :math:`f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16` + *(Default Nprime = 16)*\ + +.. container:: centeralign + + :math:`REFCLK = LaneLineRate/20` + +- On the ADC evaluation board, use a clean signal generator with low phase + noise to provide an input signal for channel A to J101. Use a shielded, + RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC + Evaluation Board. For best results, use a narrow-band, band-pass filter with + 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen + Avionics, and K & L band-pass filters.) If providing an input clock with a + divide-by-1 setting in the AD9694 make sure the clock source has a 50% duty + cycle. For optimum SNR performance use the clock divider with a divide ratio + of 2 or higher to minimize the impact of the phase noise from the input clock + source. +- On the ADC evaluation board, use a clean signal generator with low phase + noise to provide an input signal for channel B to J102. Use a shielded, + RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC + Evaluation Board. For best results, use a narrow-band, band-pass filter with + 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen + Avionics, and K & L band-pass filters.) +- On the ADC evaluation board, use a clean signal generator with low phase + noise to provide an input signal for channel C to J104. Use a shielded, + RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC + Evaluation Board. For best results, use a narrow-band, band-pass filter with + 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen + Avionics, and K & L band-pass filters.) +- On the ADC evaluation board, use a clean signal generator with low phase + noise to provide an input signal for channel D to J107. Use a shielded, + RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC + Evaluation Board. For best results, use a narrow-band, band-pass filter with + 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen + Avionics, and K & L band-pass filters.) + +Visual Analog Setup +~~~~~~~~~~~~~~~~~~~ + +- Click Start :math:`right` All Programs :math:`right` Analog Devices + :math:`right` VisualAnalog :math:`right` VisualAnalog +- On the VisualAnalog “New Canvas” window, and select the desired canvas. + **Note: The current canvases for VisualAnalog only support operating both + pairs of channels in the AD9694 in the same chip operating mode with the same + decimation rate. If Pair AB is in full bandwidth mode then Pair CD must also + be in full bandwidth mode. If Pair AB is in real DDC0/DDC1 mode with a + decimation rate of 2 then pair CD must also be in real DDC0/DDC1 mode with a + decimation rate of 2.** + +.. image:: images/newcanvas9694.jpg + :align: center + +.. container:: centeralign + + *Selecting the :adi:`AD9694` canvas* + +- Next, program the FPGA in VisualAnalog by clicking into the **ADC Data + Capture Settings** block and selecting the **Capture Board** tab. Use the + **Browse** button to navigate to the **ad9694_ads7v2.bin** file and then + click **Program**. The **FPGA_DONE** LED should illuminate on the ADS7-V1 + board indicating that the FPGA has been correctly programmed. + +.. image:: images/9694_program_fpga.png + :align: center + +.. container:: centeralign + + \ *Programming the* `ADS7-V2EBZ `_\ + +- Click the **General** button in the **ADC Data Capture Settings** block. On + the **General** tab make sure the clock frequency is set to match the sample + clock. For example, if the sample clock of the AD9694 is 368.64 MHz then set + the **Clock Frequency (MHz)** to 368.64 MHz. The FFT capture length may be + changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA + software supports up to 2M FFT capture (1M per channel). + +.. image:: images/9694_data_capture_settings_general.png + :align: center + +.. container:: centeralign + + \ *Changing the ADC Capture Settings*\ + +- If VisualAnalog opens with a collapsed view, click on the “Expand Display” + icon (see figure 5) + +.. image:: images/fig4_expand_display.png + :align: center + +.. container:: centeralign + + \ *Expanding Display in VA*\ + +- On the **Device** tab. Make sure that **Enable Alternate REFCLK** option is + checked. +- Click **OK** + +ACE Setup +~~~~~~~~~ + +- Click Start :math:`right` All Programs :math:`right` Analog Devices + :math:`right` ACE :math:`right` ACE +- Once ACE opens the AD9694 evaluation board should appear in the **Attached + Hardware** section. + +.. image:: images/9694_ace_start.png + :align: center + +.. container:: centeralign + + *ACE Attached Hardware: AD9694* + +- Double click on the **AD9694 Eval Board** icon which will open up the Initial + Configuration wizard. The default conditions for the AD9694 are Full BW mode + with a sample clock of 500 MHz. From here both pairs of ADC channels (Pair AB + and Pair CD) can be configured simultaneously. **NOTE:It is important to + remember that the AD9694 functions as two dual ADCs.** + +.. image:: images/9694_ace_initial_config.png + :align: center + +.. container:: centeralign + + \ *ACE - AD9694 Initial Configuration Wizard*\ + +- Prior to configuring any modes in the AD9694 double click on the **AD9694** + icon to bring up the device view. From the device view click on the **Read + All** icon to read the SPI settings from the device. Do this for each pair by + selecting one pair at a time and then clicking the **Read All** icon. + +.. image:: images/9694_ace_device_view_read_all.png + :align: center + +.. container:: centeralign + + \ *ACE - AD9694 Initial Configuration Wizard*\ + +- From the the **Initial Configuration Wizard** the clock frequency, chip + application mode (per pair), DDC inputs and outputs, and the JESD204B + settings can be quickly configured. The default conditions are: + + - Clock Input = **1 GHz** + - Clock Divider = **Divide by 2** + - Chip Operating Mode = **Full Bandwidth Mode** + - JESD204B Parameters: **L.M.F = 2.2.2** ; **N' = 16** + +- All these parameters can be seen below: + +.. image:: images/9694_ace_initial_config_204b.png + :align: center + +.. container:: centeralign + + \ *ACE - AD9694 Initial Configuration Wizard Showing JESD204B Parameters*\ + +Device Setup - Full BW Mode +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The default Chip Application Mode for the AD9694-500 is Full BW mode. In this + example the clock frequency will be set to **500 MHz**, the clock divider set + to **Divide by 1**, and the chip operating mode set to **Full BW Mode**. Once + the settings have been entered, click **Apply**. This will configure the + device with the selected settings and provide an **Initial Configuration + Summary** which will summarize the settings that have been loaded into the + AD9694 and also provide the frequency for the required FPGA reference clock. + +.. image:: images/9694_ace_initial_config_apply.png + :align: center + +.. container:: centeralign + + \ *Default Application Mode - Full BW Mode*\ + +- In order to change the settings for each channel, double-click on the AD9694 + icon from the **AD9694 Eval Board** view (highlighted in the figure below). + +.. image:: images/9694_ace_initial_config_highlight.png + :align: center + +.. container:: centeralign + + \ *Double-click the AD9694 Icon in the Eval Board View*\ + +- This will bring up the AD9694 device view showing more specific settings for + each pair and channel. The device view shows one pair of the AD9694 at a + time. The **ADC Pair Selection** drop down box is used to select the current + pair. To select the desired pair (Pair AB or Pair CD) select the desired pair + form the drop down box. This sets the current changes to affect the select + pair only. The settings can now be configured for each channel. Once the + settings are configured click **Apply Changes** in the upper left of the + device view. This will load the setting changes to the selected ADC pair and + channel(s). If the settings are desired for all four channels then click the + **Apply** button in the **AD9694 Configuration** window on the left of the + screen. This loads the current settings to all channels in the device. + +.. image:: images/9694_ace_device_view_fullbw.png + :align: center + +.. container:: centeralign + + \ *Figure 15. Pair AB - Channel A and Channel B NSR Settings*\ + +- The device view in ACE also has controls for the analog input controls. The + input buffer current, input full-scale voltage, and analog input differential + termination can be adjusted. The analog inputs can also be disabled from this + menu. + +.. image:: images/9694_ace_device_view_analog_input_controls.png + :align: center + +.. container:: centeralign + + \ *Analog Input Control Settings*\ + +- The **Memory Map View** can be accessed from the AD9694 **Device View**. The + **Memory Map View** can be used to individually write registers in the + AD9694. **Note: When writing individual registers it is imperative to first + write the Pair Index register (0x0009) before any other write so that the + correct ADC channel pair (Pair AB or Pair CD) is being addressed. If writing + a local register, subsequently write the ADC channel index register (0x0008) + so that the desired channel within the desired pair is written (Channel A/C + or Channel B/D).** + +.. image:: images/9694_ace_memorymap_view.png + :align: center + +.. container:: centeralign + + \ *Memory Map View*\ + +Obtaining an FFT - Full BW Mode +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The first item to configure in Visual Analog is the input clock frequency. + This needs to be set to twice the frequency of the input clock. Click in the + ADC Data Capture block to open the settings. In this example, 500 MHz is the + input clock frequency so 1000 is entered into VisualAnalog. + +.. image:: images/9694_data_capture_settings_general_1000.png + :align: center + +.. container:: centeralign + + \ *AD9694 FFT Data Capture Settings*\ + +- In this example, with an input clock of 500MHz, the output sample rate is + 500MSPS. The default JESD204B lane configuration for the JESD204B link of + each ADC Channel Pair is 2.2.2 (L.M.F). The required REFCLK frequency is 500 + MHz (refer to step 7 in the section "Configuring the Board"). +- Click the Run button in Visual Analog and you should see the capture data + similar to the plot below. + +.. image:: images/9694_fullbw_fft_fin70mhz.png + :align: center + :width: 800 + +.. container:: centeralign + + \ *AD9694 FFT with NSR Enabled (Tuning Word = 58*\ + +- Adjust the amplitude of the input signal so that the fundamental is at the + desired level. (Examine the **Fund Power** reading in the left panel of the + VisualAnalog FFT window.) NSR imposes a ~3dB loss in the signal, but does not + impact the dynamic range. A -1.0 dBFS input signal will show as -4.0 dBFS in + the FFT in Visual Analog. +- To save the FFT plot do the following + + - Click on the Float Form button in the FFT window + +.. image:: images/fig13_floatform.png + :align: center + +.. container:: centeralign + + \ *Floating the FFT window*\ + +- Click on File :math:`right` Save Form As button and save it to a location of + choice + +.. image:: images/6684_va_fft_saveas.png + :align: center + +.. container:: centeralign + + \ *Saving the FFT*\ + +Device Setup - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The default Chip Application Mode for the AD9694 is full bandwidth mode. The + AD9694 settings must be changed to configure the AD9694 into DDC mode. To set + up the AD9694 for DDC mode change the Chip Application Mode to **DDC0** in + the **Initial Configuration** window in the **AD9694 Eval Board** view in ACE + and click **Apply**. (**Note: Due to the software limitation in VisualAnalog, + both ADC pairs (AB and CD) must be set to the same operating mode and same + decimation rate.**) + +.. image:: images/9694_ace_initial_config_1ddc_complexinout.png + :align: center + +.. container:: centeralign + + \ *Set Application Mode to DDC0*\ + +- The DDC settings can be configured from the **Device View** in ACE. In this + example a complex input signal is being input to the AD9694, I data is on + Channel A/C and Q data is on Channel B/D. See the AD9694 data sheet for more + details on the available DDC modes and decimation rates. To access the device + view, double-click the **AD9694** icon from the **AD9694 Eval Board** view + which will bring up the view below. In this example DDC0 is set to complex + mode with the NCO in Variable IF mode and the tuning frequency set to 230MHz + (the input frequency to the AD9694 is 270.1 MHz). Once the settings have been + entered click **Apply Changes** in the upper left of the **Device View**. + This will apply changes to the ADC Pair (Pair AB or Pair CD) selected in the + **Device View**. + +.. image:: images/9694_ace_device_view_1ddc_complexinout.png + :align: center + +.. container:: centeralign + + \ *Pair AB: Channel A and Channel B DDC0 Settings*\ + +- Once again, make sure that Pair CD has the same DDC mode as Pair AB (due to + VisualAnalog software limitation). The NCO tuning and NCO mode can be + different between Pair AB and Pair CD, but the pairs must both be set to + complex mode or to real mode and the decimation rates must be the same. To do + so, set the **ADC Pair Selection** to the desired pair, configure the block + diagram as desired and click **Apply Changes** in the upper left of the + window. This should be done for each pair (Pair AB and Pair CD). + +.. image:: images/9694_ace_device_view_1ddc_complexinout_paircd.png + :align: center + +.. container:: centeralign + + \ *Pair CD: Channel C and Channel D DDC0 Settings*\ + +- When making changes to the DDC settings the **DDC Soft Reset** must be + written afterwards. To do so, select **DDC Held in Reset** from the drop down + menu in the block diagram. Then click **Apply Changes** in the upper left of + the AD9694 Device view in ACE. Next, select **Normal Operation** from the + drop down menu in the block diagram and then click **Apply Changes** once + again. This process resets the DDC and then places the DDC back into normal + operating mode. This must be done for each pair (Pair AB and/or Pair CD) for + which DDC changes have been applied. + +.. image:: images/9694_ace_device_view_1ddc_complexinout_ddc_softreset.png + :align: center + +.. container:: centeralign + + \ *Pair AB: Channel A and Channel B DDC0 Settings with DDC Soft Reset*\ + +Obtaining an FFT - 1 DDC Per ADC Pair in Complex Mode with Decimation by 2 Mode +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The first item to configure in Visual Analog is the input clock frequency. + This needs to be set to twice the frequency of the input clock. Click in the + ADC Data Capture block to open the settings. In this example, 368.64 MHz is + the sample clock frequency so 368.64 is entered into VisualAnalog. Also, make + sure that the output data is set to \*Ch. DDC0 Data\*. + +.. image:: images/6684_data_capture_settings_ddc0.png + :align: center + +.. container:: centeralign + + \ *AD9694 FFT Data Capture Settings*\ + +- In this example, with a sample clock of 368.64MHz, the output sample rate is + 184.32MSPS. The JESD204B lane configuration for the JESD204B link of each ADC + Channel Pair is 2.4.4 (L.M.F). The required REFCLK frequency is 368.64 MHz + (refer to step 7 in the section "Configuring the Board"). +- Click the Run button in Visual Analog and you should see the capture data + similar to the plot below. + +.. image:: images/9694_2ddc_complex_inout_ncopassthrough_fft_fin345p1mhz.png + :align: center + :width: 800 + +.. container:: centeralign + + \ *AD9694 FFT with DDC0 Enabled*\ + +- Adjust the amplitude of the input signal so that the fundamental is at the + desired level. (Examine the **Fund Power** reading in the left panel of the + VisualAnalog FFT window.) Adjust the input signal to -1.4 dBFS or less in the + FFT in Visual Analog (this accounts for the approximately -0.4 dB loss in the + DDC. Recall that the mixing process incurs a 6dB additional loss; the signal + amplitude is -7.4 dBFS in this plot. +- To save the FFT plot do the following + + - Click on the Float Form button in the FFT window + +.. image:: images/fig13_floatform.png + :align: center + +.. container:: centeralign + + \ *Floating the FFT window*\ + +- Click on File :math:`right` Save Form As button and save it to a location of + choice + +.. image:: images/6684_va_fft_saveas.png + :align: center + +.. container:: centeralign + + \ *Saving the FFT*\ + +.. |image1| image:: images/ad9694_jumpers.jpg +.. |image2| image:: images/ad9694_jumpers_new_board.jpg +.. |image3| image:: images/ad9694_connection.png + :width: 800 +.. |image4| image:: images/ad9694_connection_new_board.jpg + :width: 800 diff --git a/docs/solutions/reference-designs/eval-ad9694/images/6684_data_capture_settings_ddc0.png b/docs/solutions/reference-designs/eval-ad9694/images/6684_data_capture_settings_ddc0.png new file mode 100644 index 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100644 index 00000000000..f1784343272 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/images/newcanvas9694.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:13994e6b31dae6222016aee3639312ab7e6fe82b6c0f2cda7ec91b087b92c9e3 +size 67987 diff --git a/docs/solutions/reference-designs/eval-ad9694/index.rst b/docs/solutions/reference-designs/eval-ad9694/index.rst new file mode 100644 index 00000000000..b3caa4651a9 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/index.rst @@ -0,0 +1,155 @@ +.. _eval-ad9694: + +EVAL-AD9694 +=============================================================================== + +14-Bit, 500 MSPS, Quad, JESD204B Analog-to-Digital Converter Evaluation Board. + +.. image:: images/ad9694-chip-illustration.png + :align: left + :width: 150 + +Overview +------------------------------------------------------------------------------- + +The :adi:`AD9694-500EBZ` is a full-featured evaluation board for the +:adi:`AD9694`, a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC) with a +JESD204B serial interface. The device is organized as two dual ADC pairs (Pair +AB and Pair CD). + +The board provides all support circuitry required to operate the AD9694 in its +various modes and configurations. It connects to an FPGA carrier board running +ADI Kuiper Linux with IIO-based software tools. + +Features: + +- JESD204B coded serial digital outputs with support for lane rates up to 15 + Gbps/lane +- Wide full-power bandwidth supports IF sampling of signals up to 1.4 GHz +- Four integrated wideband decimation filters and NCO blocks supporting + multiband receivers +- Buffered inputs ease filter design and implementation +- Programmable fast overrange detection and signal monitoring +- On-chip temperature diode for system thermal management + +Applications: + +- Multi-band, multi-mode receivers +- Radar and electronic warfare +- Instrumentation and test equipment +- Software-defined radio (SDR) + +.. figure:: images/ad9694-500ebzangle-evaluation-board.jpg + :align: center + :width: 500 + + AD9694-500EBZ + +.. toctree:: + :hidden: + + user-guide + prerequisites + quickstart/index + ad9694-500ebz + +Recommendations +------------------------------------------------------------------------------- + +People who follow the flow that is outlined, have a much better experience with +things. However, like many things, documentation is never as complete as it +should be. If you have any questions, feel free to ask on our :ref:`EngineerZone +forums `, but before that, please make sure you read our +documentation thoroughly. + +To better understand the :adi:`AD9694`, we recommend using the +:adi:`AD9694-500EBZ` evaluation board. + +Table of contents +------------------------------------------------------------------------------- + +#. Using the evaluation board/full stack reference design that we offer: + + #. :ref:`ad9694 user-guide` --- hardware guide for the evaluation board + #. :ref:`Prerequisites ` --- what you need to get + started + #. :ref:`Quick start guides `: + + #. Using the :ref:`ZCU102/Zynq UltraScale+ MPSoC ` + + #. Configure an SD Card with :external+kuiper:doc:`Kuiper ` + + #. Linux Applications + + #. :ref:`iio-oscilloscope` + +#. Design with the AD9694 + + - :ref:`ad9694 block-diagram` + + - :adi:`AD9694 product page ` + + - Resources for designing a custom AD9694-based platform + + #. For Linux software: + + #. About the device driver: + + - :dokuwiki:`AD9694 Linux IIO ADC driver + ` + - :dokuwiki:`JESD204B Receive Linux driver + ` + - :dokuwiki:`JESD204B/C AXI_ADXCVR High-speed transceivers Linux + driver ` + - :dokuwiki:`AXI ADC HDL Linux driver + ` + - :dokuwiki:`AXI-DMAC DMA Controller Linux driver + ` + + #. About the device tree: + + - :dokuwiki:`Customizing the device tree on the target + ` + + #. About the JESD204 utilities: + + - :dokuwiki:`JESD204 (FSM) Interface Linux Kernel Framework + ` + - :dokuwiki:`JESD204 status utility + ` + - :external+hdl:ref:`jesd204` + + #. :external+hdl:ref:`HDL reference design ` which you must use + in your FPGA. + +#. :ref:`Help and Support ` + +.. _ad9694 block-diagram: + +Block diagram +------------------------------------------------------------------------------- + +.. image:: images/ad9694-fbl.png + :align: center + :width: 500 + +ADI articles +------------------------------------------------------------------------------- + +About the JESD204 standard: + +#. :adi:`JESD204B Survival Guide + ` +#. :adi:`JESD204C Primer: What's New and in It for You---Part 1 ` +#. :adi:`JESD204C Primer: What's New and in It for You---Part 2 ` + +Warning +------------------------------------------------------------------------------- + +.. esd-warning:: + +Help and support +------------------------------------------------------------------------------- + +Please go to :ref:`Help and Support ` page. diff --git a/docs/solutions/reference-designs/eval-ad9694/prerequisites.rst b/docs/solutions/reference-designs/eval-ad9694/prerequisites.rst new file mode 100644 index 00000000000..f7fc4f633e7 --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/prerequisites.rst @@ -0,0 +1,69 @@ +.. _ad9694 prerequisites: + +Prerequisites +=============================================================================== + +What you need, depends on what you are trying to do. As a minimum, you need to +start out with: + +Hardware prerequisites +------------------------------------------------------------------------------- + +#. The AD9694-based evaluation board: :adi:`AD9694-500EBZ ` +#. An FPGA carrier platform. Our recommended one can be found :ref:`here `. + +#. Some way to interact with the FPGA platform: + + - Micro-USB cable for UART console + - LAN cable (Ethernet) for SSH or IIO applications + - HDMI or DisplayPort monitor (Optional) + - USB Keyboard (Optional) + - USB Mouse (Optional) + +#. A clock source, any low-noise clock generator with multiple outputs can be + used. The following items are needed only if using the + :adi:`AD-SYNCHRONA14-EBZ `: + + - :adi:`AD-SYNCHRONA14-EBZ ` clock source board + (Optional) + - Serial port module for the AD-SYNCHRONA14-EBZ serial interface (Optional) + - 20-pin GPIO ribbon cable for serial communication between the ZCU102 and + the AD-SYNCHRONA14-EBZ, connected pin-to-pin, all 20 pins (Optional) + - 4x SMA 50 Ohm terminators for unused AD-SYNCHRONA14-EBZ output channels + (Optional) + +#. SMA cables (for connections between the clock source, AD9694, and signal + generator) +#. Low phase noise signal generator with antialiasing filter (analog input + source) +#. ZCU102 power supply (12 V) +#. SD card with at least 16 GB of memory + +Software prerequisites +------------------------------------------------------------------------------- +The following software is needed on the host PC: + +.. note:: + + Pre-built files for this reference design are not yet available. The files + must be built manually using the links above. Official release artifacts will + be provided here once available. For now, check: :external+hdl:ref:`Build an + HDL project ` and :ref:`Build the Linux kernel ` + +#. SD card 16 GB imaged with :external+kuiper:doc:`Kuiper ` (check out + that guide on how to do it, then come back here). +#. A UART terminal (PuTTY/Tera Term/Minicom), 115200 baud, 8N1. +#. :ref:`iio-oscilloscope` for data visualization. + +For capturing and visualizing data from the device: + +#. :external+scopy:doc:`Scopy ` v2.0 or later (must contain the IIO + plugin) +#. :doc:`IIO Oscilloscope `, a graphical tool + for capturing and visualizing IIO device data + +.. note:: + + :adi:`ADI <>` does not offer FPGA carrier platforms for sale or loan; getting + one yourself is the normal part of development or evaluation. diff --git a/docs/solutions/reference-designs/eval-ad9694/quickstart/index.rst b/docs/solutions/reference-designs/eval-ad9694/quickstart/index.rst new file mode 100644 index 00000000000..5680e5759fd --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/quickstart/index.rst @@ -0,0 +1,62 @@ +.. _ad9694 quickstart: + +Quickstart +=============================================================================== + +The quick start guides provide simple step-by-step instructions on how to do an +initial system setup for the :adi:`AD9694-500EBZ` board using various evaluation +platforms. + +.. toctree:: + :maxdepth: 1 + + On ZCU102 + +.. _ad9694 carriers: + +Supported carriers +------------------------------------------------------------------------------- + +The :adi:`AD9694-500EBZ` is an FMC card; it needs a carrier to plug into. + +The carriers we support are: + +.. list-table:: + :header-rows: 1 + + * - Platform + - Connector + - Notes + * - :xilinx:`ZCU102` + - FMC HPC1 + - FPGA carrier, Kuiper Linux + +Supported environments +------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Platform + - HDL + - Linux software + - No-OS software + * - :xilinx:`ZCU102` + - Yes + - Yes + - No + +Hardware setup +------------------------------------------------------------------------------- + +On the ZCU102, the :adi:`AD9694-500EBZ` connects to the **FMC HPC1** connector. +The carrier setup requires power, UART (115200 baud), Ethernet (Linux), and SMA +cables for analog inputs and clock sources. + +ZCU102 + AD9694-500EBZ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: ../images/ad9694_zcu102_setup.png + :width: 800 + +Go to :ref:`the ZCU102 quickstart guide `. diff --git a/docs/solutions/reference-designs/eval-ad9694/quickstart/zcu102.rst b/docs/solutions/reference-designs/eval-ad9694/quickstart/zcu102.rst new file mode 100644 index 00000000000..3fadc225cae --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/quickstart/zcu102.rst @@ -0,0 +1,240 @@ +.. _ad9694 quickstart zcu102: + +ZCU102 Quickstart +=============================================================================== + +This guide provides step-by-step instructions on how to set up the +:adi:`AD9694-500EBZ` on: + +- :xilinx:`ZCU102` on FMC HPC1 + +.. image:: ../../images/zcu102.jpg + :width: 900 + +.. esd-warning:: + +Using Linux as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. note:: + + Pre-built files for this reference design are not yet available. + The files must be built manually using the links above. Official release + artifacts will be provided here once available. For now, check: + :external+hdl:ref:`Build an HDL project ` and + :ref:`Build the Linux kernel ` + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``Image`` +- Linux device tree: ``system.dtb`` + +They are manually generated by following the instructions below. + +- Instructions on how to manually build the boot files from source can be found + here: + + - :ref:`linux-kernel zynqmp` + - :external+hdl:ref:`ad9694_fmc` build documentation. More HDL build details + at :external+hdl:ref:`build_hdl`. + + +Required software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- SD card 16 GB imaged with :external+kuiper:doc:`Kuiper ` (check out + that guide on how to do it, then come back to this section) +- A UART terminal (PuTTY/Tera Term/Minicom) with baud rate 115200 (8N1) + +Required hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZCU102` Rev 1.0 FPGA board and its power supply (12 V) +- :adi:`AD9694-500EBZ ` FMC evaluation board +- A clock source, any low-noise clock generator with multiple outputs can be + used. The following items are needed only if using the + :adi:`AD-SYNCHRONA14-EBZ `: + + - :adi:`AD-SYNCHRONA14-EBZ ` clock source board (Optional) + - Serial port module for the AD-SYNCHRONA14-EBZ serial interface (Optional) + - 20-pin GPIO ribbon cable for serial communication between the ZCU102 and the + AD-SYNCHRONA14-EBZ, connected pin-to-pin, all 20 pins (Optional) + - 4x SMA 50 Ohm terminators for unused AD-SYNCHRONA14-EBZ output channels + (Optional) + +- SMA cables (for connections between the clock source, AD9694, and signal + generator) +- Low phase noise signal generator with antialiasing filter (analog input + source) +- SD card with at least 16 GB of memory +- Micro-USB cable (UART, J83) +- LAN cable (Ethernet) +- (Optional) USB keyboard and mouse, HDMI-compatible monitor + +More details as to why you need these can be found at :ref:`ad9694 +prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +AD9694/ZCU102 +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +.. image:: ../images/ad9694_zcu102_setup.png + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +.. note:: + + The AD‑SYNCHRONA14‑EBZ module is optional. Users may use any alternative + clock source as required by their setup. + +#. Set up the :adi:`AD-SYNCHRONA14-EBZ ` clock source: + + The AD-SYNCHRONA14-EBZ provides all clocks required for this setup. Refer to + the :ref:`AD-SYNCHRONA14-EBZ ` for board setup and GUI + installation instructions. + + Once the Synchrona GUI is open (as described in the GUI section of that + guide), configure the output channels as follows: + + - Enable channels **3**, **5**, and **6**. + - Set the output frequencies: + + .. list-table:: + :header-rows: 1 + + * - Channel + - Frequency (Hz) + * - 3 + - 3906250 + * - 5 + - 250000000 + * - 6 + - 1000000000 + + - Click **Reload Config** to apply the settings. + + Connect the GPIO serial port of the AD-SYNCHRONA14-EBZ to the ZCU102 using + the 20-pin ribbon cable, **pin-to-pin** (all 20 pins connected directly, + 1-to-1). + +#. Prepare the :adi:`AD9694-500EBZ`: + + - Configure the jumpers as described in the :ref:`ad9694 user-guide` hardware + configuration section. + - Connect channel 9 output of the AD-SYNCHRONA14-EBZ to **J203** (500 MHz ADC + sample clock, 50 Ohm coaxial cable). + - Connect channel 10 output of the AD-SYNCHRONA14-EBZ to the ZCU102 reference + clock input (250 MHz JESD204B reference clock). + - Connect the signal source to **J101** (Channel A) and/or **J102** (Channel + B), **J104** (Channel C), **J107** (Channel D) via an antialiasing filter. + +#. Plug the :adi:`AD9694-500EBZ` into the **FMC HPC1** connector on the ZCU102. +#. Insert the SD card into the SD card socket on the ZCU102. +#. Configure the :xilinx:`ZCU102` for SD card boot mode (SW6[4:1] = **OFF, OFF, + OFF, ON**): + + .. image:: ../../images/zcu102_1p0_bootmode.jpg + :width: 400 + +#. Plug in an Ethernet cable from your router/switch to the Ethernet port on the + FPGA board. +#. Connect USB UART J83 (Micro-USB) to your host PC. +#. (Optional) Connect a monitor via HDMI and a USB keyboard and mouse. +#. Connect the power supply to the ZCU102. +#. Turn on the power switch on the FPGA board. +#. Observe kernel and serial console output messages on your terminal (use the + first ttyUSB or COM port registered, 115200 8N1). + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console after connecting to the +correct ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + .. TO BE ADDED + +Useful commands for the serial terminal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Login information** + +.. code-block:: text + + user: analog password: analog + +To find the IP address of the FPGA board: + +.. shell:: + + $ifconfig + +To see the IIO devices detected: + +.. shell:: + + $iio_info | grep iio:device iio:device0: axi-ad9694-hpc (buffer capable) + iio:device1: xadc + +To power off the system safely (wait for the final message, then flip the power +switch): + +.. shell:: + + $poweroff + +To reboot: + +.. shell:: + + $reboot + +.. important:: + + This is a persistent file system. Do not cut power without shutting down + first --- use ``poweroff`` or ``sudo shutdown -h now`` to avoid filesystem + corruption. + +Using IIO Oscilloscope +------------------------------------------------------------------------------- + +After booting process is complete, you can open IIO-Oscilloscope. Learn more +about it :doc:`here `. You can interact with +the IIO-Osc GUI either directly or over the network. + +Once the board is booted and you have the IP address: + +#. Open :ref:`iio-oscilloscope` on your host PC. +#. Connect to the ZCU102 by entering its IP address. +#. Select the **AD9694** device from the device list. +#. Configure the capture settings (sample rate, decimation, DDC NCO frequency as + needed). +#. Click **Capture** to view the ADC data in time domain or FFT. + +#. Captured Loopback Signal Time Domain + + .. .. image:: ../images/ad9694_zcu102_time_domain.png + .. :width: 900 + .. TO BE ADDED + +#. Captured Loopback Signal Frequency Domain + + .. .. image:: ../images/ad9694_zcu102_frequency_domain.png + .. :width: 900 + .. TO BE ADDED + +For further details on IIO Oscilloscope features, refer to its +:ref:`iio-oscilloscope` documentation. diff --git a/docs/solutions/reference-designs/eval-ad9694/user-guide.rst b/docs/solutions/reference-designs/eval-ad9694/user-guide.rst new file mode 100644 index 00000000000..f45e2913e6e --- /dev/null +++ b/docs/solutions/reference-designs/eval-ad9694/user-guide.rst @@ -0,0 +1,91 @@ +.. _ad9694 user-guide: + +User guide +=============================================================================== + +Hardware guide +------------------------------------------------------------------------------- + +Hardware configuration +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Connector layout +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. figure:: images/ad9694_connector_new_board.jpg + :width: 600 + :alt: AD9694-500EBZ connector layout + + AD9694-500EBZ Connector Layout + +.. tip:: + + For more information on Sysref, see the :adi:`JESD204B Survival Guide + `. + +Jumper configuration +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. figure:: images/ad9694_jumpers_new_board.jpg + :width: 600 + :alt: Jumper connections on AD9694-500EBZ + + Jumper Connections on AD9694-500EBZ + +Before using the evaluation board, configure the jumpers as highlighted in green +in the evaluation board figure. Refer to the :ref:`ad9694-500ebz legacy page +` for detailed jumper positions for both old and new board +revisions. + +Power supply +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The AD9694-500EBZ can be powered externally or through the FMC connector from +the FPGA carrier board. It supports 12 V-1 A and 3.3 V-3 A supplies from FMC. +The evaluation board VADJ range is 1.2 V to 2.5 V. + +.. warning:: + + Removing jumpers or the board while powered via FMC may damage the board + and/or chip. Always power down before making changes. + +Analog inputs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The AD9694 has four analog input channels organized as two pairs: + +- **J101** --- Channel A input +- **J102** --- Channel B input +- **J104** --- Channel C input +- **J107** --- Channel D input + +Connect a clean, low-jitter signal source to the desired channel via coaxial +cable. It is recommended to use a narrow-band band-pass filter with 50 Ohm +terminations. + +For the ADC sample clock, connect a low-jitter clock source to connector +**J203** (up to 1 GHz, 50 Ohm coaxial cable, 14 dBm). + +Schematic, PCB Layout, Bill of Materials +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Design and integration files (schematic, PCB layout, BOM) are available from the +:adi:`AD9694 product page ` under the Design Resources tab. + +Helpful documents: + +- :adi:`AD9694 Data Sheet ` +- :adi:`AN-835 Application Note `, *Understanding ADC Testing and + Evaluation* + +Software guide +------------------------------------------------------------------------------- + +The AD9694-500EBZ is supported through the :ref:`libiio` library on ADI Kuiper +Linux, which runs on the FPGA carrier board (ZCU102). Applications that +interface via libiio include: + +- :ref:`iio-oscilloscope` --- graphical waveform and spectrum analyzer +- :external+pyadi-iio:doc:`index` --- Python interface + +For a step-by-step walkthrough, see the :ref:`ad9694 quickstart zcu102` guide.