diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ace_ad9136-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ace_ad9136-ebz.rst new file mode 100644 index 00000000000..1dbd714093d --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ace_ad9136-ebz.rst @@ -0,0 +1,143 @@ +AD9136/AD9135-EBZ Evaluation Board Quick Start Guide +==================================================== + +Getting Started with the AD9136/AD9135-EBZ Evaluation Board and Software +------------------------------------------------------------------------ + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`EVAL-AD9135` or :adi:`EVAL-AD9136` Evaluation Board for the :adi:`AD9136`/:adi:`AD9135` +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 1 Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9136/AD9135-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9136`/:adi:`AD9135`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9136/AD9135-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9136-EBZ. + +AD9136/AD9135 Evaluation Software +--------------------------------- + +The AD9136/AD9135 Evaluation Board software runs on the easy-to-use ACE (Analysis|Control|Evaluate) graphical user interface (GUI). It is included on the Evaluation Board CD. Registers on the AD9136/AD9135 and AD9516 products are programmed via a USB cable connecting the user’s PC to the AD9144-EBZ XP2 connector. Software in the AD9136-EBZ/AD9135-EBZ PIC processor (XU1) provides the interface between the USB bus and the SPI busses of the AD9136/AD9135 and AD9516. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J17. This is the +DAC0 output. The evaluation board connects to the DPG3 through the connector P4. +The PC should be connected to the EVB using the mini-USB connector XP2 after +installation of the Evaluation Board software. Figure 1 shows the block diagram +of the set-up. + +.. figure:: ../images/figure_1.png + :align: center + :width: 440 + + Block diagram of the AD9136/AD9135 lab bench set-up + +.. image:: ../images/figure_2.jpg + :align: center + :width: 400 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg. The installation will include the DPG Downloader software as well as all the necessary AD9136/AD9135 files including schematic, board layout, datasheet, AD9136/AD9135 SPI, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and AD9136/AD9135 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test +~~~~~~~~~~~~~~~~ + +These settings configure the AD9136/AD9135 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata = 1.6GHz, 1X interpolation, 4-carrier WCDMA signal with center frequency = 100MHz. + +Configure DPG Vector Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +1. To begin, turn on the external +5V supply. +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9136/AD9135, as indicated in the “Evaluation Board” drop-down list, shown in Figure 3. + +.. figure:: ../images/ad9136-ebz_dpgstartup.png + :align: center + :width: 600 + + Initial DPGDownloader Panel + +3. Select "QBF 2X4 85G 425M" from the "Port Configuration" drop-down list to configure the DPG for Dual Link and "Mode 8" from the "JESD Mode" drop-down list. +3. Click on “Add Generated Waveform”, and then “Wireless Infrastructure”. A WIFR panel will be added to the vector list. Enter the Data Rate, in this case 1.6GHz and the desired frequency, 100MHz. Enter the digital amplitude. In this case we use 0dBFS. Select "2's Complement" from the Number Format drop-down list. Input the center frequency of "100MHz" at the bottom of the panel, choose "WCDMA" from the Standard drop-down menu and increase the No. of Carriers to "4" - then hit the "Add Carriers" button. The DPG Downloader panel should look like Figure 3. +4. Select the WIFR vector (I) in the “DAC0” drop down menu and the WIFR vector (Q) in the “DAC1”. At this point, the DPG Downloader panel should look like Figure 4. + +.. figure:: ../images/ad9136-ebz_dpgsetup.png + :align: center + :width: 600 + + Configured DPGDownloader Panel + +Configuring SPI +^^^^^^^^^^^^^^^ + +1. Open ACE (Start > All Programs > Analog Devices > ACE). It should recognize the AD9136-EBZ or AD9135-EBZ in the attached hardware section when the application startup screen displays, as showing in Figure 5 for the AD9136-EBZ. + +.. figure:: ../images/ad9136-ebz_acestartup.png + :align: center + :width: 600 + + Initial ACE Startup Window with Attached Hardware AD9136-EBZ + +2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1.6GHz, and the output level to 3dBm. The spectrum analyzer can be configured with Start Frequency = 1 MHz, Stop Frequency = 800 MHz, and Resolution Bandwidth of 30 kHz, and Trace Detector to Average (Log/RMS/V). Choose Input Attenuation to be 8dB. This can be adjusted later if indications are that the analyzer is causing degradations. +3. Follow the sequence below to configure the AD9136-EBZ/AD9135-EBZ Setup Wizard settings. + + - The Links should be set to dual link. The JESD Mode is set to 8, Interpolation set to 1, and FDAC set to 1.6GHz, as shown in Figure 6. + - Hit “Apply” and the wizard will execute a startup routine to configure the AD9516 and the AD9136/AD9135. Once complete, the SERDES PLL lock indicator on the board will turn green if it locked and the display will look like Figure 7. + +.. figure:: ../images/ad9136-ebz_acesetup.png + :align: center + :width: 600 + + Configured ACE Wizard GUI for the AD9136-EBZ + +.. figure:: ../images/ad9136-ebz_acewizran.png + :align: center + :width: 600 + + ACE Wizard Executed and SERDES PLL Locked for the AD9136-EBZ + +4. Return to DPGDownloader and note the Serial Line Rate readback should read + 8Gbps indicating that the clocks going to the FPGA are configured properly + for this setup, as shown in Figure 8. + +5. Click Download (|9154_down_arrow.png|) and Play (|9154_right_green_arrow.png|) in the DPGDownloader screen. + +.. figure:: ../images/ad9136-ebz_dpgdwnld.png + :align: center + :width: 600 + + Executed DPGDownloader GUI for the AD9136-EBZ + +The current on the 5V supply should read about 1430mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four register readbacks on the board view for Code Group Sync, Frame Sync, Good CheckSum and Initial Lane Sync should all read 0x0F indicating the lanes are working correctly, as seen in Figure 7. +6. The output spectrum of the DAC should look like Figure 9 below. + +.. figure:: ../images/ad9136_1.6ghzdac_1x_4xwcdma_fout100m_plloff.png + :align: center + :width: 600 + + AD9136/AD9135-EBZ Eval Board DAC output Spectrum + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-ebz.rst new file mode 100644 index 00000000000..2b623c72d31 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-ebz.rst @@ -0,0 +1,318 @@ +AD9136/AD9135-EBZ Evaluation Board Quick Start Guide (SPIPro) +============================================================= + +Getting Started with the AD9136/AD9135-EBZ Evaluation Board and Software +------------------------------------------------------------------------ + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9135-EBZ` or :adi:`AD9136-EBZ` Evaluation Board +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 1 Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9136/AD9135-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9136-EBZ` or :adi:`AD9135-EBZ`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9136/AD9135-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9136-EBZ. + +AD9136/AD9135 Evaluation Software +--------------------------------- + +The AD9136/AD9135 Evaluation Board software has a legacy easy-to-use graphical user interface (GUI) included with the DPGDownloader. It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG3) and AD9136/AD9135 SPI software. However, ACE, or Analysis|Control|Evaluation, is the preferred evaluation software over the SPI software. ACE is included on the Evaluation Board CD or can be downloaded from https://wiki.analog.com/resources/tools-software/ace. The ACE plug-in for the AD9136/AD9135 is available in the software section of the eval website for both the :adi:`EVAL-AD9135` and :adi:`EVAL-AD9136`. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J17. This is the +DAC0 output. The evaluation board connects to the DPG3 through the connector P4. +The PC should be connected to the EVB using the mini-USB connector XP2 after +installation of the Evaluation Board software. Figure 1 shows the block diagram +of the set-up. + +.. figure:: ../images/figure_1.png + :align: center + :width: 440 + + Block diagram of the AD9136/AD9135 lab bench set-up + +.. image:: ../images/figure_2.jpg + :align: center + :width: 400 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg and the ACE website at https://wiki.analog.com/resources/tools-software/ace. The installation will include the DPG Downloader software as well as all the necessary AD9136/AD9135 files including schematic, board layout, datasheet, AD9136/AD9135 SPI, and other files. The ACE installation will include the necessary evaluation software, which is preferred over the DPGDownloader GUI. The following set-up describes how to use either ACE or the legacy SPI GUI to generate an output. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and ACE or the AD9136/AD9135 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test +~~~~~~~~~~~~~~~~ + +These settings configure the AD9136/AD9135 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata = 1.6GHz, 1X interpolation, 4-carrier WCDMA signal with center frequency = 100MHz. + +Configure DPG Vector Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +1. To begin, turn on the external +5V supply. +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9136/AD9135, as indicated in the “Evaluation Board” drop-down list, and select it. Select "QBF 2X4 85G 425M" from the "Port Configuration" drop-down list and "Mode 8" from the "JESD Mode" drop-down list. +3. Click on “Add Generated Waveform”, and then “Wireless Infrastructure”. A WIFR panel will be added to the vector list. Enter the Data Rate, in this case 1.6GHz and the desired frequency, 100MHz. Enter the digital amplitude. In this case we use 0dBFS. Select "2's Complement" from the Number Format drop-down list. Input the center frequency of "100MHz" at the bottom of the panel, choose "WCDMA" from the Standard drop-down menu and increase the No. of Carriers to "4" - then hit the "Add Carriers" button. +4. Select the WIFR vector (I) in the “DAC0” drop down menu and the WIFR vector (Q) in the “DAC1”. At this point, the DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/ad9135_dpgd_new.png + :align: center + + DPG Downloader Panel + +Configuring SPI using ACE +^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1.6GHz, and the output level to 3dBm. The spectrum analyzer can be configured with Start Frequency = 1 MHz, Stop Frequency = 800 MHz, and Resolution Bandwidth of 30 kHz, and Trace Detector to Average (Log/RMS/V). Choose Input Attenuation to be 8dB. This can be adjusted later if indications are that the analyzer is causing degradations. +2. Open ACE (Start > All Programs > Analog Devices > ACE > ACE). The |ace_icon_small.png| icon indicates the ACE software. If the board is connected properly, the screen should look similar to Figure 4. Double click on this board. + +.. figure:: ../images/ad9135_detected.png + :align: center + + Detected AD9135 in ACE + +Ensure that the |connection_icon.png| button is green in the subsystem image under the “System” tab, as shown in Figure 5. If not, click it, select the AD9136/5, and click *Acquire*. Double click on the subsystem image to reach the board block diagram. + +.. figure:: ../images/ad9135_system.png + :align: center + + AD9135 system + +Next to the board block diagram, click "Modify" under "Initial Configuration +Summary." + +.. figure:: ../images/ad9135_boardview_new.png + :align: center + + AD9135 board block diagram. The JESD PLL should not be locked yet + +Select "Dual Link" from the pull-down menu next to Links, and set the JESD Mode +to 8. Check the Subclass box and set interpolation to 1. The FDAC frequency +should be set to 1.6 GHz. The settings should match Figure 6. Select "Apply." + +.. figure:: ../images/ad9135_applypage_new.png + :align: center + + Initial configuration settings for the AD9135 + +Double click on the dark blue AD9135 chip block in the board block diagram. The +chip block diagram should appear, as shown in Figure 8. The JESD PLL should now +be locked on both the board and chip block diagrams. Other parameters can be +changed on both block diagrams, but do not need to be for this test. For more +information about changing parameters in ACE, see the ACE Software Features +section. + +.. figure:: ../images/ad9135_chipview_new.png + :align: center + + AD9135 chip block diagram + +3. On the DPGDownloader panel, seen in Figure 3, the Serial Line Rate in the should read 8Gbps. +Click Download (|image11|) and Play (|image12|) in the DPG Downloader screen. +The current on the 5V supply should read about 1430mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are working correctly. +4. The output spectrum of the DAC should look like Figure 9 below. + +.. figure:: ../images/ad9136_1.6ghzdac_1x_4xwcdma_fout100m_plloff.png + :align: center + :width: 600 + + AD9136/AD9135-EBZ Eval Board DAC output Spectrum + +Configuring SPI using the legacy SPI Application +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Open the AD9136/AD9135 SPI application (Start > All Programs > Analog Devices > AD9136/AD9135 > AD9136/AD9135 SPI). The screen should look similar to Figure 10. + +.. figure:: ../images/ad9136-ebz_spipro_initialview.png + :align: center + :width: 600 + + Entry Screen of the AD9136/AD9135 SPI software + +2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1.6GHz, and the output level to 3dBm. The spectrum analyzer can be configured with Start Frequency = 1 MHz, Stop Frequency = 800 MHz, and Resolution Bandwidth of 30 kHz, and Trace Detector to Average (Log/RMS/V). Choose Input Attenuation to be 8dB. This can be adjusted later if indications are that the analyzer is causing degradations. +3. Follow the sequence below to configure the AD9136/AD9135 SPI registers. + + - The Links should be set to dual link. The JESD Mode is set to 8, Subclass 1 box checked, Interpolation set to 1, and FDAC set to 1.6GHz. Click “Commit” button to initialize the AD9136/AD9135. The JESD204B PLL should be locked indicated with bright green JESD204B PLL readback LED. + - At this point the Serial Line Rate in the DPG3 software panel should read 8Gbps. + +.. figure:: ../images/ad9136-ebz_spipro_finalview.png + :align: center + :width: 600 + + Configured panel of the AD9136/AD9135 SPI software + + - Click Download (|image16|) and Play (|image17|) in the DPG Downloader screen. + - The current on the 5V supply should read about 1430mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are working correctly. + +4. The output spectrum of the DAC should look like Figure 12 below. + +.. figure:: ../images/ad9136_1.6ghzdac_1x_4xwcdma_fout100m_plloff.png + :align: center + :width: 600 + + AD9136/AD9135-EBZ Eval Board DAC output Spectrum + +ACE Software Features +--------------------- + +The ACE software is organized to allow the user to evaluate and control the +AD9122A evaluation board. The “Initial Configuration” wizard, which is only +available for certain boards, controls the DAC and PLL setups. Block diagram +views of the board and chip contain elements that can be used to vary parameters +like ref current and data format. These parameters can be changed using check +boxes, drop down menus, and input boxes. Some parameters do not have settings +shown in the diagram. Double click on the parameter to view the available +settings, seen with the NCO settings below. + +.. image:: ../images/ad9122_nco.png + :align: center + + +.. container:: centeralign + + NCO settings for the AD9122 + +In addition, some parameters can be enabled or disabled. This feature is evident +by the color of the block parameter. For example, if the block parameter is dark +blue, the parameter is enabled. If it is light grey, it is disabled. To enable +or disable a parameter, click on it. + +.. container:: column + + .. + +.. image:: ../images/ad9739a_on.png + :align: center + + +.. container:: column + + .. + +.. image:: ../images/ad9739a_off.png + :align: center + + +.. container:: column + + + .. container:: centeralign + + Enabled parameter + + + +.. container:: column + + + .. container:: centeralign + + Disabled parameter + + + +More direct changes to registers and bit fields can be made in the memory map, +which is linked from the chip block diagram through the “Proceed to Memory Map” +button. In this view, names, addresses, and data can be manually altered by the +user. + + + +.. image:: ../images/ad9122_memmap.png + :align: center + + +.. container:: centeralign + + Bench Set-Up + +ACE also contains the Macro Tool, which can be used to record register reads and +writes. This is executed in the memory map view or with the initialization +wizard. To use, check the “Record Sub-Commands” checkbox and press the record +button. Changes in the memory map, which are bolded until they are applied to +the part, are recorded as UI commands by the macro tool once the changes are +made. Changed register write commands for the controls are also recorded. Hit +“Apply Changes” to execute the commands and make changes in the memory map. To +stop recording, click the “Stop Recording” button. A macro tool page with the +command steps will be created. The macro can be saved using the “Save Macro” +button so that it may be loaded for future use. + +.. image:: ../images/ad9122_macrocommands.png + :align: center + + +.. container:: centeralign + + Macro tool in ACE. The *Stop Recording*, *Record*, and *Save Macro* commands are located at the top of the macro tool. + +The raw macro file will be saved using ACE syntax, which is not easily readable. +To remedy this, the ACE software download includes the Macro to Hex Conversion +Tool. The user can choose to include or exclude register write, reads, and/or +comments in the conversion. The file pathways for the source and save paths +should be the same, except that one should be an .acemacro file and the other +should be a .txt file. The “Convert” button converts and opens the converted +text file, which is easier to read. The conversion tool can also convert back to +an .acemacro file if desired. + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_5.png + :align: center + + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_4.png + :align: center + + +.. container:: column + + + .. container:: centeralign + + Conversion set-up for macro to hex + + + +.. container:: column + + + .. container:: centeralign + + Converted text file + + + +For more information about ACE and its features, visit https://wiki.analog.com/resources/tools-software/ace. + +.. |ace_icon_small.png| image:: ../images/ace_icon_small.png +.. |connection_icon.png| image:: ../images/connection_icon.png +.. |image11| image:: ../images/image009.png +.. |image12| image:: ../images/image010.png +.. |image16| image:: ../images/image009.png +.. |image17| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-fmc-ebz.rst new file mode 100644 index 00000000000..ad57b49eab2 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/ad9136-fmc-ebz.rst @@ -0,0 +1,162 @@ +EVALUATING THE AD9135/AD9136 DIGITAL-TO-ANALOG CONVERTER +======================================================== + +Preface +------- + +This user guide describes both the hardware and software setup needed to acquire data capture from :adi:`AD9135-FMC-EBZ `/:adi:`AD9136-FMC-EBZ ` evaluation board to characterize :adi:`AD9135`/:adi:`AD9136` 11-/16-bit 2.8Gsps dual JESD204B signal processing RF Digital to Analog Converter. + +The :adi:`AD9135-FMC-EBZ `/:adi:`AD9136-FMC-EBZ ` is an FMC mezzanine card and connects to an :adi:`ADS7-V2 ` or :adi:`ADS8-V1 ` data pattern generator system. The ADS7-V2/ADS8-V1 automatically formats the data and sends it to the AD9135/AD9136 FMC card via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2/ADS8-V1 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2/ADS8-V1. There is also an FMC standard I2C bus that is used by the ADS7-V2/ADS8-V1 to identify the AD9135/AD9136 FMC card. This I2C interface is implemented in software in the AD9135/AD9136 FMC card PIC processor (XU1). All ADS7-V2/ADS8-V1 to/from AD9135/AD9136 FMC card interface signals are connected via the FMC connector P1. + +Typical Setup +------------- + +.. figure:: ../images/ad9135-fmc-ebz_setup_with_label.jpg + :align: center + :width: 600 + + AD9135-FMC-EBZ Setup with ADS7-V2EBZ + +.. figure:: ../images/ad9135-fmc-ebz_setup2_with_labels.jpg + :align: center + :width: 600 + + AD9135-FMC-EBZ Setup with ADS8-V1EBZ + +.. figure:: ../images/ad9136-fmc-ebz_setup_with_labels.jpg + :align: center + :width: 600 + + AD9136-FMC-EBZ Setup with ADS7-V2EBZ + +.. figure:: ../images/ad9136-fmc-ebz_setup2_with_labels.jpg + :align: center + :width: 600 + + AD9136-FMC-EBZ Setup with ADS8-V1EBZ + +.. tip:: + + Tip: Click on any picture in this guide to open an enlarged version. + +Helpful Files/Links +------------------- + +- :doc:`AD9135-EBZ/AD9136-EBZ User Guide ` for non-FMC card users +- :dokuwiki:`ADS7-V1/-V2 for High-Speed DAC Evaluation ` +- Datasheet: :adi:`AD9135/AD9136 ` +- IBIS Model: :adi:`AD9135 `,\ :adi:`AD9136 ` +- AMI Model: `AD9144/AD9152/AD9154/AD9135/AD9136 `_ +- Simulink ADIsimDAC Model: `AD9136 `_ +- Schematic: `AD9135-FMC-EBZ <../resources/ad9135-fmc-ebz_revb_schematic.pdf>`_, `AD9136-FMC-EBZ <../resources/ad9136-fmc-ebz_revb_schematic.pdf>`_ +- Bill of Materials: `AD9135-FMC-EBZ <../resources/ad9135-fmc-ebz_revb_bom_customer.xlsx>`_, `AD9136-FMC-EBZ <../resources/ad9136-fmc-ebz_revb_bom_customer.xls>`_ +- PCB Gerber Files: `RevB <../resources/ad9144-fmc-ebz_revb_gerber_files.zip>`_ +- PCB BRD File: `RevB <../resources/ad9144-fmc-ebz_revb.zip>`_ +- PCB Layout PDF: `RevB <../resources/ad9144-fmc-ebz_revb_layout.pdf>`_ + +Software Needed +--------------- + +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`DPG Lite ` (Recommended; Installed with ACE) or :dokuwiki:`DPG Downloader ` +- ACE Plugin for Specific Device: :adi:`AD9135 `, :adi:`AD9136 ` + +.. important:: + + - Do not install ACE on a computer with DAC Software Suite. + - Known Issue: ACE may fail to detect HS-DAC boards, details :dokuwiki:`here `. + +Hardware Needed +--------------- + +- :adi:`AD9135-FMC-EBZ `/:adi:`AD9136-FMC-EBZ ` Evaluation Board which comes with: + + - USB-A to USB-Mini Cable + +- :dokuwiki:`ADS7-V2EBZ ` or :dokuwiki:`ADS8-V1EBZ ` Evaluation Kit which includes: + + - 12V 60W AC/DC Power Supply + - Power Cord + - USB-A to USB-B Cable + +- PC with ACE and DPG Lite Software Applications +- Low Phase Noise High-Frequency Continuous Wave Generator +- Signal/Spectrum Analyzer and/or Wide Bandwidth Oscilloscope +- (3) SMA Cables + +Quick Start Guide +----------------- + +- Attach AD9135-FMC-EBZ/AD9136-FMC-EBZ onto the FMC connector of ADS7-V2 or ADS8-V1 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, the DAC output at J17 to a signal/spectrum analyzer, and, if desired, the other DAC output at J5 to an oscilloscope. Connect ADS7-V2/ADS8-V1 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to :doc:`Typical Setup ` section for pictures of actual evaluation setup. +- Set the frequency of the continuous waveform generator output to **2.0 GHz** and the output level to **+3 dBm**. Enable the output. + +.. figure:: ../images/ad9136-fmc-ebz_dpg_board_detect.png + :align: center + :width: 600 + + ADS7-V2 and AD9136 detected in DPG Software + +- Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. + +.. figure:: ../images/ad9136-fmc-ebz_ace_board_detect.png + :align: center + :width: 600 + + AD9136-FMC-EBZ detected in ACE + +- Open ACE. The board will automatically be recognized by the software. Otherwise, install the plugin for AD9135/AD9136 evaluation board by following the steps in this page: :dokuwiki:`Quickstart - ACE Quickstart and Plug-in Installation `. + +.. figure:: ../images/ad9136-fmc-ebz_ace_configuration_wizard.png + :align: center + :width: 600 + + ACE Initial Configuration Wizard + +.. figure:: ../images/ad9136-fmc-ebz_ace_chipview.png + :align: center + :width: 600 + + ACE AD9136 Chipview Tab + +- In ACE, apply the configuration wizard settings enumerated below and shown in + JESD204B PLL should lock and the indicator should turn green. + + - **Links:** Dual Link + + - **JESD Mode:** 8 + - **Subclass1:** True + - **Interpolation:** 1 + - **DAC PLL:** False + - **FDAC:** 2 GHz + +.. figure:: ../images/ad9136-fmc-ebz_dpg_output_generation.png + :align: center + :width: 600 + + Single Tone and ADS7-V2 Configuration Panels in DPG + +- In DPG Lite or DPG Downloader, configure generation of two single tone waveforms. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Do this two times then configure the panels as follows: + + - **Data Rate** = 2 GHz, **Amplitude** = -1dBFS, **Unsigned Data** is unchecked for both panels. + + - **Desired Frequency = 112 MHz** in one panel while **Desired Frequency = 221 MHz** in the other. + - If using AD9135, set **DAC Resolution** to **11 bits**. Otherwise, leave as is (16 bits). + +- In the ADS7-V2 or ADS8-V1 panel in the DPG window, configure **Data Playback** by selecting tone2 for DAC0 and tone1 for DAC1. Set **JESD Mode** to Mode 8, **Links** to Dual, and **Subclass** to 1. + +.. figure:: ../images/ad9136-35_dac0_sa_output.png + :align: center + :width: 600 + + DAC0 Output Spectrum Analyzer Display + +.. figure:: ../images/ad9136-35_dac1_scope_output.png + :align: center + :width: 600 + + DAC1 Output Scope Display + +- Press the download arrow (|9154_down_arrow.png|) then the play button (|9154_right_green_arrow.png|). **Serial Line Rate** should appear as 10 Gbps and **Sync Status** should have two check marks. Refer to FFT plot of the DAC0 output in Figure 8 and the oscilloscope capture of DAC1 output in Figure 9. + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/eval-ad9136.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/eval-ad9136.rst new file mode 100644 index 00000000000..b27b8ce8437 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/eval-ad9136.rst @@ -0,0 +1,69 @@ +AD9136 & AD9135 Evaluation Boards +================================= + +The :adi:`AD9136` and :adi:`AD9135` evaluation boards follow the same design as +the AD9144 evaluation board. They share the same PCBs. The BOM & schematics +below reflect the differences in board components and assembly. + +The AD9136 & AD9135 DPG3 and ADS7 evaluation boards are also compatible and +supported by new SPI programming software called ACE (Analysis \| Control \| +Evaluate). This software can be downloaded from the ACE Wiki site under +"Resources" (:dokuwiki:`/resources/tools-software/ace`) and is also +included in the DVD that is shipped as part of the evaluation board kit. Please +refer to the Quick Start Guide Using ACE for details on how to use the new SPI +GUI software. + +Documentation and software updates for using High-Speed DAC Evaluation Boards +are included in the :dokuwiki:`DAC Software Suite ` +and below. Follow the link to the Quick Start Guides below for information on +both the AD9136 and AD9135. + +Files +----- + +- :adi:`AD9136 & AD9135 Data Sheet ` +- :adi:`IBIS Model ` + +.. list-table:: + :header-rows: 1 + + * - Item + - AD9136-EBZ & AD9135-EBZ + - AD9136-FMC-EBZ & AD9135-FMC-EBZ + * - Quick Start Guide + - :doc:`ACE ` / :doc:`SPIPro ` + - :doc:`ACE ` + * - Schematics + - :download:`RevA <../resources/ad9144-ebz_reva_schematic.pdf>` + - :download:`AD9135-FMC-EBZ <../resources/ad9135-fmc-ebz_revb_schematic.pdf>` / + :download:`AD9136-FMC-EBZ <../resources/ad9136-fmc-ebz_revb_schematic.pdf>` + * - Bill of Materials + - :download:`RevA <../resources/ad9144-ebz_reva_bom.xls>` + - :download:`AD9135-FMC-EBZ <../resources/ad9135-fmc-ebz_revb_bom_customer.xlsx>` / + :download:`AD9136-FMC-EBZ <../resources/ad9136-fmc-ebz_revb_bom_customer.xls>` + * - PCB Gerber Files + - :download:`RevA <../resources/ad9144-ebz_reva_gerber_files.zip>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_gerber_files.zip>` + * - PCB BRD File + - :download:`RevA <../resources/ad9144-ebz_reva.zip>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb.zip>` + * - PCB Layout PDF + - :download:`RevA <../resources/ad9144-ebz_reva_layout.pdf>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_layout.pdf>` + +Data Pattern Generator +---------------------- + +The Data Pattern Generator (DPG) is a bench-top instrument for driving vectors +into high-speed digital-to-analog converters. The DPG connects to a USB on a PC +and allows a user to download a vector from the PC into the internal memory of +the DPG. Once downloaded, the vector can be played out to an attached evaluation +board for a specific DAC at full speed. This allows for rapid evaluation of the +DAC with both generic and custom-generated test data. + +For more information on the DPG line of pattern generators and software: + +- :dokuwiki:`DAC Software Suite ` +- :dokuwiki:`DPG Lite ` +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`ADS7 ` diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/index.rst new file mode 100644 index 00000000000..bf036d1a9ea --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9136/index.rst @@ -0,0 +1,9 @@ +AD9135 / AD9136 +=============================================================================== + +.. toctree:: + + eval-ad9136 + ace_ad9136-ebz + ad9136-ebz + ad9136-fmc-ebz diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-ebz.rst new file mode 100644 index 00000000000..7383855c262 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-ebz.rst @@ -0,0 +1,117 @@ +AD9144-EBZ Evaluation Board Quick Start Guide Using ACE (Analysis \| Control \| Evaluate) Software +================================================================================================== + +Getting Started with the AD9144-EBZ Evaluation Board and Software +----------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9144-EBZ` Evaluation Board +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9144-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9144`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9144-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9144-EBZ. + +AD9144 Evaluation Software +-------------------------- + +The AD9144 Evaluation Board software runs on the easy-to-use ACE (Analysis|Control|Evaluate) graphical user interface (GUI). It is included on the Evaluation Board CD. Registers on the AD9144 and AD9516 products are programmed via a USB cable connecting the user’s PC to the AD9144-EBZ XP2 connector. Software in the AD9144-EBZ PIC processor (XU1) provides the interface between the USB bus and the SPI busses of the AD9144 and AD9516. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J4. A +1.0V power +supply must be connected to the VTT probe point near SMA connector J9, along +with a GND connection to the GND probe point next to it. The evaluation board +connects to the DPG3 through the connectors P4. The PC should be connected to +the EVB using the mini-USB connector XP2 after installation of the Evaluation +Board software. Figure 1 shows the block diagram of the set-up. + +.. figure:: ../images/ad9144_figure_1.png + :align: center + :width: 440 + + Block diagram of the AD9144 lab bench set-up + +.. image:: ../images/ad9144_ebz_photo.jpg + :align: center + :width: 400 + +Single-Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9144 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata = 750MHz, 2X interpolation, IF = 112MHz. +=== Single Tone Demo Lab Bench Configuration Procedure:=== These settings configure the AD9144 to output a 112MHz -1dbFS sine wave using the DPG3 on all four AD9144 DACs. + +- Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 8 with a resolution bandwidth of 100kHz. + Choose an Input Attenuation of 24dB. + +- On your lab computer, open the ACE application (Start > All Programs > Analog Devices > ACE). You will see the GUI shown in Figure 5 come up. + +Single Tone Demo Hardware and Software Start Up Procedure: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Open DPG Downloader. It will say AD9144 as shown in Figure 3 + +.. image:: ../images/ad9144-ebz_dpgstartup.png + :align: center + :width: 900 + +2. To load the proper panel, select the Port Configuration option for "QBF 1x8 85G 425M" for single link (for dual link cases choose "QBF 2x4 85G 425M"). Select the JESD Mode drop-down to Mode 0 and Subclass to 0. Create a single-tone vector with a Data Rate of 750MHz, Desired Frequency of 112MHz, Amplitude of -1dBFS, uncheck the Unsigned Data checkbox and check the Generate Complex I & Q Data box. Select the I and Q vectors for each of the 4 DAC vector input options, as shown in Figure 4. + +.. image:: ../images/ad9144-ebz_dpgsetup.png + :align: center + :width: 900 + +3. Open ACE. It should recognize the AD9144-EBZ in the attached hardware section + when the application startup screen displays, as shown in Figure 5. + Double-click on the AD9144-EBZ icon to navigate to the board view. + +.. image:: ../images/ad9144-ebz_acestartup.png + :align: center + :width: 900 + +4. In the Setup Wizard, select single link, JESD Mode 0, Interpolation 2 and + FDAC 1.5GHz, as shown in Figure 6. Hit "Apply" and the wizard will execute a + startup routine to configure the AD9516 and AD9144. // // Once complete, the + SERDES PLL lock indicator on the board will turn green if it locked and the + display will look like Figure 7. + +.. image:: ../images/ad9144-ebz_acesetup.png + :align: center + :width: 900 + +.. image:: ../images/ad9144-ebz_acewizran.png + :align: center + :width: 900 + +5. Return to DPGDownloader and note the Serial Line Rate readback should read 7.5Gbps indicating that the clocks going to the FPGA are configured properly for this setup. 6. Click Download (|9154_down_arrow.png|) and Play (|9154_right_green_arrow.png|). The 'Sync Status' checkmark should turn green indicating that the SYNCOUTb level is high and the link is up, as shown in Figure 7. The spectrum in Figure 8 will appear on all 4 DAC outputs (J17, J4, J5, and J14). + +.. image:: ../images/ad9144-ebz_dpgdwnld.png + :align: center + :width: 900 + +8. Figure 8 shows what you will see at the output of the DACs on the Spectrum + Analyzer. + +.. image:: ../images/figure_8_ad9144_fmc_ebz_spectrum_capture_1.png + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-fmc-ebz.rst new file mode 100644 index 00000000000..78577d8b36b --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ace_ad9144-fmc-ebz.rst @@ -0,0 +1,143 @@ +EVALUATING THE AD9144 DIGITAL-TO-ANALOG CONVERTER +================================================= + +Preface +------- + +This user guide describes both the hardware and software setup needed to acquire data capture from :adi:`AD9144-FMC-EBZ ` evaluation board to characterize :adi:`AD9144` 16-bit 2.8Gsps quad JESD204B signal processing RF Digital to Analog Converter. + +The :adi:`AD9144-FMC-EBZ ` is an FMC mezzanine card and connects to an :adi:`ADS7-V2 ` data pattern generator system. The ADS7-V2 automatically formats the data and sends it to the AD9144-FMC-EBZ via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2. There is also an FMC standard I2C bus that is used by the ADS7-V2 to identify the AD9144-FMC-EBZ. This I2C interface is implemented in software in the AD9144-FMC-EBZ PIC processor (XU1). All ADS7-V2 to/from AD9144-FMC-EBZ interface signals are connected via the FMC connector P1. + +Typical Setup +------------- + +.. figure:: ../images/ad9144-fmc-ebz_setup_withlabels.jpg + :align: center + :width: 600 + + AD9144-FMC-EBZ Setup with ADS7-V2EBZ + +.. tip:: + + Tip: Click on any picture in this guide to open an enlarged version. + +Helpful Files/Links +------------------- + +- User Guides for non-FMC card users: + + - :doc:`AD9144-EBZ ` + - :doc:`AD9144-ADRF6720-EBZ ` + +- :dokuwiki:`ADS7-V1/-V2 for High-Speed DAC Evaluation ` +- Datasheet: :adi:`AD9144 ` +- IBIS Model: :adi:`AD9144 ` +- AMI Model: `AD9144/AD9152/AD9154/AD9135/AD9136 `_ +- Simulink ADIsimDAC Model: `AD9144 `_ +- Schematic: `RevB <../resources/ad9144-fmc-ebz_revb_schematic.pdf>`_ +- Bill of Materials: `RevB <../resources/ad9144-fmc-ebz_revb_bom.xls>`_ +- PCB Gerber Files: `RevB <../resources/ad9144-fmc-ebz_revb_gerber_files.zip>`_ +- PCB BRD File: `RevB <../resources/ad9144-fmc-ebz_revb.zip>`_ +- PCB Layout PDF: `RevB <../resources/ad9144-fmc-ebz_revb_layout.pdf>`_ + +Software Needed +--------------- + +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`DPG Lite ` (Recommended; Installed with ACE) or :dokuwiki:`DPG Downloader ` +- :adi:`AD9144 ACE Plugin ` + +.. important:: + + - Do not install ACE on a computer with DAC Software Suite. + - Known Issue: ACE may fail to detect HS-DAC boards, details :dokuwiki:`here `. + +Hardware Needed +--------------- + +- :adi:`AD9144-FMC-EBZ ` Evaluation Board which comes with: + + - USB-A to USB-Mini Cable + +- :dokuwiki:`ADS7-V2EBZ ` Evaluation Kit which includes: + + - 12V 60W AC/DC Power Supply + - Power Cord + - USB-A to USB-B Cable + +- PC with ACE and DPG Lite Software Applications +- Low Phase Noise High-Frequency Continuous Wave Generator +- Signal/Spectrum Analyzer +- (2) SMA Cables + +Quick Start Guide +----------------- + +- Attach AD9144-FMC-EBZ onto the FMC connector of ADS7-V2 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, and one of the DAC outputs (J4/J5/J14/J17) to a signal/spectrum analyzer. Connect ADS7-V2 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to :doc:`Typical Setup ` section for pictures of actual evaluation setup. +- Set the frequency of the continuous waveform generator output to **1.5 GHz** and the output level to **+3 dBm**. Enable the output. + +.. figure:: ../images/ad9144-fmc-ebz_dpg_board_detect.png + :align: center + :width: 600 + + ADS7-V2 and AD9144 detected in DPG Software + +- Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. See Figure 2. + +.. figure:: ../images/ad9144-fmc-ebz_ace_board_detect.png + :align: center + :width: 600 + + AD9144-FMC-EBZ detected in ACE + +- Open ACE. The board will automatically be recognized by the software as shown in Figure 3. Otherwise, install the plugin for AD9144 evaluation board by following the steps in this page: :dokuwiki:`Quickstart - ACE Quickstart and Plug-in Installation `. + +.. figure:: ../images/ad9144-fmc-ebz_ace_configuration_settings.png + :align: center + :width: 600 + + ACE Initial Configuration Wizard + +.. figure:: ../images/ad9144-fmc-ebz_ace_chipview.png + :align: center + :width: 600 + + ACE AD9144 Chipview Tab + +- In ACE, apply the configuration wizard settings enumerated below and shown in + JESD204B PLL should lock and the indicator should turn green. + + - **Links:** Single Link + - **JESD Mode:** 0 + - **Subclass1:** False + - **Interpolation:** 2 + - **DAC PLL:** False + - **FDAC:** 1.5 GHz + +.. figure:: ../images/ad9144-fmc-ebz_dpg_output_generation.png + :align: center + :width: 600 + + Single Tone and ADS7-V2 Configuration Panels in DPG + +- In DPG Lite or DPG Downloader, configure single tone waveform generation. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Apply the following settings: + + - **Data Rate:** 750 MHz + - **Desired Frequency:** 112 MHz + - **DAC Resolution:** 16 bits + - **Amplitude:** -1 dB + - **Unsigned Data:** unchecked + - **Generate Complex Data (I & Q):** checked + +- In the ADS7-V2 panel in the DPG window, configure **Data Playback** by selecting tones for the DAC outputs from each dropdown menu. Set **JESD Mode** to Mode 0, **Links** to Single, and **Subclass** to 0. + +.. figure:: ../images/ad9144-fmc-ebz_spectrum_capture.png + :align: center + :width: 600 + + AD9144 DAC Output FFT for Data Rate = 750 MHz, FOUT = 112 MHz + +- Press the download arrow (|9154_down_arrow.png|) then the play button (|9154_right_green_arrow.png|). **Serial Line Rate** should appear as 7.5 Gbps and **Sync Status** should have a check mark. FFT plot of the DAC output is in Figure 7. + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-adrf6720-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-adrf6720-ebz.rst new file mode 100644 index 00000000000..3f572051281 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-adrf6720-ebz.rst @@ -0,0 +1,162 @@ +AD9144-ADRF6720-EBZ Evaluation Board Quick Start Guide +====================================================== + +Getting Started with the AD9144-ADRF6720-EBZ Evaluation Board and Software +-------------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- AD9144-ADRF6720-EBZ Evaluation Board Rev 2 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 2 Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9144-ADRF6720-EBZ Evaluation board (13016 Rev B)(SAP part number +AD9144-M6720-EBZ) connects to a DPG3 for quick evaluation of the AD9144(a +high-speed, signal processing Digital to Analog Converter) and the ADRF6720 +(Analog Quadrature Modulator with integrated PLL) combined performance. The +Evaluation board include the AD9144 +two ADRF6720 AQMs to make two seperate TX +paths output on SMA's J4 and J14.The DPG3 automatically formats the data and +sends it to the AD9144-ADRF6720-EBZ, simplifying evaluation of the device. The +Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 +is included on this EVB as a clock fan-out and frequency divider for the DACCLK, +REFCLK and DPG3 input clock.Figure 2 is an image of the top side of the +AD9144-ADRF6720-EBZ. + +AD9144 Evaluation Software +-------------------------- + +The AD9144 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG3) and AD9144 SPI software. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. One low phase noise high frequency clock source +should be connected to the SMA connector, J1. J1 is the clock input of the +AD9516, whose outputs feed into the DAC and the DPG3. The other low phase noise +high frequency clock source should be connected to the SMA connector, J18 (the +ADRF6720-1 LO input), and the spectrum analyzer should be connected to the SMA +connector, J4 (the ADRF6720-1 RF1 output) or J14 (the ADRF6720-2 RF2 output) . +The default settings for ADRF6720-1 feeds the LO to the other AQM ADRF6720-2. +The evaluation board connects to the DPG3 through the connectors P4. The PC +should be connected to the EVB using the mini-USB connector XP2 after +installation of the Evaluation Board software. Figure 1 shows the block diagram +of the set-up. + +.. figure:: ../images/ad9144_figure_1.png + :align: center + :width: 440 + + Block diagram of the AD9144 lab bench set-up + +.. image:: ../images/figure_2.png + :align: center + :width: 300 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg. The installation will include the DPG Downloader software as well as all the necessary AD9144 files including schematic, board layout, datasheet, AD9144 SPI, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and AD9144 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test with DAC PLL used +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9144 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the IQMOD output, under the condition: Fdata = 500MHz, 4X interpolation, REFCLK = 250MHz Input signal = 70MHz,Nco =100MHz LO = 1000MHz, RF = 1170MHz. + +Configure the DPG Downloader Vector Software +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. To begin, turn on the external +5V supply. +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9144, as indicated in the “Evaluation Board” drop-down list and select the "QBF 2X4 5G 250M" option from the "Port Configuration" drop-down list. The “Serial Line Rate” window will show the incorrect clock rate until after the SPI software has been started; then it will change to the correct frequency. The DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/ad9144-adrf6720-ebz_dpg_downloader.png + :align: center + :width: 600 + + DPG Downloader Panel + +.. figure:: ../images/ad9144-adrf6720-ebz_dpg_downloader_final.png + :align: center + :width: 600 + + DPG Downloader sinewave vector + +4. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 500MHz for AD9516 clock input (divides down to 250MHz for the RefClk frequency), and the output level to 3dBm. Set the frequency of the LO clock signal generator to 1GHz, and the output level to 6dBm. The spectrum analyzer can be configured with Center Frequency = 1.11GHz, Span = 400 MHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 24dB. This can be adjusted later if indications are that the analyzer is causing degradations. + +Configure the SPI Software +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Open the AD9144-6720 SPI application (Start > All Programs > Analog Devices > AD9144 > AD9144 SPI). The screen should look similar to Figure 5. + +.. figure:: ../images/ad9144-adrf6720-ebz_initialviewp.png + :align: center + :width: 600 + + Entry Screen of the AD9144 SPI software + +2. Follow the sequence below to configure the AD9144 SPI registers. +a. Open the AD9144 customer SPI software and go to the Quick Start tab. (See Figure 5.) The parameters in the top left corner need to be selected in the Quick Start List in the panel. The Links should be set to dual link, mode (which is the interface mode) set to 4, Subclass 1 box checked, Interpolation set to 4, the DAC PLL box checked, REFCLK = 250MHz Fin =500MHz and FDAC set to 2GHz. +b. Click the “Configure DAC and Clock” button to initialize the AD9144. The JESD204B PLL lock should show PLL is locked, and the PLL Lock light should be bring green indicating the DAC PLL is also locked. +c. Click the “Read All Registers” button in the top menu bar. +d. The four registers "codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync" should all read 0F indicating the lanes are working correctly. The code will be different than 0F for other interface modes.At this point the "Serial Line Rate" readback on the DPG3 panel should read 5Gbps. +e. Click Download (|image8|) and Play (|image9|) in the DPG Downloader screen. +f. Configure the ADRF6720 modulators by selecting the "Restore Registers from File" button on the top right. Then select the "ADRF6720.csv" file from the pop-up browser window (should be located in the directory under "C:\\Program Files (x86)\\Analog Devices\\HSDAC\\AD9144\\SPIPro"). +g. For the "Select Sideband" control choose "Upper" on the Quick Start tab so that the output places the fout above the LO frequency. + +3. Once all the steps have been completed up to this point, the SPI software program should look like Figure 6. + +.. figure:: ../images/ad9144-adrf6720-ebz_finalsetup_nonco.png + :align: center + :width: 600 + + AD9144-ADRF6720 SPI Software Program Setup + +.. figure:: ../images/70mhz_tone_lo_1ghz.png + :align: center + :width: 600 + + AD9144-ADRF6720 Eval Board output Spectrum + +Single-Tone Test with NCO used +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +1. In the AD9144 customer SPI software go to the Quick Start tab. Set the FDAC to 2GHz and selecting the shift frequency, for this example we will use -50MHz. Select "Fine (uses FTW)" from the "Modulation Type" drop-down list, the NCO FTW will change from 00000 to F99999999998. Next click the ftw undate req button, the ftw update light should turn bring green at this point. See Figure 7. The analyzer spectrum shows the tone at 120MHz from the Lo frequency shown in Figure 8. + +.. figure:: ../images/ad9144-adrf6720-ebz_finalsetup_withnco.png + :align: center + :width: 600 + + SPI Panel set up for NCO + +.. figure:: ../images/120mhz_tone_using_50mhznco_shift.png + :align: center + :width: 600 + + AD9144-ADRF6720 Eval Board output Spectrum with NCO used + +Note +~~~~ + +In single link JESD204B mode 2 through 10, four additional register writes, as shown below, are added in this software to match the data mapping the DPG3 requires. They are not required if the data source is not a DPG3. +write(0x308,0x2c) write(0x309,0x3e) write(0x30A,0x08) write(0x30B,0x1a) + +.. |image8| image:: ../images/image009.png +.. |image9| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-ebz.rst new file mode 100644 index 00000000000..df72c01a6d5 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-ebz.rst @@ -0,0 +1,146 @@ +AD9144-EBZ Evaluation Board Quick Start Guide +============================================= + +Getting Started with the AD9144-EBZ Evaluation Board and Software +----------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9144-EBZ` Evaluation Board (Rev 2 Silicon) +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 2 Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9144-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9144`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9144-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9144-EBZ. + +AD9144 Evaluation Software +-------------------------- + +The AD9144 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG3) and AD9144 SPI software. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J4. A +1.0V power +supply must be connected to the VTT probe point near SMA connector J9, along +with a GND connection to the GND probe point next to it. The evaluation board +connects to the DPG3 through the connectors P4. The PC should be connected to +the EVB using the mini-USB connector XP2 after installation of the Evaluation +Board software. Figure 1 shows the block diagram of the set-up. + +.. figure:: ../images/ad9144_figure_1.png + :align: center + :width: 440 + + Block diagram of the AD9144 lab bench set-up + +.. image:: ../images/ad9144_ebz_photo.jpg + :align: center + :width: 400 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg. The installation will include the DPG Downloader software as well as all the necessary AD9144 files including schematic, board layout, datasheet, AD9144 SPI, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and AD9144 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test using DAC PLL==== These settings configure the AD9144 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +250MHz, 4X interpolation, IF = 50MHz, DAC PLL RefClock 125MHz. + +Configure DPG Vector Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +1. To begin, turn on the external +5V supply 2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog Devices > DPG > DPGDownloader). Ensure that the program detects the AD9144, as indicated in the “Evaluation Board” drop-down list, and select "QBF 2X4 5G 250M" from the "Port Configuration" drop-down list. The “Serial Line Rate” window will not readback properly because the SPI software has not been executed. The DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/ad9144-ebz_dpg_downloader.png + :align: center + :width: 600 + + DPG Downloader Panel + +.. figure:: ../images/ad9144-ebz_dpg_downloader_final.png + :align: center + :width: 600 + + DPG Downloader sinewave vector + +Configuring SPI +^^^^^^^^^^^^^^^ + +1. Open the AD9144 SPI application (Start > All Programs > Analog Devices > AD9144 > AD9144 SPI). The screen should look similar to Figure 5. + +.. figure:: ../images/ad9144-ebz_spipro_initialview.png + :align: center + :width: 600 + + Entry Screen of the AD9144 SPI software + +2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 250MHz for AD9516 clock input (divides down to 125MHz for the RefClk frequency), and the output level to 3dBm. The spectrum analyzer can be configured with Center Frequency = 200 MHz, Span = 400 MHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 20dB. This can be adjusted later if indications are that the analyzer is causing degradations. +3. Follow the sequence below to configure the AD9144 SPI registers. + + - Open the AD9144 customer SPI software and go to the Quick Start tab (See Figure 5). The parameters in top left corner need to be selected in the Quick Start List shown in the panel below. The Links should be set to dual link, mode which is interface mode set to 4, Subclass 1 box checked, Interpolation set to 4, the DAC PLL box checked,refCLK = 125MHz, Fin =250MHz and FDAC set to 1000 MHz. + - Click “Configure DAC and Clock” button to initialize the AD9144. At this point both the JESD204B PLL should be locked and the DAC PLL should locked indicated with bright green PLL button. + - Click “Read All Registers” in the top menu bar. You should see “JESD204B PLL Lock Readback” LED readback is bright green indicating that the SERDES PLL is locked. Similarly the DAC PLL is locked when the "PLL Lock" LED is bright green. + - The four registers "codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync" should all read 0F indicating the lanes are working correctly. If you are using a different interface mode than 4 these register will read different codes. At this point the “Serial Line Rate” readback on the DPG3 panel should read 2.5Gbps. + - Click Download (|image8|) and Play (|image9|) in the DPG Downloader screen. + - The current on the 5V supply should read about 1600mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are working correctly. + +.. figure:: ../images/50mhztone.png + :align: center + :width: 600 + + AD9144-EBZ Eval Board output Spectrum + +ConfSingle Tone using the NCO +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. The NCO is used by loading the FDAC to 1GHz and selecting the shift + frequency, for this example we will use 75MHz. Select “Fine (uses FTW)” from + the “Modulation Type” drop-down list, the NCO FTW will change from 00000 to + 133333333333 click the ftw undate req button, the ftw update light should + turn bring green at this point. See Figure 7 + +2. The DAC outputs will shift up to 125MHz (Sum on input and the NCO freq shift) + See Figure 8. + +.. figure:: ../images/ad9144-ebz_spipro_finalsetup.png + :align: center + :width: 600 + + SPI Setting for using NCO + +.. figure:: ../images/nco_tone_shift.png + :align: center + :width: 600 + + SPI Setting for using NCO + +Note +~~~~ + +In single link JESD204B mode 2 through 10, four additional register writes, as shown below, are added in this software to match the data mapping the DPG3 requires. They are not required if the data source is not a DPG3. +write(0x308,0x2c) write(0x309,0x3e) write(0x30A,0x08) write(0x30B,0x1a) + +.. |image8| image:: ../images/image009.png +.. |image9| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-fmc-ebz.rst new file mode 100644 index 00000000000..12c57de4e01 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/ad9144-fmc-ebz.rst @@ -0,0 +1,139 @@ +AD9144-FMC-EBZ Evaluation Board Quick Start Guide +================================================= + +Getting Started with the AD9144-FMC-EBZ Evaluation Board and Software +--------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9144-FMC-EBZ` Evaluation Board for ADS7 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Sinusoidal Clock Sources +- Spectrum Analyzer +- Oscilloscope +- Data Pattern Generator ADS7 + +Introduction +------------ + +The AD9144-FMC-EBZ connects to an ADS7 data pattern generator system. The AD9144 +is a quad JESD204B signal processing RF Digital to Analog Converter. The ADS7 +automatically formats the data and sends it to the AD9144-FMC-EBZ via its +JESD204B lanes. The AD9144-FMC-EBZ is an FMC mezzanine card. +12V, +3.3V, and +VADJ power supply rails are provided by the ADS7 system via the FMC connector +P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out +and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK +clock used by the ADS7. There is also an FMC standard I2C bus that is used by +the ADS7 to identify the AD9144-FMC-EBZ. This I2C interface is implemented in +software in the AD9144-FMC-EBZ PIC processor (XU1). All ADS7 to/from +AD9144-FMC-EBZ interface signals are connected via the FMC connector P1. + +AD9144 Evaluation Software +-------------------------- + +The AD9144 Evaluation Board software runs on the easy-to-use SPIPro graphical +user interface (GUI). It is included on the Evaluation Board CD. Registers on +the AD9144 and AD9516 products are programmed via a USB cable connecting the +user’s PC to the AD9144-FMC-EBZ XP2 connector. Software in the AD9144-FMC-EBZ +PIC processor (XU1) provides the interface between the USB bus and the SPI +busses of the AD9144 and AD9516. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J4. A +1.0V power +supply must be connected to the VTT probe point near SMA connector J9, along +with a GND connection to the GND probe point next to it. The evaluation board +connects to the DPG3 through the connectors P4. The PC should be connected to +the EVB using the mini-USB connector XP2 after installation of the Evaluation +Board software. Figure 1 shows the block diagram of the set-up. + +.. figure:: ../images/figure_1_ad9144_fmc_ebz_lab_bench_set-up.png + :align: center + + Block diagram of the FMC-EBZ lab bench set-up + +.. image:: ../images/figure_2_ad9144_fmc_ebz_board_photo.png + :align: center + +A low phase noise high frequency clock source should be connected to the SMA +connector J1. A spectrum analyzer should be connected to the SMA connector J4. +J5, J14 and J17 of the EVB should be connected to an oscilloscope. The +evaluation board connects to the ADS7 through the connector P4. The PC should be +connected to the EVB using the mini-USB connector XP2 after installation of the +Evaluation Board software. Figure 1 shows a block diagram of the set-up. + +Getting Started +--------------- + +The PC software is included in the CD shipped with the EVB. The installation +will include the DPG Downloader software as well as all the necessary AD9144 +files including schematic, board layout, datasheet, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and SPIPro software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Plug the AD9144-FMC-EBZ into port FMC_1 of the ADS7 System. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB as shown in Figure 1. +3. Connect the ADS7 unit to your PC via USB and turn on the ADS7. + +Single-Tone Demonstration==== These settings configure the AD9144 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +368.64MHz, 4X interpolation, IF = 20MHz. +=== Single Tone Demo Lab Bench Configuration Procedure:=== These settings configure the AD9144 to output a 112Mhz -1dbFS sine wave using the ADS7 on all four AD9144 DACs. + +- Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 8 with a resolution bandwidth of 100kHz. + Choose an Input Attenuation of 24dB. + +- On your lab computer, open the SPIPro application (Start > All Programs > Analog Devices > AD9144 > SPIPro). You will see the GUI shown in Figure 5 come up. + +.. image:: ../images/figure_3_ad9144_fmc_ebz_dp3_gui_initial.png + :align: center + :width: 900 + +Single Tone Demo Hardware and Software Start Up Procedure: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Run DPG Downloader. It will say AD9144 as shown in Figure 3 +2. Execute Port Configuration ‘Below 7.5Gbps’. This will turn on the ADS7 FMC power supplies that power the FMC EVB. + +.. image:: ../images/figure_4_ad9144_fmc_ebz_initial_dpg_downloader_.png + :align: center + :width: 900 + +3. Open SPIPro. It will say AD9144-FMC-EBZ in the upper left hand corner. +4. Select single link, JESD mode 0, Interpolation 2. Press ‘Configure DAC and Clock’ button. JESD204B PLL lock will turn green. + +.. image:: ../images/figure_5_ad9144_fmc_ebz_spipro_gui.png + :align: center + :width: 900 + +5. Select Single Tone under the Add Generated Waveforms Tab. Set Data Rate: 750Mhz, Desired Frequency: 112Mhz, Amplitude: -1dbFS, Uncheck Unsigned Data, Check Generate Complex Data (I and Q) +6. Populate the data playback selections as shown in Figure 6. +7. Click Download ( ) and Play ( ). The spectrum in figure 7 will appear on all 4 DAC outputs (J17, J4, J5, and J14), Serial Line Rate will be 7.5Gsps. + +.. image:: ../images/figure_6_ad9144_fmc_ebz_dp3_gui.png + :align: center + :width: 900 + +8. Here’s what you will see on DAC0, DAC1, and DAC3 on the scope + +.. image:: ../images/figure_7_ad9144_fmc_ebz_scope_capture.png + :align: center + +9. Here is what you will see at the output of DAC2 on the Spectrum Analyzer. + +.. image:: ../images/figure_8_ad9144_fmc_ebz_spectrum_capture_1.png + :align: center diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/eval-ad9144.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/eval-ad9144.rst new file mode 100644 index 00000000000..325bfa1f3b7 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/eval-ad9144.rst @@ -0,0 +1,77 @@ +AD9144 Evaluation Boards +======================== + +There are currently :adi:`AD9144` evaluation boards that support either the DPG3 +Pattern Generator Platform or the ADS7 FMC-compatible Pattern Generator. These +board variants are listed below in the table. + +The AD9144 DPG3 and ADS7 DAC-only evaluation boards are also compatible and +supported by new SPI programming software called ACE (Analysis \| Control \| +Evaluate). This software can be downloaded from the ACE Wiki site under +"Resources" (:dokuwiki:`/resources/tools-software/ace`) and is also included in +the DVD that is shipped as part of the evaluation board kit. Please refer to the +Quick Start Guide Using ACE for details on how to use the new SPI GUI software. + +Documentation and software updates for using High-Speed DAC Evaluation Boards +are included in individual, self-extracting update files. + +Files included in the AD9144 Update: +------------------------------------ + +- SPI Application +- DPGDownloader Panel +- :adi:`AD9144 Data Sheet ` +- :adi:`IBIS Model ` + +.. list-table:: + :header-rows: 1 + + * - Item + - AD9144-EBZ + - AD9144-M6720-EBZ + - AD9144-FMC-EBZ + * - Quick Start (SPIPro) + - :doc:`ad9144-ebz ` + - :doc:`ad9144-adrf6720-ebz ` + - :doc:`ad9144-fmc-ebz ` + * - Quick Start (ACE) + - :doc:`ace_ad9144-ebz ` + - Not Currently Supported + - :doc:`ace_ad9144-fmc-ebz ` + * - Schematics + - :download:`RevA <../resources/ad9144-ebz_reva_schematic.pdf>` + - :download:`RevC <../resources/ad9144-adrf6720-ebz_revc_schematic.pdf>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_schematic.pdf>` + * - Bill of Materials + - :download:`RevA <../resources/ad9144-ebz_reva_bom.xls>` + - Unavailable + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_bom.xls>` + * - PCB Gerber Files + - :download:`RevA <../resources/ad9144-ebz_reva_gerber_files.zip>` + - :download:`RevC <../resources/ad9144-adrf6720-ebz_revc_gerber_files.zip>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_gerber_files.zip>` + * - PCB BRD File + - :download:`RevA <../resources/ad9144-ebz_reva.zip>` + - :download:`RevC <../resources/ad9144-adrf6720-ebz_revc.zip>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb.zip>` + * - PCB Layout PDF + - :download:`RevA <../resources/ad9144-ebz_reva_layout.pdf>` + - :download:`RevC <../resources/ad9144-adrf6720-ebz_revc_layout.pdf>` + - :download:`RevB <../resources/ad9144-fmc-ebz_revb_layout.pdf>` + +Data Pattern Generator +---------------------- + +The Data Pattern Generator (DPG) is a bench-top instrument for driving vectors +into high-speed digital-to-analog converters. The DPG connects to a USB on a PC +and allows a user to download a vector from the PC into the internal memory of +the DPG. Once downloaded, the vector can be played out to an attached evaluation +board for a specific DAC at full speed. This allows for rapid evaluation of the +DAC with both generic and custom-generated test data. + +For more information on the DPG line of pattern generators and software: + +- :dokuwiki:`DAC Software Suite ` +- :dokuwiki:`DPG Lite ` +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`ADS7 ` diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/index.rst new file mode 100644 index 00000000000..8d355a663db --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9144/index.rst @@ -0,0 +1,11 @@ +AD9144 +=============================================================================== + +.. toctree:: + + eval-ad9144 + ace_ad9144-ebz + ace_ad9144-fmc-ebz + ad9144-adrf6720-ebz + ad9144-ebz + ad9144-fmc-ebz diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-adrf6720-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-adrf6720-ebz.rst new file mode 100644 index 00000000000..f70f6903e6b --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-adrf6720-ebz.rst @@ -0,0 +1,153 @@ +AD9152-ADRF6720-EBZ Evaluation Board Quick Start Guide +====================================================== + +Getting Started with the AD9152-ADRF6720-EBZ Evaluation Board and Software +-------------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9152-ADRF6720-EBZ ` Evaluation Board +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 2 Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9152-ADRF6720-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9152`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9152-ADRF6720-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9152-ADRF6720-EBZ. + +AD9152-ADRF6720 Evaluation Software +----------------------------------- + +The AD9152-ADRF6720 Evaluation Board software has an easy-to-use graphical user interface (GUI). It is included on the Evaluation Board CD, or can be downloaded from the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG3) and AD9152-ADRF6720 SPI software. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J17/J4 They are the +DAC0 output. The External LO should be connected to the SMA connector of J18. +The evaluation board connects to the DPG3 through the connector P4. The PC +should be connected to the EVB using the mini-USB connector XP2 after +installation of the Evaluation Board software. Figure 1 shows the block diagram +of the set-up. + +.. figure:: ../images/ad9152-6720-ebz_system1.png + :align: center + :width: 500 + + Block diagram of the AD9152-ADRF6720 lab bench set-up + +.. image:: ../images/ad9152-6720-ebz_photo.png + :align: center + :width: 300 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg. The installation will include the DPG Downloader software as well as all the necessary AD9152-ADRF6720 files including schematic, board layout, datasheet, AD9152-ADRF6720 SPI, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and AD9152-ADRF6720 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test +~~~~~~~~~~~~~~~~ + +These settings configure the AD9152_6720 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the Mod output, under the condition: Fdata = 375MHz, 4X interpolation, IF = 200MHz, LO = 2GHz (external). + +Configure DPG Vector Software +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. To begin, turn on the external +5V supply. + +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog + Devices > DPG > DPGDownloader). Ensure that the program detects the + AD9152-ADRF6720, as indicated in the “Evaluation Board” drop-down list, and + select it. + +3. Set “Port configuration” to “2X4 37G 187M ” in the DPG Downloader panel and + select Mode 4 in the JESD Mode drop-down box. + +4. Click on “Add Generated Waveform”, and then “Single Tone”. A Single Tone + panel will be added to the vector list. Enter the Data Rate, in this case + 350MHz and the desired frequency, 100MHz. Enter the digital amplitude. In + this case we use -10dBFS. Uncheck the “Unsigned Data” box, check the + “Generate complex data (I & Q)”, as in Figure 3. + +5. Select the data vector of 100MHz desired frequency ’in-phase’ data in the “DAC0” drop down menu and the ‘Quadrature’ data in the “DAC1”. At this point, the DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/dpg_downloader_pane1.png + :align: center + :width: 800 + + DPG Downloader Panel + +Configuring SPI +^^^^^^^^^^^^^^^ + +1. Open the AD9152 SPI application (Start > All Programs > Analog Devices > AD9152 > AD9152 SPI). The screen should look similar to Figure 4. + +.. figure:: ../images/ad9152_spipro0.png + :align: center + :width: 800 + + Entry Screen of the AD9152 SPI software + +2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1.5GHz, and the output level to +3dBm. The spectrum analyzer can be configured with Start Frequency = 10 MHz, Stop Frequency = 1.5GHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 10dB. This can be adjusted later if indications are that the analyzer is causing degradations. +3. Follow the sequence below to configure the AD9152 SPI registers. + + - The Links should be set to single link. The JESD Mode is set to 4, Interpolation set to 4, and FDAC set to 1.5GHz. Click “Commit” button to initialize the AD9152. The JESD204B PLL should be locked indicated with bright green JESD204B PLL readback LED. + - At this point the data clock frequency on the LED panel of the DPG3 should read 187MHz and the Serial Line Rate in the DPG3 software panel should read 3.75Gbps. + - Click “Read All Registers” in the top menu bar. You should see “JESD204B PLL Lock Readback” LED readback is bright green indicating that the SERDES PLL is locked. + +.. figure:: ../images/ad9152_spirpro1.png + :align: center + :width: 800 + + Entry Screen of the AD9152 SPI software + +d. Click Download (|image8|) and Play (|image9|) in the DPG Downloader screen. + +e. Configure the ADRF6720 by a startup sequence, Select “ Restore Registers from + File” in the “File” menu, then Select the file called + ADRF6720_PLLoff_for_AD9152_6720_evb.csv. See Figure6. + +.. figure:: ../images/ad9152-6720_6720_cfg_download.png + :align: center + :width: 800 + + AD9152-EBZ Eval Board output Spectrum + +f. The current on the 5V supply should read about 1479mA. If you do not see the + output, gently push the board toward the DPG3. This ensures that the board is + firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, + GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are + working correctly. The output should appear as Figure 7. + +.. figure:: ../images/ad9152-6720-ebz_rf_output.png + :align: center + :width: 600 + + AD9152-ADRF6720 EBZ Eval Board output Spectrum + +Note +~~~~ + +In single link JESD204B mode 4,5,6,7,9,10, the Serdes line cross-bar setting as shown below, are added in this software to match the data mapping the DPG3 requires. They are not required if the data source is not a DPG3. +write(0x308,0x08) write(0x309,0x1A) + +.. |image8| image:: ../images/image009.png +.. |image9| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-ebz.rst new file mode 100644 index 00000000000..e17cc629987 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-ebz.rst @@ -0,0 +1,338 @@ +AD9152-EBZ Evaluation Board Quick Start Guide +============================================= + +Getting Started with the AD9152-EBZ Evaluation Board and Software +----------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9152-EBZ` Evaluation Board +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5Vdc, Power Supply +- 1 Sinusoidal Clock Source +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9152-EBZ connects to a DPG3 for quick evaluation of the :adi:`AD9152`, a high-speed, signal processing Digital to Analog Converter. The DPG3 automatically formats the data and sends it to the AD9152-EBZ, simplifying evaluation of the device. The Evaluation Board (EVB) runs from a +5V supply. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, REFCLK and DPG3 input clock. Figure 2 is an image of the top side of the AD9152-EBZ. + +AD9152 Evaluation Software +-------------------------- + +The AD9152 Evaluation Board software includes the ACE software application and DPGDownloader software. There is an easy-to-use legacy graphical user interface (GUI) available on the DPG website at http://www.analog.com/dpg, but ACE is the preferred evaluation method for the AD9152. ACE is included on the Evaluation Board CD or can be downloaded from the ACE website at http://www.analog.com/en/design-center/evaluation-hardware-and-software/ace-software.html. The legacy GUI and DPGDownloader software are available on the DPG website at http://www.analog.com/dpg. This will install DPGDownloader (for generating and loading vectors into the DPG3) and AD9152 SPI software. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector, J1. This is the DACCLK input. The +spectrum analyzer should be connected to the SMA connector, J4. A +1.0V power +supply must be connected to the VTT probe point near SMA connector J9, along +with a GND connection to the GND probe point next to it. The evaluation board +connects to the DPG3 through the connectors P4. The PC should be connected to +the EVB using the mini-USB connector XP2 after installation of the Evaluation +Board software. Figure 1 shows the block diagram of the set-up. + +.. figure:: ../images/ad9152-ebz_photo.png + :align: center + :width: 500 + + Block diagram of the AD9152 lab bench set-up + +.. image:: ../images/ad9152_ebz_photo.png + :align: center + :width: 300 + +Getting Started +--------------- + +The PC software comes on the included Evaluation Board CD, but may also be downloaded from the DPG Web site at http://www.analog.com/dpg and the ACE website at http://www.analog.com/en/design-center/evaluation-hardware-and-software/ace-software.html. The installation will include the ACE application software and the DPG Downloader software as well as all the necessary AD9152 files including schematic, board layout, datasheet, AD9152 SPI, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and the ACE application software, which is preferred, or the AD9152 SPI software and support files on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB. +3. Connect the DGP3 unit to your PC and turn on the unit. + +Single-Tone Test +~~~~~~~~~~~~~~~~ + +These settings configure the AD9152 to output a sine wave using the DPG3 and allow the user to view the single-tone performance at the DAC output, under the condition: Fdata = 375MHz, 4X interpolation, Fout = 100MHz. + +Using ACE +~~~~~~~~~ + + +Configure DPG Vector Software +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. To begin, turn on the external +5V supply. + +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog + Devices > DPG > DPGDownloader). Ensure that the program detects the AD9152, + as indicated in the “Evaluation Board” drop-down list, and select it. + +3. Set “Port configuration” to “2X4 37G 187M ” in the DPG Downloader panel and + select Mode 4 in the JESD Mode drop-down box. + +4. Click on “Add Generated Waveform”, and then “Single Tone”. A Single Tone + panel will be added to the vector list. Enter the Data Rate, in this case + 375MHz and the desired frequency, 100MHz. Enter the digital amplitude. In + this case we use -10dBFS. Uncheck the “Unsigned Data” box, check the + “Generate complex data (I & Q)”, as in Figure 3. + +5. Select the data vector of 100MHz desired frequency ’in-phase’ data in the “DAC0” drop down menu and the ‘Quadrature’ data in the “DAC1”. At this point, the DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/dpg_downloader_pane1.png + :align: center + :width: 800 + + DPG Downloader Panel + +Configure the ACE Software +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Open ACE from the start window. It can be found by following the file path to the program or by searching in the windows search bar for “ACE.” The |ace_icon_small.png| icon indicates the ACE software. +2. If the board is connected properly, ACE will detect it and display it on the Start page under "Attached Hardware." Double click this board. + +.. figure:: ../images/ad9152_detected_new.png + :align: center + + The detected AD9152 in ACE. + +3. Ensure that the |connection_icon.png| button is green in the subsystem image under the “System” tab. If not, click it, select the AD9152, and click "Acquire." Double click on the subsystem image. + +.. figure:: ../images/ad9152_system_new.png + :align: center + + The AD9152 system. + +.. figure:: ../images/ad9152_boardview_new.png + :align: center + + The board block diagram of the AD9152. + +.. figure:: ../images/ad9152_applypage_new.png + :align: center + + Inputs for the Initial Configuration of the AD9152. + +.. figure:: ../images/ad9152_chipview.png + :align: center + + The chip block diagram of the AD9152. + +7. At this point the data clock frequency on the LED panel of the DPG3 should read 187MHz and the Serial Line Rate in the DPG3 software panel should read 3.75Gbps. Click Download (|image11|) and Play (|image12|) in the DPG Downloader screen. +8. The current on the 5V supply should read about 1256mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are working correctly. + +.. figure:: ../images/ad9152_dac_output1.png + :align: center + :width: 600 + + AD9152-EBZ Eval Board output Spectrum + +Using the Legacy SPI Application +"""""""""""""""""""""""""""""""" + +Configure DPG Vector Software +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. To begin, turn on the external +5V supply. + +2. Open DPG Downloader if you have not done so. (Start > All Programs > Analog + Devices > DPG > DPGDownloader). Ensure that the program detects the AD9152, + as indicated in the “Evaluation Board” drop-down list, and select it. + +3. Set “Port configuration” to “2X4 37G 187M ” in the DPG Downloader panel and + select Mode 4 in the JESD Mode drop-down box. + +4. Click on “Add Generated Waveform”, and then “Single Tone”. A Single Tone + panel will be added to the vector list. Enter the Data Rate, in this case + 375MHz and the desired frequency, 100MHz. Enter the digital amplitude. In + this case we use -10dBFS. Uncheck the “Unsigned Data” box, check the + “Generate complex data (I & Q)”, as in Figure 3. + +5. Select the data vector of 100MHz desired frequency ’in-phase’ data in the “DAC0” drop down menu and the ‘Quadrature’ data in the “DAC1”. At this point, the DPG Downloader panel should look like Figure 3. + +.. figure:: ../images/dpg_downloader_pane1.png + :align: center + :width: 800 + + DPG Downloader Panel + +Configuring SPI +^^^^^^^^^^^^^^^ + +1. Open the AD9152 SPI application (Start > All Programs > Analog Devices > AD9152 > AD9152 SPI). The screen should look similar to Figure 11. + +.. figure:: ../images/ad9152_spipro0.png + :align: center + :width: 800 + + Entry Screen of the AD9152 SPI software + +2. Configure the hardware according to the hardware set-up instructions given in the Hardware Setup section above. Set the frequency of the DAC clock signal generator to 1.5GHz, and the output level to +3dBm. The spectrum analyzer can be configured with Start Frequency = 10 MHz, Stop Frequency = 1.5GHz, and Resolution Bandwidth of 30 kHz. Choose Input Attenuation to be 10dB. This can be adjusted later if indications are that the analyzer is causing degradations. +3. Follow the sequence below to configure the AD9152 SPI registers. + + - The Links should be set to single link. The JESD Mode is set to 4, Interpolation set to 4, and FDAC set to 1.5GHz. Click “Commit” button to initialize the AD9152. The JESD204B PLL should be locked indicated with bright green JESD204B PLL readback LED. + - At this point the data clock frequency on the LED panel of the DPG3 should read 187MHz and the Serial Line Rate in the DPG3 software panel should read 3.75Gbps. + - Click “Read All Registers” in the top menu bar. You should see “JESD204B PLL Lock Readback” LED readback is bright green indicating that the SERDES PLL is locked. + +.. figure:: ../images/ad9152_spirpro1.png + :align: center + :width: 800 + + Entry Screen of the AD9152 SPI software + +d. Click Download (|image17|) and Play (|image18|) in the DPG Downloader screen. +e. The current on the 5V supply should read about 1256mA. If you do not see the output, gently push the board toward the DPG3. This ensures that the board is firmly connected to the DPG3. The four registers codeGrpSync, FrameSync, GoodCheckSum and Initial LaneSync should all read 0F indicating the lanes are working correctly. + +.. figure:: ../images/ad9152_dac_output1.png + :align: center + :width: 600 + + AD9152-EBZ Eval Board output Spectrum + +ACE Software Features +~~~~~~~~~~~~~~~~~~~~~ + +The ACE software is organized to allow the user to evaluate and control the +AD9122A evaluation board. The “Initial Configuration” wizard, which is only +available for certain boards, controls the DAC and PLL setups. Block diagram +views of the board and chip contain elements that can be used to vary parameters +like ref current and data format. These parameters can be changed using check +boxes, drop down menus, and input boxes. Some parameters do not have settings +shown in the diagram. Double click on the parameter to view the available +settings, seen with the NCO settings below. + +.. image:: ../images/ad9122_nco.png + :align: center + + +.. container:: centeralign + + NCO settings for the AD9122 + +In addition, some parameters can be enabled or disabled. This feature is evident +by the color of the block parameter. For example, if the block parameter is dark +blue, the parameter is enabled. If it is light grey, it is disabled. To enable +or disable a parameter, click on it. + +.. container:: column + + .. + +.. image:: ../images/ad9739a_on.png + :align: center + + +.. container:: column + + .. + +.. image:: ../images/ad9739a_off.png + :align: center + +.. container:: column + + .. container:: centeralign + + Enabled parameter + +.. container:: column + + .. container:: centeralign + + Disabled parameter + +More direct changes to registers and bit fields can be made in the memory map, +which is linked from the chip block diagram through the “Proceed to Memory Map” +button. In this view, names, addresses, and data can be manually altered by the +user. + +.. image:: ../images/ad9122_memmap.png + :align: center + + +.. container:: centeralign + + Bench Set-Up + +ACE also contains the Macro Tool, which can be used to record register reads and +writes. This is executed in the memory map view or with the initialization +wizard. To use, check the “Record Sub-Commands” checkbox and press the record +button. Changes in the memory map, which are bolded until they are applied to +the part, are recorded as UI commands by the macro tool once the changes are +made. Changed register write commands for the controls are also recorded. Hit +“Apply Changes” to execute the commands and make changes in the memory map. To +stop recording, click the “Stop Recording” button. A macro tool page with the +command steps will be created. The macro can be saved using the “Save Macro” +button so that it may be loaded for future use. + +.. image:: ../images/ad9122_macrocommands.png + :align: center + + +.. container:: centeralign + + Macro tool in ACE. The *Stop Recording*, *Record*, and *Save Macro* commands + are located at the top of the macro tool. + +The raw macro file will be saved using ACE syntax, which is not easily readable. +To remedy this, the ACE software download includes the Macro to Hex Conversion +Tool. The user can choose to include or exclude register write, reads, and/or +comments in the conversion. The file pathways for the source and save paths +should be the same, except that one should be an .acemacro file and the other +should be a .txt file. The “Convert” button converts and opens the converted +text file, which is easier to read. The conversion tool can also convert back to +an .acemacro file if desired. + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_5.png + :align: center + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_4.png + :align: center + +.. container:: column + + .. container:: centeralign + + Conversion set-up for macro to hex + +.. container:: column + + .. container:: centeralign + + Converted text file + +For more information about ACE and its features, visit https://wiki.analog.com/resources/tools-software/ace. + +Note +~~~~ + +In single link JESD204B mode 4,5,6,7,9,10, the Serdes line cross-bar setting as shown below, are added in this software to match the data mapping the DPG3 requires. They are not required if the data source is not a DPG3. +write(0x308,0x08) write(0x309,0x1A) + +.. |ace_icon_small.png| image:: ../images/ace_icon_small.png +.. |connection_icon.png| image:: ../images/connection_icon.png +.. |image11| image:: ../images/image009.png +.. |image12| image:: ../images/image010.png +.. |image17| image:: ../images/image009.png +.. |image18| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-fmc-ebz.rst new file mode 100644 index 00000000000..208cd069098 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/ad9152-fmc-ebz.rst @@ -0,0 +1,155 @@ +EVALUATING THE AD9152 DIGITAL-TO-ANALOG CONVERTER +================================================= + +Preface +------- + +This user guide describes both the hardware and software setup needed to acquire data capture from :adi:`AD9152-FMC-EBZ ` evaluation board (EVB) to characterize the :adi:`AD9152` 16-bit 2.25GSPS Dual JESD204B signal processing RF Digital-to-Analog Converter. + +The AD9152-FMC-EBZ has an FMC mezzanine card and connects to an :adi:`ADS7-V2 ` or :adi:`ADS8-V1 ` data pattern generator system. The ADS7-V2/ADS8-V1 automatically formats the data and sends it to the EVB via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2/ADS8-V1 system via the FMC connector P1. A clock distribution chip (AD9516-1) is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2/ADS8-V1. + +There is also an FMC standard I2C bus that is used by the ADS7-V2/ADS8-V1 to +identify the board. This I2C interface is implemented in software in the +AD9152-FMC-EBZ PIC processor (XU1). All ADS7-V2/ADS8-V1 to/from the EVB +interface signals are connected via the FMC connector P1. + +Typical Setup +------------- + +.. figure:: ../images/ad9152-fmc-ebz_setup_with_labels.jpg + :align: center + :width: 600 + + AD9152-FMC-EBZ Setup with ADS7-V2EBZ + +.. figure:: ../images/ad9152-fmc-ebz_setup2_with_labels.jpg + :align: center + :width: 600 + + AD9152-FMC-EBZ Setup with ADS8-V1EBZ + +.. tip:: + + Tip: Click on any picture in this guide to open an enlarged version. + +Helpful Files/Links +------------------- + +- User Guides for non-FMC card users: + + - :doc:`AD9152-EBZ ` + - :doc:`AD9152-ADRF6720-EBZ ` + +- :dokuwiki:`ADS7-V1/-V2 for High-Speed DAC Evaluation ` +- Datasheet: :adi:`AD9152 ` +- IBIS Model: :adi:`AD9152 ` +- AMI Model: `AD9144/AD9152/AD9154/AD9135/AD9136 `_ +- Schematic: `RevA <../resources/ad9152-fmc-ebz_reva_schematic.pdf>`_ +- Bill of Materials: `RevA <../resources/ad9152-fmc-ebz_reva_bom.xlsx>`_ +- PCB Gerber Files: `RevA <../resources/ad9152-fmc-ebz_reva_gerber_files.zip>`_ +- PCB BRD File: `RevA <../resources/ad9152-fmc-ebz_reva.zip>`_ +- PCB Layout PDF: `RevA <../resources/ad9152-fmc-ebz_reva_layout.pdf>`_ + +Software Needed +--------------- + +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`DPG Lite ` (Recommended; Installed with ACE) or :dokuwiki:`DPG Downloader ` +- :adi:`AD9152 ACE Plugin ` + +.. important:: + + + - Do not install ACE on a computer with DAC Software Suite. + - Known Issue: ACE may fail to detect HS-DAC boards, details :dokuwiki:`here `. + + +Hardware Needed +--------------- + +- :adi:`AD9152-FMC-EBZ ` Evaluation Board which comes with: + + - USB-A to USB-Mini Cable + +- :dokuwiki:`ADS7-V2EBZ ` or :dokuwiki:`ADS8-V1EBZ ` Evaluation Kit which includes: + + - 12V 60W AC/DC Power Supply + - Power Cord + - USB-A to USB-B Cable + +- PC with ACE and DPG Lite Software Applications +- Low Phase Noise High-Frequency Continuous Wave Generator +- Signal/Spectrum Analyzer +- (2) SMA Cables + +Quick Start Guide +----------------- + +- Attach AD9152-FMC-EBZ onto the FMC connector of ADS7-V2 or ADS8-V1 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, and one of the DAC outputs (J4 or J17) to a signal/spectrum analyzer. Connect ADS7-V2/ADS8-V1 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to :doc:`Typical Setup ` section for pictures of actual evaluation setup. +- Set the frequency of the continuous waveform generator output to **1.5 GHz** and the output level to **+3 dBm**. Enable the output. + +.. figure:: ../images/ad9152-fmc-ebz_dpg_board_detect_ads7.png + :align: center + :width: 600 + + ADS7-V2 and AD9152 detected in DPG Software + +- Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. See Figure 2. + +.. figure:: ../images/ad9152-fmc-ebz_ace_board_detect_ads7.png + :align: center + :width: 600 + + AD9152-FMC-EBZ detected in ACE + +- Open ACE. The board will automatically be recognized by the software as shown in Figure 3. Otherwise, install the plugin for AD9152 evaluation board by following the steps in this page: :dokuwiki:`Quickstart - ACE Quickstart and Plug-in Installation `. + +.. figure:: ../images/ad9152-fmc-ebz_ace_configuration_wizard_ads7.png + :align: center + :width: 600 + + ACE Initial Configuration Wizard + +.. figure:: ../images/ad9152-fmc-ebz_ace_chipview_ads7.png + :align: center + :width: 600 + + ACE AD9152 Chip View Tab + +- In ACE, apply the configuration wizard settings enumerated below and shown in + JESD204B PLL should lock and the indicator should turn green. + + - **FDAC:** 1.5 GHz + - **Interpolation:** 2 + - **JESD Mode:** 4 + - **Subclass1:** True + - **DigGain:** True + - **PLL_Enable:** False + - **Input Data Format:** 2's complement + +.. figure:: ../images/ad9152-fmc-ebz_dpg_generate_output.png + :align: center + :width: 600 + + Single Tone and ADS7-V2 Configuration Panels in DPG + +- In DPG Lite or DPG Downloader, configure single tone waveform generation. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Apply the following settings: + + - **Data Rate:** 750 MHz + - **Desired Frequency:** 100 MHz + - **DAC Resolution:** 16 bits + - **Amplitude:** -10 dB + - **Unsigned Data:** unchecked + - **Generate Complex Data (I & Q):** checked + +- In the ADS7-V2 or ADS8-V1 panel in the DPG window, configure **Data Playback** by selecting tones for the DAC outputs from each dropdown menu. Set **JESD Mode** to Mode 4, **Links** to Single and **Subclass** to 1. + +.. figure:: ../images/ad9152-fmc_dac_output.png + :align: center + + AD9152 DAC Output FFT for Data Rate = 700 MHz, FOUT = 100 MHz + +- Press the download arrow (|9154_down_arrow.png|) then the play button (|9154_right_green_arrow.png|). As in Figure 6, **Serial Line Rate** should appear as 7.5 Gbps and **Sync Status** should have a check mark. The FFT plot of the DAC output is in Figure 7. + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/eval-ad9152.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/eval-ad9152.rst new file mode 100644 index 00000000000..3f1bf2a6818 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/eval-ad9152.rst @@ -0,0 +1,65 @@ +AD9152 Evaluation Board +======================= + +The :adi:`AD9152` evaluation boards follow the same design principles and are +available in multiple form factors for different evaluation setups. + +Documentation and software updates for using High-Speed DAC Evaluation Boards +are included in individual, self-extracting update files. + +Files included in the AD9152 Update: +------------------------------------ + +- SPI Application +- DPGDownloader Panel +- :adi:`AD9152 Data Sheet ` +- :adi:`IBIS Model ` + +.. list-table:: + :header-rows: 1 + + * - Item + - AD9152-EBZ + - AD9152-ADRF6720-EBZ + - AD9152-FMC-EBZ + * - Quick Start + - :doc:`ad9152-ebz ` + - :doc:`ad9152-adrf6720-ebz ` + - :doc:`ad9152-fmc-ebz ` + * - Schematics + - :download:`RevB <../resources/ad9152-ebz_revb_schematic.pdf>` + - :download:`RevB <../resources/ad9152-adrf6720-ebz_revb_schematic.pdf>` + - :download:`RevA <../resources/ad9152-fmc-ebz_reva_schematic.pdf>` + * - Bill of Materials + - :download:`RevB <../resources/ad9152-ebz_revb_bom.xlsx>` + - :download:`RevB <../resources/ad9152-adrf6720-ebz_revb_bom.xlsx>` + - :download:`RevA <../resources/ad9152-fmc-ebz_reva_bom.xlsx>` + * - PCB Gerber Files + - :download:`RevB <../resources/ad9152-ebz_revb_gerber_files.zip>` + - :download:`RevB <../resources/ad9152-adrf6720-ebz_revb_gerber_files.zip>` + - :download:`RevA <../resources/ad9152-fmc-ebz_reva_gerber_files.zip>` + * - PCB BRD File + - :download:`RevB <../resources/ad9152-ebz_revb.zip>` + - :download:`RevB <../resources/ad9152-adrf6720-ebz_revb.zip>` + - :download:`RevA <../resources/ad9152-fmc-ebz_reva.zip>` + * - PCB Layout PDF + - :download:`RevB <../resources/ad9152-ebz_revb_layout.pdf>` + - :download:`RevB <../resources/ad9152-adrf6720-ebz_revb_layout.pdf>` + - :download:`RevA <../resources/ad9152-fmc-ebz_reva_layout.pdf>` + +Data Pattern Generator +---------------------- + +The Data Pattern Generator (DPG) is a bench-top instrument for driving vectors +into high-speed digital-to-analog converters. The DPG connects to a USB on a PC +and allows a user to download a vector from the PC into the internal memory of +the DPG. Once downloaded, the vector can be played out to an attached evaluation +board for a specific DAC at full speed. This allows for rapid evaluation of the +DAC with both generic and custom-generated test data. + +For more information on the DPG line of pattern generators and software: + +- :dokuwiki:`DAC Software Suite ` +- :dokuwiki:`DPG Lite ` +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`ADS7 ` diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/index.rst new file mode 100644 index 00000000000..636531dd2f4 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9152/index.rst @@ -0,0 +1,9 @@ +AD9152 +=============================================================================== + +.. toctree:: + + eval-ad9152 + ad9152-adrf6720-ebz + ad9152-ebz + ad9152-fmc-ebz diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-ebz.rst new file mode 100644 index 00000000000..83ab5d7081d --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-ebz.rst @@ -0,0 +1,139 @@ +ACE AD9154-EBZ Evaluation Board Quick Start Guide +================================================= + +Getting Started with the AD9154-EBZ Evaluation Board and Software +----------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9154-EBZ` Evaluation Board for DPG3 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5VDC Lab Power Supply +- Sinusoidal Clock Source +- Spectrum Analyzer +- Oscilloscope +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal +processing RF Digital to Analog Converter. The DPG3 automatically formats the +data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board +(EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is +included on this EVB as a clock fan-out and frequency divider for the DACCLK, +JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. + +AD9154 Evaluation Software +-------------------------- + +The AD9154 Evaluation Board software runs on the ADI ACE graphical user +interface (GUI). ACE is included on the Evaluation board CD. Registers on the +AD9154 and AD9516 products are programmed by the ACE software via a USB cable +connecting the user’s PC to the AD9154-EBZ XP2 connector. Firware in the +AD9154-EBZ PIC processor (XU1) provides the interface between the USB bus and +the SPI busses of the AD9154 and AD9516. + +Hardware Setup +-------------- + +Figure 1 shows the block diagram of the set-up. + +.. image:: ../images/9154ebz_figure_1_1.png + +.. image:: ../images/9154ebz_figure_2.png + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector J1 (CLK_IN). A spectrum analyzer should +be connected to the SMA connector J17. Connect J4, J5, and J7 to an +oscilloscope. The evaluation board connects to the DPG3 through the connector +P4. The PC should be connected to the EVB using the mini-USB connector XP2. +Figure 1 shows a block diagram of the set-up. + +Getting Started +--------------- + +The EVB software is included in the CD shipped with the EVB. The installation +includes the DPG Downloader software as well as all the necessary AD9154 files +including schematic, board layout, datasheet, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DAC software suite and ACE on your PC. Follow the instructions in + the installation wizard and use the default (recommended) installation + settings. + +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment + to the EVB. + +3. Connect the DPG3 unit to your PC and turn on the unit. + +Single Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9154 to output a 112Mhz -1dbFS sine wave using +the DPG3 on all four AD9154 DACs. + +1. Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 7 with a resolution bandwidth of 100kHz. + Choose an Input Attenuation of 24dB. + +2. Open ACE from Start->Analog Devices->ACE. ACE will come up and display the initial ACE page shown in figure 3a. +3. Press the AD9154 icon and populate the AD9154 initialization wizard as shown in figure 3b, JESD mode 0, Interpolation 2. Leave all other settings in their default state. Press rhe APPLY button. JESD204B PLL lock will turn green as shown in figure 3c. Press the AD9154 icon in the initialization wizard tab. The AD9154 block diagram view will appear populated as shown in figure 3d. + +.. image:: ../images/ace_ad9154_ebz_realinit.png + :align: center + +.. image:: ../images/ace_ad9154_ebz_init.png + :align: center + +.. image:: ../images/ace_ad9154_ebz_afterapply.png + :align: center + +.. image:: ../images/ace_ad9154_ebz_block.png + :align: center + +4. DPGDownloader Start Up Sequence + +a. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > + DPGDownloader). DPGDownloader GUI will come up as shown Figure 4. + +b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress + bar will then show a moving green indication. + +c. Once port configuration is complete, select “add generated waveform” and + “single tone”. + +d. Set Data Rate to 750Mhz, Desired Frequency to 112Mhz, Amplitude to -1.0 dBFS, + uncheck unsigned, check Generate Complex Data (I&Q). + +e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 + and DAC3. + +f. Click Download then Play. The spectrum in Figure 6 will appear on all 4 DAC + outputs (J17, J4, J5, and J7), Serial Line Rate will be 7.5Gbps. Figure 7 is + a scope capture of the DAC output signal taken on three of the channels. + +5. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI + looks the same as Figure 4. + +.. image:: ../images/9154ebz_figure_5.png + +.. image:: ../images/9154ebz_figure_6.png + +6. Here is what you will see at the output of DAC0 on the Spectrum Analyzer. + +.. image:: ../images/9154ebz_figure_7.png + +7. Here’s what you will see on DAC1, DAC2, and DAC3 on the scope. + +.. image:: ../images/9154ebz_figure_8.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-fmc-ebz.rst new file mode 100644 index 00000000000..05d201788d0 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ace-fmc-ebz.rst @@ -0,0 +1,150 @@ +EVALUATING THE AD9154 DIGITAL-TO-ANALOG CONVERTER +================================================= + +Preface +------- + +This user guide describes both the hardware and software setup needed to acquire data capture from :adi:`AD9154-FMC-EBZ ` evaluation board to characterize :adi:`AD9154` 16-bit 2.4Gsps quad JESD204B signal processing RF Digital to Analog Converter. + +The :adi:`AD9154-FMC-EBZ ` is an FMC mezzanine card and connects to an :adi:`ADS7-V2 ` data pattern generator system. The ADS7-V2 automatically formats the data and sends it to the AD9154-FMC-EBZ via its JESD204B lanes. +12V, +3.3V, and VADJ power supply rails are provided by the ADS7-V2 system via the FMC connector P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK clock used by the ADS7-V2. There is also an FMC standard I2C bus that is used by the ADS7-V2 to identify the AD9154-FMC-EBZ. This I2C interface is implemented in software in the AD9154-FMC-EBZ PIC processor (XU1). All ADS7-V2 to/from AD9154-FMC-EBZ interface signals are connected via the FMC connector P1. + +Typical Setup +------------- + +.. figure:: ../images/ad9154-fmc-ebz_setup_with_labels.png + :align: center + :width: 600 + + AD9154-FMC-EBZ Setup with ADS7-V2EBZ + +.. tip:: + + Tip: Click on any picture in this guide to open an enlarged version. + +Helpful Files/Links +------------------- + +- User Guides for non-FMC card users: + + - :doc:`AD9154-EBZ ` + - :doc:`AD9154-ADRF6720-EBZ ` + +- :dokuwiki:`ADS7-V1/-V2 for High-Speed DAC Evaluation ` +- Datasheet: :adi:`AD9154 ` +- IBIS Model: :adi:`AD9154 ` +- AMI Model: `AD9144/AD9152/AD9154/AD9135/AD9136 `_ +- Schematic: `RevA <../resources/ad9154-fmc-ebz_reva_schematic.pdf>`_ +- Bill of Materials: `RevA <../resources/ad9154-fmc-ebz_reva_bom.xls>`_ +- PCB Gerber Files: `RevA <../resources/ad9154-fmc-ebz_reva_gerber_files.zip>`_ +- PCB BRD File: `RevA <../resources/ad9154-fmc-ebz_reva.zip>`_ +- PCB Layout PDF: `RevA <../resources/ad9154-fmc-ebz_reva_layout.pdf>`_ + +Software Needed +--------------- + +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`DPG Lite ` (Recommended; Installed with ACE) or :dokuwiki:`DPG Downloader ` +- :adi:`AD9154 ACE Plugin ` + +.. important:: + + + - Do not install ACE on a computer with DAC Software Suite. + - Known Issue: ACE may fail to detect HS-DAC boards, details :dokuwiki:`here `. + + +Hardware Needed +--------------- + +- :adi:`AD9154-FMC-EBZ ` Evaluation Board which comes with: + + - USB-A to USB-Mini Cable + +- :dokuwiki:`ADS7-V2EBZ ` Evaluation Kit which includes: + + - 12V 60W AC/DC Power Supply + - Power Cord + - USB-A to USB-B Cable + +- PC with ACE and DPG Lite Software Applications +- Low Phase Noise High-Frequency Continuous Wave Generator +- Signal/Spectrum Analyzer and/or Wide Bandwidth Oscilloscope +- 2 to 5 SMA Cables + +Quick Start Guide +----------------- + +- Attach AD9154-FMC-EBZ onto the FMC connector of ADS7-V2 controller board. Connect the evaluation board to PC via USB, the continuous waveform generator output to J1, one of the DAC outputs to a spectrum/signal analyzer and the rest to an oscilloscope. Connect ADS7-V2 to PC via USB and to a 12V 60W AC/DC power supply, then switch the board ON using S1 beside the connector for 12V supply. Refer to Typical Setup section for pictures of actual evaluation setup. +- Set the frequency of the continuous waveform generator output to **1.5 GHz** and the output level to **+3 dBm**. Enable the output. + +.. figure:: ../images/ad9154-fmc-ebz_dpg_board_detect_ads7.png + :align: center + :width: 600 + + ADS7-V2 and AD9154 detected in DPG Software + +- Start DPG Lite or DPG Downloader. A panel named after the detected controller board should appear at the bottom of the DPG window. The device on the evaluation board and the data interface should also be automatically detected by the software and shown at **Evaluation Board** and **Port Configuration**, respectively. See Figure 2. + +.. figure:: ../images/ad9154-fmc-ebz_ace_board_detect_ads7.png + :align: center + :width: 600 + + AD9154-FMC-EBZ detected in ACE + +- Open ACE. The board will automatically be recognized by the software as shown in Figure 3. Otherwise, install the plugin for AD9154 evaluation board by following the steps in this page: :dokuwiki:`Quickstart - ACE Quickstart and Plug-in Installation `. + +.. figure:: ../images/ad9154-fmc-ebz_ace_configuration_wizard_ads7.png + :align: center + :width: 600 + + ACE Initial Configuration Wizard + +.. figure:: ../images/ad9154-fmc-ebz_ace_chipview_ads7.png + :align: center + :width: 600 + + ACE AD9154 Chipview Tab + +- In ACE, apply the configuration wizard settings enumerated below and shown in + JESD204B PLL should lock and the indicator should turn green. + + - **Links:** Single Link + - **JESD Mode:** 0 + - **Subclass1:** False + - **Interpolation:** 2 + - **DAC PLL:** False + - **FDAC:** 1.5 GHz + +.. figure:: ../images/ad9154-fmc-ebz_dpg_generate_output.png + :align: center + :width: 600 + + Single Tone and ADS7-V2 Configuration Panels in DPG + +- In DPG Lite or DPG Downloader, configure single tone waveform generation. From the **Add Generator Waveforms** pulldown menu, select **Single Tone**. Apply the following settings: + + - **Data Rate:** 750 MHz + - **Desired Frequency:** 180 MHz + - **DAC Resolution:** 16 bits + - **Amplitude:** 0 dB + - **Unsigned Data:** unchecked + - **Generate Complex Data (I & Q):** checked + +- In the ADS7-V2 panel in the DPG window, configure **Data Playback** by selecting tones for the DAC outputs from each dropdown menu. Set **JESD Mode** to Mode 0, **Links** to Single, and **Subclass** to 0. + +.. figure:: ../images/ace_ad9154_fmc_180msa.png + :align: center + :width: 600 + + AD9154 DAC Output FFT for Data Rate = 750 MHz, FOUT = 180 MHz + +.. figure:: ../images/9154_fmcfigure_8_scope.png + :align: center + :width: 600 + + Oscilloscope Capture of Other DAC Outputs + +- Press the download arrow (|9154_down_arrow.png|) then the play button (|9154_right_green_arrow.png|). As in Figure 6, **Serial Line Rate** should appear as 7.5 Gbps and **Sync Status** should have a check mark. FFT plot of one of the DAC outputs is shown in Figure 7 while the oscilloscope capture of the other outputs is Figure 8. + +.. |9154_down_arrow.png| image:: ../images/9154_down_arrow.png +.. |9154_right_green_arrow.png| image:: ../images/9154_right_green_arrow.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-adrf6720-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-adrf6720-ebz.rst new file mode 100644 index 00000000000..8f68312487c --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-adrf6720-ebz.rst @@ -0,0 +1,158 @@ +AD9154-ADRF6720-EBZ Evaluation Board Quick Start Guide +====================================================== + +Getting Started with the AD9154-ADRF6720-EBZ Evaluation Board and Software +-------------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9154-ADRF6720-EBZ ` Evaluation Board for DPG3 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5VDC Lab Power Supply +- Two Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9154-ADRF6720-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal +processing RF Digital to Analog Converter. The DPG3 automatically formats the +data and sends it to the AD9154-ADRF6720-EBZ via its JESD204B lanes. The +AD9154-ADRF6720-EBZ includes an AD9154 and two ADRF6720-27 Wideband Quadrature +Modulators with Integrated PLL and VCO. There is a board level passive low pass +filter between the output of each AD9154 DAC and its corresponding ADRF6720-27 +baseband input. The Evaluation Board (EVB) runs from a single +5V lab supply. A +clock distribution chip AD9516 is included on this EVB as a clock fan-out and +frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock +used by the DPG3. + +AD9154 and ADRF6720-27 Evaluation Software +------------------------------------------ + +The AD9154 and ADRF6720-27 Evaluation software runs on the easy-to-use SPIPro +graphical user interface (GUI). It is included on the Evaluation Board CD. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector J1 (CLK_IN). A spectrum analyzer should +be connected to the SMA connector J4, RF_OUT_1. Connect a low phase sinusoidal +signal source to J18, the RF local oscillator input to ADRF6720-27_1. (The +ADRF6720-27 on-chip LO synthesizer is not used in this quick start guide.) The +evaluation board connects to the DPG3 through the connector P4. The PC is +connected to the EVB using the mini-USB connector XP2. Figure 1 shows a block +diagram of the set-up. + +.. image:: ../images/9154m6720_figure_1.png + +.. image:: ../images/9154m6720_figure_2.png + +Getting Started +--------------- + +The PC software is included in the CD shipped with the EVB. The installation +includes the DPG Downloader software as well as all the necessary AD9154 files +including schematic, board layout, datasheet, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and SPIPro software and support files on your PC. + Follow the instructions in the installation wizard and use the default + (recommended) installation settings. + +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment + to the EVB. + +3. Connect the DPG3 unit to your PC and turn on the unit. + +Single Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9154 to output a 182Mhz -1dbFS sine wave using +the DPG3 on all four AD9154 DACs. The DAC output signals are I/Q pairs. An +external LO of 1.36GHz is supplied to the ADRF6720-27 chips. The AD9720-27 chips +perform a complex single sideband up-conversion of the sine wave I/Q pairs to a +1542MHz RF signal at the RF_OUT_1 and RF_OUT_2 connectors J4 and J14. 1. +Configure the hardware according to the hardware set-up instructions given in +the Hardware Setup section above. Set the frequency of the DAC clock signal +generator to 1500MHz, and the output level to 3dBm. Set the frequency of the +ADRF6720-27 Synthesizer Local Oscillator Source to 1.36GHz and set its output +amplitude to +4dbm. The spectrum analyzer can be configured as shown in Figure 7 +with a resolution bandwidth of 100kHz. Choose an Input Attenuation of 24dB. 2. +On your lab computer, open the AD9154 SPIPro application (Start > All Programs > +Analog Devices > AD9154 > AD9154 SPI). You will see the GUI shown in Figure 7 +come up. + +.. image:: ../images/9154m6720_figure_3.png + +.. image:: ../images/9154m6720_figure_4.png + +3. SPIPro Start Up Sequence. + +a. In the Quick Start Tab Select “Single” for Links. + +b. Select JESD Mode 0. c. Uncheck the “Subclass 1” box. + +d. Select “2” for Interpolation. + +e. Press the “Configure DAC and Clock” Button + +f. The JESD204B PLL Lock Readback light should turn green and register bit + settings will be populated. The GUI will look like Figure 4, except that + values in “CodeGrpSync”, “FrameSync”, “GoodCheckSum”, and “InitialLaneSync” + may be different because the link JESD204B Transmitter has not yet been set + up. + +g. Load Register Settings into the ADRF6720 devices by clicking “Restore + Registers from File” and locating “ADRF6720.csv”. This should be located at + the install directory for the AD9154 SPIPro application. + +h. Click on “ADRF6720” tab for Mod 1 and confirm the GUI matches Figure 5 below. + +.. image:: ../images/9154m6720_figure_5.png + +i. Click on “ADRF67202” tab for Mod 2 and confirm the GUI matches Figure 6 + below. + +.. image:: ../images/9154m6720_figure_6_1.png + :align: center + +4. DPGDownloader Start Up Sequence + +a. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > + DPGDownloader). DPGDownloader GUI will come up as shown Figure 7. + +b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress + bar will then show a moving green indication. + +c. Once port configuration is complete, select “add generated waveform” and + “single tone”. + +d. Set Data Rate to 750Mhz, Desired Frequency to 182Mhz, Amplitude to -1.0 dBFS, + uncheck unsigned, check Generate Complex Data (I&Q). + +e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 + and DAC3. + +f. Click Download Button and the Play Button. The spectrum in Figure 9 will + appear on J4, RF_OUT_1. The Serial Line Rate will be 7.5Gbps. + +.. image:: ../images/9154m6720_figure_7.png + +.. image:: ../images/9154m6720_figure_8.png + +5. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI + looks the same as Figure 4. + +6. The current on the 5V supply should read about 2300mA – 2400mA. + +.. image:: ../images/9154m6720_figure_9.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ebz.rst new file mode 100644 index 00000000000..722d256104d --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-ebz.rst @@ -0,0 +1,402 @@ +SPIPRO AD9154-EBZ Evaluation Board Quick Start Guide +==================================================== + +Getting Started with the AD9154-EBZ Evaluation Board and Software +----------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9154-EBZ` Evaluation Board for DPG3 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5VDC Lab Power Supply +- Sinusoidal Clock Source +- Spectrum Analyzer +- Oscilloscope +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9154-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal +processing RF Digital to Analog Converter. The DPG3 automatically formats the +data and sends it to the AD9154-EBZ via its JESD204B lanes. The Evaluation Board +(EVB) runs from a single +5V lab supply. A clock distribution chip AD9516 is +included on this EVB as a clock fan-out and frequency divider for the DACCLK, +JESD204B SYSREF signals, and a CFRAME clock used by the DPG3. + +AD9154 Evaluation Software +-------------------------- + +There are two evaluation softwares available for the AD9154: ACE, the preferred evaluation software from ADI, and the legacy SPIPro graphical user interface (GUI). Both are included on the Evaluation Board CD. ACE can also be downloaded from the ACE website at https://wiki.analog.com/resources/tools-software/ace. In addition, the ACE plugin for the AD9154 is available in the software section of the :adi:`EVAL-AD9154` eval webpage. DPGDownloader is used with both evaluation softwares and can be downloaded from the DPG website at http://www.analog.com/dpg. + +Hardware Setup +-------------- + +Figure 1 shows the block diagram of the set-up. + +.. figure:: ../images/9154ebz_figure_1_1.png + :align: center + + AD9154-EBZ Lab Block Diagram + +.. figure:: ../images/9154ebz_figure_2.png + :align: center + + Top view of AD9154-EBZ + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector J1 (CLK_IN). A spectrum analyzer should +be connected to the SMA connector J17. Connect J4, J5, and J7 to an +oscilloscope. The evaluation board connects to the DPG3 through the connector +P4. The PC should be connected to the EVB using the mini-USB connector XP2. +Figure 1 shows a block diagram of the set-up. + +Getting Started +--------------- + +The PC software is included in the CD shipped with the EVB. The installation +includes the DPG Downloader software as well as all the necessary AD9154 files +including schematic, board layout, datasheet, and other files. The AD9154 +Evaluation Software section details the necessary evaluation software. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and ACE (or the SPIPro software) and support files + on your PC. Follow the instructions in the installation wizard and use the + default (recommended) installation settings. + +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment + to the EVB. + +3. Connect the DPG3 unit to your PC and turn on the unit. + +Single Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9154 to output a 112Mhz -1dbFS sine wave using +the DPG3 on all four AD9154 DACs. + +Using ACE +^^^^^^^^^ + +1. Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1.5 GHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 9 with a resolution bandwidth of 100kHz. + Choose an Input Attenuation of 24dB. + +2. Open ACE (Start > All Programs > Analog Devices > ACE > ACE). The |ace_icon_small.png| icon indicates the ACE software. If the board is connected properly, the screen should look similar to Figure 3. Double click on this board. + +.. figure:: ../images/ad9154_detected.png + :align: center + + Detected AD9154 in ACE + +Ensure that the |connection_icon.png| button is green in the subsystem image under the “System” tab, as shown in Figure 4. If not, click it, select the AD9154, and click "Acquire." Double click on the subsystem image to reach the board block diagram. + +.. figure:: ../images/ad9154_system.png + :align: center + + AD9154 system + +Next to the board block diagram, click "Modify" under "Initial Configuration +Summary." + +.. figure:: ../images/ad9154_boardview_enabled.png + :align: center + + AD9154 board block diagram. The JESD PLL should not be locked yet + +Select "Single Link" from the pull-down menu next to Links, and set the JESD +Mode to 0. Ensure that the Subclass box is unchecked, and set interpolation to +2. The FDAC frequency should be set to 1.5 GHz. The settings should match Figure +6. Select "Apply." + +.. figure:: ../images/ad9154_applypage.png + :align: center + + Initial configuration settings for the AD9154 + +Double click on the dark blue AD9154 chip block in the board block diagram. The +chip block diagram should appear, as shown in Figure 7. The JESD PLL should now +be locked on both the board and chip block diagrams. Other parameters can be +changed on both block diagrams, but do not need to be for this test. For more +information about changing parameters in ACE, see the ACE Software Features +section. + +.. figure:: ../images/ad9154_chipview.png + :align: center + + AD9154 chip block diagram + +3. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > + DPGDownloader). DPGDownloader GUI will come up. Select the Port configuration + QBF 1X8 85G 425M. The configuration progress bar will then show a moving + green indication. Once port configuration is complete, select “Add Generated + Waveform” and “Single Tone." Set Data Rate to 750 MHz, Desired Frequency to + 112 MHz, Amplitude to -1.0 dBFS, uncheck unsigned, check Generate Complex + Data (I&Q). Under Data Playback, select I data for DAC 0 and DAC2, and Q data + for DAC 1 and DAC3. These settings should match those in the DPGDownloader + panel in Figure 8. + +.. figure:: ../images/ad9154_dpgd.png + :align: center + + DPGDownloader settings + +4. Click Download (|image9|) and Play (|image10|) in the DPG Downloader screen. The spectrum in Figure 9 will appear on all 4 DAC outputs (J17, J4, J5, and J7), Serial Line Rate will be 7.5 Gbps. The current on the 5V supply should read around 1800mA - 1950mA. Figure 10 is a scope capture of the DAC output signal taken on three of the channels. + + + +5. Here is what you will see at the output of DAC0 on the Spectrum Analyzer. + +.. figure:: ../images/9154ebz_figure_7.png + :align: center + + DAC Output Spectrum Analyzer Display + +6. Here’s what you will see on DAC1, DAC2, and DAC3 on the scope. + +.. figure:: ../images/9154ebz_figure_8.png + :align: center + + DAC Outputs Scope Display + +Using the SPIPro software +^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1.5 GHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 15 with a resolution bandwidth of 100kHz. + Choose an Input Attenuation of 24dB. + +2. On your lab computer, open the AD9154 SPIPro application (Start > All + Programs > Analog Devices > AD9154 > AD9154 SPI). You will see the GUI shown + in Figure 11 come up. + +.. figure:: ../images/9154ebz_figure_3.png + :align: center + + AD9154 SPIPro at start up + +3. SPIPro Start Up Sequence. + +a. Select “Single” for Links. + +b. Select JESD Mode 0. + +c. Uncheck the “Subclass 1” box + +d. Select “2” for Interpolation. + +e. Press the “Configure DAC and Clock” Button + +f. The JESD204B PLL Lock Readback light should turn green and register bit + settings will be populated. The GUI will look like Figure 12, except that + values in “CodeGrpSync”, “FrameSync”, “GoodCheckSum”, and “InitialLaneSync” + may be different because the link JESD204B Transmitter has not yet been set + up. + +4. DPGDownloader Start Up Sequence + +a. Open DPGDownloader. (Start > All Programs > Analog Devices > DPG > + DPGDownloader). DPGDownloader GUI will come up as shown Figure 13. + +b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress + bar will then show a moving green indication. + +c. Once port configuration is complete, select “Add Generated Waveform” and + “Single Tone”. + +d. Set Data Rate to 750 MHz, Desired Frequency to 112 MHz, Amplitude to -1.0 + dBFS, uncheck unsigned, check Generate Complex Data (I&Q). + +e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 + and DAC3. The DPGDownloader settings should resemble Figure 14. + +f. Click Download (|image14|) and Play (|image15|) in the DPG Downloader screen. The spectrum in Figure 15 will appear on all 4 DAC outputs (J17, J4, J5, and J7), Serial Line Rate will be 7.5Gbps. Figure 16 is a scope capture of the DAC output signal taken on three of the channels. + +5. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI + looks the same as Figure 12. + +6. The current on the 5V supply should read around 1800mA - 1950mA. + +.. figure:: ../images/9154ebz_figure_4.png + :align: center + + Fully Configured AD9154 SPIPro + +.. figure:: ../images/9154ebz_figure_5.png + :align: center + + DPG Downloader Panel at Start Up + +.. figure:: ../images/9154ebz_figure_6.png + :align: center + + Fully Configured DPG Downloader Panel + +.. figure:: ../images/9154ebz_figure_7.png + :align: center + + DAC Output Spectrum Analyzer Display + +8. Here’s what you will see on DAC1, DAC2, and DAC3 on the scope. + +.. figure:: ../images/9154ebz_figure_8.png + :align: center + + DAC Outputs Scope Display + +ACE Software Features +--------------------- + +The ACE software is organized to allow the user to evaluate and control the +AD9122A evaluation board. The “Initial Configuration” wizard, which is only +available for certain boards, controls the DAC and PLL setups. Block diagram +views of the board and chip contain elements that can be used to vary parameters +like ref current and data format. These parameters can be changed using check +boxes, drop down menus, and input boxes. Some parameters do not have settings +shown in the diagram. Double click on the parameter to view the available +settings, seen with the NCO settings below. + +.. image:: ../images/ad9122_nco.png + :align: center + + +.. container:: centeralign + + NCO settings for the AD9122 + +In addition, some parameters can be enabled or disabled. This feature is evident +by the color of the block parameter. For example, if the block parameter is dark +blue, the parameter is enabled. If it is light grey, it is disabled. To enable +or disable a parameter, click on it. + +.. container:: column + + .. + +.. image:: ../images/ad9739a_on.png + :align: center + + +.. container:: column + + .. + +.. image:: ../images/ad9739a_off.png + :align: center + + +.. container:: column + + + .. container:: centeralign + + Enabled parameter + + + +.. container:: column + + + .. container:: centeralign + + Disabled parameter + + + +More direct changes to registers and bit fields can be made in the memory map, +which is linked from the chip block diagram through the “Proceed to Memory Map” +button. In this view, names, addresses, and data can be manually altered by the +user. + + + +.. image:: ../images/ad9122_memmap.png + :align: center + + +.. container:: centeralign + + Bench Set-Up + +ACE also contains the Macro Tool, which can be used to record register reads and +writes. This is executed in the memory map view or with the initialization +wizard. To use, check the “Record Sub-Commands” checkbox and press the record +button. Changes in the memory map, which are bolded until they are applied to +the part, are recorded as UI commands by the macro tool once the changes are +made. Changed register write commands for the controls are also recorded. Hit +“Apply Changes” to execute the commands and make changes in the memory map. To +stop recording, click the “Stop Recording” button. A macro tool page with the +command steps will be created. The macro can be saved using the “Save Macro” +button so that it may be loaded for future use. + +.. image:: ../images/ad9122_macrocommands.png + :align: center + + +.. container:: centeralign + + Macro tool in ACE. The *Stop Recording*, *Record*, and *Save Macro* commands are located at the top of the macro tool. + +The raw macro file will be saved using ACE syntax, which is not easily readable. +To remedy this, the ACE software download includes the Macro to Hex Conversion +Tool. The user can choose to include or exclude register write, reads, and/or +comments in the conversion. The file pathways for the source and save paths +should be the same, except that one should be an .acemacro file and the other +should be a .txt file. The “Convert” button converts and opens the converted +text file, which is easier to read. The conversion tool can also convert back to +an .acemacro file if desired. + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_5.png + :align: center + + +.. container:: column + + .. + +.. image:: ../images/ad9122_m2hconvert_4.png + :align: center + + +.. container:: column + + + .. container:: centeralign + + Conversion set-up for macro to hex + + + +.. container:: column + + + .. container:: centeralign + + Converted text file + + + +For more information about ACE and its features, visit https://wiki.analog.com/resources/tools-software/ace. + +.. |ace_icon_small.png| image:: ../images/ace_icon_small.png +.. |connection_icon.png| image:: ../images/connection_icon.png +.. |image9| image:: ../images/image009.png +.. |image10| image:: ../images/image010.png +.. |image14| image:: ../images/image009.png +.. |image15| image:: ../images/image010.png diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-fmc-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-fmc-ebz.rst new file mode 100644 index 00000000000..39f16b70869 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-fmc-ebz.rst @@ -0,0 +1,140 @@ +SPIPRO AD9154-FMC-EBZ Evaluation Board Quick Start Guide +======================================================== + +Getting Started with the AD9154-FMC-EBZ Evaluation Board and Software +--------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9154-FMC-EBZ` Evaluation Board for ADS7 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Sinusoidal Clock Source +- Spectrum Analyzer +- Oscilloscope +- Data Pattern Generator with FMC Interface ADS7 + +Introduction +------------ + +The AD9154-FMC-EBZ connects to an ADS7 data pattern generator system. The AD9154 +is a quad JESD204B signal processing RF Digital to Analog Converter. The ADS7 +automatically formats the data and sends it to the AD9154-FMC-EBZ via its +JESD204B lanes. The AD9154-FMC-EBZ is an FMC mezzanine card. +12V, +3.3V, and +VADJ power supply rails are provided by the ADS7 system via the FMC connector +P1. A clock distribution chip AD9516 is included on this EVB as a clock fan-out +and frequency divider for the DACCLK, JESD204B SYSREF signals, and a GBTCLK +clock used by the ADS7. There is also an FMC standard I2C bus that is used by +the ADS7 to identify the AD9154-FMC-EBZ. This I2C interface is implemented in +firmware in the AD9154-FMC-EBZ PIC processor (XU1). PIC firmware is installed in +PIC non-volatile memory by ADI. All ADS7 to/from AD9154-FMC-EBZ interface +signals are connected via the FMC connector P1. + +AD9154 Evaluation Software +-------------------------- + +The AD9154 Evaluation Board software runs on the SPIPro graphical user interface +(GUI). It is included on the Evaluation Board CD. Registers on the AD9154 and +AD9516 products are programmed via a USB cable connecting the user’s PC to the +AD9154-FMC-EBZ XP2 connector. Software in the AD9154-FMC-EBZ PIC processor (XU1) +provides the interface between the USB bus and the SPI busses of the AD9154 and +AD9516. + +Hardware Setup +-------------- + +Figure 1 shows the block diagram of the set-up. + +.. image:: ../images/9154fmc_figure_1_lab_block_diagram.png + :align: center + +.. image:: ../images/9154_fmc_figure_2_photo.png + :align: center + +A low phase noise high frequency clock source should be connected to the SMA +connector J1. A spectrum analyzer should be connected to the EVB SMA connector +J4. Connect SMA connectors J5, J14 and J17 of the EVB to an oscilloscope. The +evaluation board connects to the ADS7 through the connector P1. The PC should be +connected to the EVB using the mini-USB connector XP2. Figure 1 shows a block +diagram of the set-up. + +Getting Started +--------------- + +The PC software is included in the CD shipped with the EVB. The installation +will include the software as well as all the AD9154 EVB files including +schematic, board layout, datasheet, this quick start guide and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the customer evaluation board software and support files, including DPGDownloader and SPIPro GUI on your PC. Follow the instructions in the installation wizard and use the default (recommended) installation settings. +2. Plug the AD9154-FMC-EBZ into port FMC_1 of the ADS7 System. Use a USB cable to connect the EVB to your PC and connect the lab equipment to the EVB as shown in Figure 1. +3. Connect the ADS7 unit to your PC via USB and turn on the ADS7. +4. Connect SMA connector J5 to a spectrum analyzer, connect SMA connectors J17, J4 and J14 to an oscilloscope. + +Single Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + + +Single Tone Demo Lab Bench Configuration Procedure: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +These settings configure the AD9154 to output a 181Mhz 0dbFS sine wave using the +ADS7 on all four AD9154 DACs. + +- Configure the hardware according to the hardware set-up instructions given in + the Hardware Setup section above. Set the frequency of the DAC clock signal + generator to 1500MHz, and the output level to 3dBm. The spectrum analyzer can + be configured as shown in Figure 8 with a resolution bandwidth of 300kHz. + Choose an Input Attenuation of 22dB. + +.. figure:: ../images/9154_fmcfigure_6_start_dpg.png + :align: center + + Initial DPG Downloader Panel + +Single Tone Demo Hardware and Software Start Up Procedure: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +1. Run DPG Downloader from Start->Analog Devices->DPG->DPG Downloader. The DPG Downloader GUI will say Evaluation Board: AD9154 and Port Configuration: JESD204B as shown in Figure 3. At this point, the ADS7 FMC power supplies will be turned on. + + 2. Open SPIPro from Start->Analog Devices->AD9154->AD9154 SPI. It will say + AD9154-FMC-EBZ in the upper left hand corner. + +3. Select single link, JESD mode 0, Interpolation 2. Leave all other settings in their default state. Press ‘Configure DAC and Clock’ button. JESD204B PLL lock will turn green. + +.. image:: ../images/9154_fmcfigure_4_ad9154_spi.png + :align: center + +4. In DPG Downloader Window Select Single Tone under the Add Generated Waveforms + Tab. Set Data Rate: 750Mhz, Desired Frequency: 181Mhz, Amplitude: 0dbFS, + Uncheck Unsigned Data, Check Generate Complex Data (I&Q) + +5. Select JESD Mode: Mode 0 + +6. Populate the data playback selections for each DAC output as shown in Figure + 5. + +7. Click Download button and click Play button. The signals shown in figures 7 + and 8 will appear on the DAC outputs (J17, J4, J5, and J14), Serial Line Rate + will be 7.5Gbps. The green SYNC check mark indicates that the JESD204B link + running. + +.. image:: ../images/9154_fmcfigure_7_configured_dpgdownlaoder.png + :align: center + +8. Here’s what you will see on DAC0, DAC1, and DAC3 on the scope + +.. image:: ../images/9154_fmcfigure_8_scope_1.png + :align: center + +9. Here is what you will see at the output of DAC2 on the Spectrum Analyzer. + +.. image:: ../images/9154_fmc_figure_9_sa_1.png + :align: center diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-m6720-ebz.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-m6720-ebz.rst new file mode 100644 index 00000000000..e7292b6663e --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/ad9154-m6720-ebz.rst @@ -0,0 +1,169 @@ +AD9154-ADRF6720-EBZ Evaluation Board Quick Start Guide +====================================================== + +Getting Started with the AD9154-ADRF6720-EBZ Evaluation Board and Software +-------------------------------------------------------------------------- + +What's in the Box +~~~~~~~~~~~~~~~~~ + +- :adi:`AD9154-ADRF6720-EBZ ` Evaluation Board for DPG3 +- Evaluation Board CD +- Mini-USB Cable + +Recommended Equipment List +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- +5VDC Lab Power Supply +- Two Sinusoidal Clock Sources +- Spectrum Analyzer +- Data Pattern Generator Series 3 (DPG3) + +Introduction +------------ + +The AD9154-ADRF6720-EBZ connects to a DPG3. The AD9154 is a quad JESD204B signal +processing RF Digital to Analog Converter. The DPG3 automatically formats the +data and sends it to the AD9154-M6720-EBZ via its JESD204B lanes. The +AD9154-M6720-EBZ includes an AD9154 and two ADRF6720-27 Wideband Quadrature +Modulators with Integrated PLL and VCO. There is a board level passive low pass +filter between the output of each AD9154 DAC and its corresponding ADRF6720-27 +baseband input. The Evaluation Board (EVB) runs from a single +5V lab supply. A +clock distribution chip AD9516 is included on this EVB as a clock fan-out and +frequency divider for the DACCLK, JESD204B SYSREF signals, and a CFRAME clock +used by the DPG3. + +AD9154 and ADRF6720-27 Evaluation Software +------------------------------------------ + +The AD9154 and ADRF6720-27 Evaluation software runs on the easy-to-use SPIPro +graphical user interface (GUI). It is included on the Evaluation Board CD. + +Hardware Setup +-------------- + +Connect +5.0V to P5, GND to P6. A low phase noise high frequency clock source +should be connected to the SMA connector J1 (CLK_IN). A spectrum analyzer should +be connected to the SMA connector J4, RF_OUT_1. Connect a low phase sinusoidal +signal source to J18, the RF local oscillator input to ADRF6720-27_1. (The +ADRF6720-27 on-chip LO synthesizer is not used in this quick start guide.) The +evaluation board connects to the DPG3 through the connector P4. The PC is +connected to the EVB using the mini-USB connector XP2. Figure 1 shows a block +diagram of the set-up. + +.. image:: ../images/9154m6720_figure_1.png + :align: center + +.. image:: ../images/9154m6720_figure_2.png + :align: center + +Getting Started +--------------- + +The PC software is included in the CD shipped with the EVB. The installation +includes the DPG Downloader software as well as all the necessary AD9154 files +including schematic, board layout, datasheet, and other files. + +Initial Set-Up +~~~~~~~~~~~~~~ + +1. Install the DPG Downloader and SPIPro software and support files on your PC. + Follow the instructions in the installation wizard and use the default + (recommended) installation settings. + +2. Use a USB cable to connect the EVB to your PC and connect the lab equipment + to the EVB. + +3. Connect the DPG3 unit to your PC and turn on the unit. + +Single Tone Demonstration +~~~~~~~~~~~~~~~~~~~~~~~~~ + +These settings configure the AD9154 to output a 182Mhz -1dbFS sine wave using +the DPG3 on all four AD9154 DACs. The DAC output signals are I/Q pairs. An +external LO of 1.36GHz is supplied to the ADRF6720-27 chips. The AD9720-27 chips +perform a complex single sideband up-conversion of the sine wave I/Q pairs to a +1542MHz RF signal at the RF_OUT_1 and RF_OUT_2 connectors J4 and J14. 1. +Configure the hardware according to the hardware set-up instructions given in +the Hardware Setup section above. Set the frequency of the DAC clock signal +generator to 1500MHz, and the output level to 3dBm. Set the frequency of the +ADRF6720-27 Synthesizer Local Oscillator Source to 1.36GHz and set its output +amplitude to +4dbm. The spectrum analyzer can be configured as shown in Figure 7 +with a resolution bandwidth of 100kHz. Choose an Input Attenuation of 24dB. 2. +On your lab computer, open the AD9154 SPIPro application (Start > All Programs > +Analog Devices > AD9154 > AD9154 SPI). You will see the GUI shown in Figure 7 +come up. + +.. image:: ../images/9154m6720_figure_3.png + + + +.. image:: ../images/9154m6720_figure_4.png + :align: center + + 3. SPIPro Start Up Sequence. + +a. In the Quick Start Tab Select “Single” for Links. + +b. Select JESD Mode 0. c. Uncheck the “Subclass 1” box. + +d. Select “2” for Interpolation. + +e. Press the “Configure DAC and Clock” Button + +f. The JESD204B PLL Lock Readback light should turn green and register bit + settings will be populated. The GUI will look like Figure 4, except that + values in “CodeGrpSync”, “FrameSync”, “GoodCheckSum”, and “InitialLaneSync” + may be different because the link JESD204B Transmitter has not yet been set + up. + +g. Load Register Settings into the ADRF6720 devices by clicking “Restore + Registers from File” and locating “ADRF6720.csv”. This should be located at + the install directory for the AD9154 SPIPro application. + +h. Click on “ADRF6720” tab for Mod 1 and confirm the GUI matches Figure 5 below. + +.. image:: ../images/9154m6720_figure_5.png + + i. Click on “ADRF67202” tab for Mod 2 and confirm the GUI matches +Figure 6 below. + +.. image:: ../images/9154m6720_figure_6_1.png + :align: center + +4. DPG Downloader Start Up Sequence + +a. Open DPG Downloader. (Start > All Programs > Analog Devices > DPG > + DPGDownloader). DPG Downlader GUI will come up as shown Figure 7. + +b. Select the Port configuration QBF 1X8 85G 425M. The configuration progress + bar will then show a moving green indication. + +c. Once port configuration is complete, select “add generated waveform” and + “single tone”. + +d. Set Data Rate to 750Mhz, Desired Frequency to 182Mhz, Amplitude to -1.0 dBFS, + uncheck unsigned, check Generate Complex Data (I&Q). + +e. Under Data Playback, select I data for DAC 0 and DAC2, and Q data for DAC 1 + and DAC3. + +f. Click Download Button and the Play Button. The spectrum in Figure 9 will + appear on J4, RF_OUT_1. The Serial Line Rate will be 7.5Gbps. + +.. image:: ../images/9154m6720_figure_7.png + + + +.. image:: ../images/9154m6720_figure_8.png + + + +5. On SPIPro Quick Start Tab, click “Read All Registers” and confirm the GUI + looks the same as Figure 4. + +6. The current on the 5V supply should read about 2300mA – 2400mA. + +.. image:: ../images/9154m6720_figure_9.png + + diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/eval-ad9154.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/eval-ad9154.rst new file mode 100644 index 00000000000..c0210357172 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/eval-ad9154.rst @@ -0,0 +1,69 @@ +AD9154 Evaluation Boards +======================== + +The :adi:`AD9154` evaluation boards are available in multiple form factors for +different evaluation setups. + +Documentation and software updates for using High-Speed DAC Evaluation Boards +are included in individual, self-extracting update files. + +Files included in the AD9154 Update: +------------------------------------ + +- SPI Application +- DPGDownloader Panel +- :adi:`AD9154 Data Sheet ` +- :adi:`IBIS Model ` + +.. list-table:: + :header-rows: 1 + + * - Item + - AD9154-EBZ + - AD9154-ADRF6720-EBZ + - AD9154-FMC-EBZ + * - Quick Start (SPIPro) + - :doc:`ad9154-ebz ` + - :doc:`ad9154-adrf6720-ebz ` + - :doc:`ad9154-fmc-ebz ` + * - Quick Start (ACE) + - :doc:`ad9154-ace-ebz ` + - :doc:`ad9154-m6720-ebz ` + - :doc:`ad9154-ace-fmc-ebz ` + * - Schematics + - :download:`RevD <../resources/ad9154-ebz_revd_schematic.pdf>` + - :download:`RevA <../resources/ad9154-adrf6720-ebz_reva_schematic.pdf>` + - :download:`RevA <../resources/ad9154-fmc-ebz_reva_schematic.pdf>` + * - Bill of Materials + - :download:`RevD <../resources/ad9154-ebz_revd_bom.xls>` + - :download:`RevA <../resources/ad9154-adrf6720-ebz_reva_bom.xls>` + - :download:`RevA <../resources/ad9154-fmc-ebz_reva_bom.xls>` + * - PCB Gerber Files + - :download:`RevD <../resources/ad9154-ebz_revd_gerber_files.zip>` + - :download:`RevA <../resources/ad9154-adrf6720-ebz_reva_gerber_files.zip>` + - :download:`RevA <../resources/ad9154-fmc-ebz_reva_gerber_files.zip>` + * - PCB BRD File + - :download:`RevD <../resources/ad9154-ebz_revd.zip>` + - :download:`RevA <../resources/ad9154-adrf6720-ebz_reva.zip>` + - :download:`RevA <../resources/ad9154-fmc-ebz_reva.zip>` + * - PCB Layout PDF + - :download:`RevD <../resources/ad9154-ebz_revd_layout.pdf>` + - :download:`RevA <../resources/ad9154-adrf6720-ebz_reva_layout.pdf>` + - :download:`RevA <../resources/ad9154-fmc-ebz_reva_layout.pdf>` + +Data Pattern Generator +---------------------- + +The Data Pattern Generator (DPG) is a bench-top instrument for driving vectors +into high-speed digital-to-analog converters. The DPG connects to a USB on a PC +and allows a user to download a vector from the PC into the internal memory of +the DPG. Once downloaded, the vector can be played out to an attached evaluation +board for a specific DAC at full speed. This allows for rapid evaluation of the +DAC with both generic and custom-generated test data. + +For more information on the DPG line of pattern generators and software: + +- :dokuwiki:`DAC Software Suite ` +- :dokuwiki:`DPG Lite ` +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`ADS7 ` diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/index.rst new file mode 100644 index 00000000000..9d4620dd14d --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD9154/index.rst @@ -0,0 +1,12 @@ +AD9154 +=============================================================================== + +.. toctree:: + + eval-ad9154 + ad9154-ace-ebz + ad9154-ace-fmc-ebz + ad9154-adrf6720-ebz + ad9154-ebz + ad9154-fmc-ebz + ad9154-m6720-ebz diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/eval-ad917x.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/eval-ad917x.rst new file mode 100644 index 00000000000..697b080eb08 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/eval-ad917x.rst @@ -0,0 +1,74 @@ +AD9171/AD9172/AD9173/AD9174/AD9175/AD9176 Evaluation Board +========================================================== + +The :adi:`AD9171`, :adi:`AD9172`, :adi:`AD9173`, :adi:`AD9174`, :adi:`AD9175` and :adi:`AD9176` evaluation board is an FMC form-factor board with FMC connector that complies to the Vita 57.1 standard. The FMC board uses a Mini-Circuits balun on the DAC output. + +To operate the evaluation board, the user must attach the board to a compatible +FMC carrier board, such as those provided by FPGA vendors. Analog Devices +produces an FPGA carrier called the ADS7-V2, which serves as a digital pattern +generator or data source as well as the power supply for the boards. The AD917x +board has an option to be powered from a lab power supply when used in a special +NCO-only mode. This operation is described in more detail in the User's Guide. +The user must be able to observe the DAC output on a spectrum analyzer. A low +noise clock source is provided on the evaluations boards, the HMC7044 clock +synthesizer, and an option exists for the user to supply a low jitter external +sine or square wave clock as a clock source instead. The evaluation board comes +with software, called ACE, which allows the user to program the SPI port. Via +the SPI port, the DUT (and clock circuitry) can be programmed into any of its +various operating modes. It also comes with the DAC Software Suite which +includes the DPGDownloader for vector generation, download, and transmission to +the evaluation board when using the ADS7-V2. + +Documentation and software updates for using High-Speed DAC Evaluation Boards +are included in individual, self-extracting update files. The latest DPG +Downloader software can be downloaded from here: +:dokuwiki:`High-Speed DAC Software Suite `. +The latest ACE software can be downloaded from here: +:dokuwiki:`Analysis | Control | Evaluation (ACE) Software `. +The plugins for this board can be downloaded from the plugin manager in the ACE +software. + +Files included in the AD9171, AD9172, AD9173, AD9174, AD9175, AD9176 Update: +---------------------------------------------------------------------------- + +- SPI Application +- DPGDownloader Panel +- :adi:`AD9171 Data Sheet ` +- :adi:`AD9172 Data Sheet ` +- :adi:`AD9173 Data Sheet ` +- :adi:`AD9174 Data Sheet ` +- :adi:`AD9175 Data Sheet ` +- :adi:`AD9176 Data Sheet ` + +.. list-table:: + :header-rows: 1 + + * - Item + - AD917(1,2,3,4,5,6)-FMC-EBZ + * - Schematics + - :download:`AD917x-FMC-EBZ Schematic <../resources/ad9172-fmc-ebz_revc_schematic.pdf>` + * - Layout + - :download:`AD917x-FMC-EBZ Layout <../resources/ad9172-fmc-ebz_revc_layout.pdf>` + * - Bill of Materials + - :download:`AD917x-FMC-EBZ BOM <../resources/ad9172-fmc-ebz_revc_bom.zip>` + * - PCB Gerber Files + - :download:`AD917x-FMC-EBZ Gerber Files <../resources/ad9172-fmc-ebz_revc_gerber_files.zip>` + * - PCB BRD File + - :download:`AD917x-FMC-EBZ Board File <../resources/ad9172-fmc-ebz_revc.zip>` + +Data Pattern Generator +---------------------- + +The Data Pattern Generator (DPG) is a bench-top instrument for driving vectors +into high-speed digital-to-analog converters. The DPG connects to a USB on a PC +and allows a user to download a vector from the PC into the internal memory of +the DPG. Once downloaded, the vector can be played out to an attached evaluation +board for a specific DAC at full speed. This allows for rapid evaluation of the +DAC with both generic and custom-generated test data. + +For more information on the DPG line of pattern generators and software: + +- :dokuwiki:`DAC Software Suite ` +- :dokuwiki:`DPG Lite ` +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software ` +- :dokuwiki:`ADS7 ` diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/index.rst new file mode 100644 index 00000000000..6b43246c88d --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/AD917x/index.rst @@ -0,0 +1,6 @@ +AD917x +=============================================================================== + +.. toctree:: + + eval-ad917x diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/images/120mhz_tone_using_50mhznco_shift.png b/docs/solutions/reference-designs/dac-fmc-ebz/images/120mhz_tone_using_50mhznco_shift.png new file mode 100644 index 00000000000..742fd9371ac --- /dev/null +++ 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sha256:8392dc2cc52db9201507ceef3b882616398da9fa9f760864f135afb2eda3d47a +size 9744037 diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/images/scopy_spectrum_analyzer_ad9172_zcu102.jpg b/docs/solutions/reference-designs/dac-fmc-ebz/images/scopy_spectrum_analyzer_ad9172_zcu102.jpg new file mode 100644 index 00000000000..bae0f888976 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/images/scopy_spectrum_analyzer_ad9172_zcu102.jpg @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:de2807814c278792664563952d7e4c0cfd2fdb4f43d2a737d79c24112cd451cd +size 4741611 diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/index.rst new file mode 100644 index 00000000000..90aeaa25a42 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/index.rst @@ -0,0 +1,146 @@ +.. _dac-fmc-ebz: + +DAC-FMC-EBZ +=============================================================================== + +High-Speed JESD204B Digital-to-Analog Converter Evaluation Boards. + +Overview +------------------------------------------------------------------------------- + +The DAC-FMC-EBZ family of evaluation boards provides a platform for evaluating +Analog Devices' high-speed, JESD204B-based digital-to-analog converters (DACs). +These boards are designed to work with the :git-hdl:`AD-DAC-FMC-EBZ HDL +reference design `, supporting a range of DAC devices +from the AD9135/AD9136 through the AD9172/AD9176. + +The evaluation boards connect to a Data Pattern Generator (DPG3) or an ADS7-V2 +controller board via DPG or FMC connectors, enabling quick characterization of +DAC performance including single-tone output, NCO frequency shifting, and +multi-carrier waveform generation. + +Supported devices: + +- :adi:`AD9135` / :adi:`AD9136` -- Dual, 16-bit, 2.8 GSPS DAC +- :adi:`AD9144` -- Quad, 16-bit, 2.8 GSPS DAC +- :adi:`AD9152` -- Dual, 16-bit, 2.25 GSPS DAC +- :adi:`AD9154` -- Quad, 16-bit, 2.4 GSPS DAC +- :adi:`AD9172` / :adi:`AD9174` / :adi:`AD9176` -- Dual, 16-bit, 12.6 GSPS DAC + +.. toctree:: + :hidden: + + user-guide + prerequisites + quickstart/index + AD9136/index + AD9144/index + AD9152/index + AD9154/index + AD917x/index + +Table of contents +------------------------------------------------------------------------------- + +#. Using the evaluation board: + + #. :ref:`User Guide ` -- what you need to know about + the evaluation boards + #. :ref:`Prerequisites ` -- what you need to get + started with the setup + #. :ref:`Quick Start Guides `: + + #. Using the :ref:`ZCU102 ` + #. Using the :ref:`ZC706 ` + +#. :external+hdl:ref:`DAC-FMC-EBZ HDL Reference Design ` which you + must use in your FPGA. + +#. Resources for designing a custom AD9081/AD9082-based platform software + + #. For Linux software: + + #. About the device driver: + + - :external+linux:doc:`JESD204B Transmit Linux driver ` + - :external+linux:doc:`JESD204B Receive Linux driver ` + - :external+linux:doc:`JESD204B/C AXI_ADXCVR High-speed transceivers Linux driver ` + - :external+linux:doc:`AXI DAC HDL Linux driver ` + - :external+linux:doc:`AXI-DMAC DMA Controller Linux driver ` + - :external+linux:doc:`AD9172 Linux device driver ` + + #. About the device tree: + + - :dokuwiki:`Customizing the device tree on the target ` + + #. About the JESD204 utilities: + + - :dokuwiki:`JESD204 (FSM) interface Linux Kernel framework ` + - :dokuwiki:`HMC7044 Clock Jitter Attenuator with JESD204B Linux Driver ` + - :dokuwiki:`JESD204 status utility ` + - :dokuwiki:`JESD204 Eye Scan ` + - :external+hdl:ref:`jesd204` + + #. :ref:`Building Zynq Linux kernel and devicetree ` + #. :ref:`Building ZynqMP Linux kernel and devicetree ` + + #. For No-Os software: + + - :external+no-OS:doc:`projects/dac/ad9172` - no-OS project documentation + +#. AD9135 / AD9136 + + #. :doc:`AD9136 & AD9135 Evaluation Boards ` -- overview, + schematics, BOM, and design files + #. :doc:`AD9136/AD9135-EBZ Quick Start Guide (ACE) ` + #. :doc:`AD9136/AD9135-EBZ Quick Start Guide (SPIPro) ` + #. :doc:`AD9136-FMC-EBZ Quick Start Guide (ACE) ` + +#. AD9144 + + #. :doc:`AD9144 Evaluation Boards ` -- overview, + schematics, BOM, and design files + #. :doc:`AD9144-EBZ Quick Start Guide (ACE) ` + #. :doc:`AD9144-FMC-EBZ Quick Start Guide (ACE) ` + #. :doc:`AD9144-ADRF6720-EBZ Quick Start Guide ` + #. :doc:`AD9144-EBZ Quick Start Guide (SPIPro) ` + #. :doc:`AD9144-FMC-EBZ Quick Start Guide (SPIPro) ` + +#. AD9152 + + #. :doc:`AD9152 Evaluation Board ` -- overview, + schematics, BOM, and design files + #. :doc:`AD9152-ADRF6720-EBZ Quick Start Guide ` + #. :doc:`AD9152-EBZ Quick Start Guide ` + #. :doc:`AD9152-FMC-EBZ Quick Start Guide (ACE) ` + +#. AD9154 + + #. :doc:`AD9154 Evaluation Boards ` -- overview, + schematics, BOM, and design files + #. :doc:`AD9154-EBZ Quick Start Guide (ACE) ` + #. :doc:`AD9154-FMC-EBZ Quick Start Guide (ACE) ` + #. :doc:`AD9154-ADRF6720-EBZ Quick Start Guide ` + #. :doc:`AD9154-EBZ Quick Start Guide (SPIPro) ` + #. :doc:`AD9154-FMC-EBZ Quick Start Guide (SPIPro) ` + #. :doc:`AD9154-ADRF6720-EBZ Quick Start Guide (M6720) ` + +#. AD917x + + #. :doc:`AD9171/AD9172/AD9173/AD9174/AD9175/AD9176 Evaluation Board ` + +#. :ref:`Help and Support ` + +ADI articles +------------------------------------------------------------------------------- + +About JESD standard: + +#. :adi:`JESD204B Survival Guide ` +#. :adi:`JESD204C Primer: What's New and in It for You—Part 1 ` +#. :adi:`JESD204C Primer: What's New and in It for You—Part 2 ` + +Warning +------------------------------------------------------------------------------- + +.. esd-warning:: diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/prerequisites.rst b/docs/solutions/reference-designs/dac-fmc-ebz/prerequisites.rst new file mode 100644 index 00000000000..57cf38c840a --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/prerequisites.rst @@ -0,0 +1,51 @@ +.. _dac-fmc-ebz prerequisites: + +Prerequisites +=============================================================================== + +Hardware Prerequisites +------------------------------------------------------------------------------- + +#. One of the DAC-FMC-EBZ evaluation boards: + + - :adi:`EVAL-AD9135` / :adi:`EVAL-AD9136` + - :adi:`EVAL-AD9144` + - :adi:`EVAL-AD9152` + - :adi:`EVAL-AD9154` + - :adi:`EVAL-AD9172` (AD917x-FMC-EBZ) + +#. One of the following FPGA carrier platforms: + + - `ZCU102 `_ + - `ZC706 `_ + - `VCU118 `_ + - `Arria 10 SoC Development Kit + `_ + + .. note:: + + ADI does not sell or loan FPGA carrier platforms. These must be purchased + separately from the FPGA vendor. + +#. Depending on the carrier platform and interaction method: + + - For ARM/FPGA SoC carriers (ZCU102, ZC706, A10SoC): HDMI/DisplayPort + monitor, USB keyboard, USB mouse + - For all carriers: LAN cable and host PC + +#. RF test equipment: + + - Spectrum analyzer + - Signal generator (low phase noise clock source) + - SMA cables + +#. SD card with at least 16GB of memory + +Software Prerequisites +------------------------------------------------------------------------------- + +- :dokuwiki:`Analysis | Control | Evaluation (ACE) Software + ` -- for DPG3/ADS7-based evaluation +- :dokuwiki:`DPG Downloader ` -- for vector + generation and download +- For Linux-based evaluation: ADI Kuiper Linux SD card image diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/index.rst b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/index.rst new file mode 100644 index 00000000000..97078d34aac --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/index.rst @@ -0,0 +1,93 @@ +.. _dac-fmc-ebz quickstart: + +Quick Start Guides +=============================================================================== + +This section provides quick start guides for evaluating DAC-FMC-EBZ boards on +various FPGA carrier platforms. Each guide covers bitstream programming, booting +a Linux distribution, and verifying the DAC output. + +.. toctree:: + + On ZCU102 + On ZC706 + +Supported Carriers +------------------------------------------------------------------------------- + +All carriers support the AD9135/AD9136, AD9144, AD9152, AD9154, and +AD917x-FMC-EBZ evaluation boards. + +.. list-table:: + :header-rows: 1 + + * - Carrier + - FMC Slot + * - `ZCU102 `_ + - FMC HPC0 + * - `ZC706 `_ + - FMC HPC + * - `VCU118 `_ + - FMC+ + * - `Arria 10 SoC `_ + - FMCA + +Supported Environments +------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Carrier + - HDL + - Linux + - No-OS + * - ZCU102 + - Yes + - Yes + - Yes + * - ZC706 + - Yes + - Yes + - Yes + * - VCU118 + - Yes + - No + - No + * - Arria 10 SoC + - Yes + - No + - No + +Hardware Setup +------------------------------------------------------------------------------- + +.. important:: + + Before connecting the FMC evaluation board to the carrier, ensure that the + carrier is powered off. Improper handling can damage the board or the carrier. + +General setup: + +#. Connect the DAC-FMC-EBZ board to the corresponding FMC connector on + the carrier. +#. If it's the case, connect a low phase noise clock source to the corresponding + clock in port (please check the requirments based on the used board). +#. Connect the DAC output(s) to a spectrum analyzer via SMA cables. +#. Connect UART via USB for serial console (115200 baud, 8N1). +#. Connect Ethernet for network access (Linux). +#. Insert the SD card with ADI Kuiper Linux image. +#. Connect the power supply and power on the carrier. + +ZCU102 + EVAL-AD9172 (No external clock source) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: ../images/ad9172_zcu102_linux.jpg + :width: 800 + +ZC706 + EVAL-AD9172 (No external clock source) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: ../images/ad9172_zc706_linux.jpg + :width: 800 + diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zc706.rst b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zc706.rst new file mode 100644 index 00000000000..081a00c6de4 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zc706.rst @@ -0,0 +1,969 @@ +.. _dac-fmc-ebz quickstart zc706: + +ZC706 & EVAL-AD9172 Quick Start +=============================================================================== + +This guide provides quick instructions on how to setup the +:adi:`EVAL-AD9172 ` on: + +- :xilinx:`ZC706` FMC HPC + +.. image:: ../../images/zc706.png + :width: 900 + +.. esd-warning:: + +Using Linux as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. note:: + + The SD card includes several folders in the root directory of the BOOT + partition. In order to configure the SD card to work with a specific FPGA + board and ADI hardware, several files must be copied onto the root directory. + Using the host PC, drag and drop the required files onto the BOOT partition, + and use the EJECT function when removing the SD card from the reader. + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``uImage`` +- Linux device tree: ``devicetree.dtb`` + +They can either be taken from the SD card -- already generated by us, or you +can build them manually: + +- Instructions on how to choose the boot files from the SD card can be found in + the **Platform-Specific Manual Steps** section from here: + :external+kuiper:ref:`hardware-configuration`. +- Instructions on how to manually build the boot files from source can be found + here: + + - :ref:`linux-kernel zynq` + - :external+hdl:ref:`dac_fmc_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. + +.. important:: + + Some projects provide multiple devicetree files in the SD card's boot + folders. Make sure you select the devicetree that matches your specific use + case. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- SD Card 16GB imaged with :external+kuiper:doc:`Kuiper ` + (check out that guide on how to do it, then come back to this section) +- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZC706` Rev 1.2 or higher FPGA board and its power supply +- :adi:`EVAL-AD9172 ` FMC evaluation board +- SD card with at least 16GB of memory +- Mini-USB cable (UART) +- LAN cable (Ethernet) +- SMA cables +- Spectrum analyzer +- (Optional) USB keyboard & mouse and a HDMI compatible monitor + +More details as to why you need these, can be found at +:ref:`dac-fmc-ebz prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../images/ad9172_zc706_linux.jpg + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9172 ` FMC board to the ZC706 + **HPC** FMC socket +#. Insert SD card into the SD card socket on the FPGA +#. Configure :xilinx:`ZC706` for SD card boot mode (Set the jumpers: + The main one is: SW11 - Big Blue Switch in the middle, which controls the + Boot Mode, it needs to be set: **1: Down, 2: Down, 3: Up, 4: Up, 5: Down**) +#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on + the FPGA board +#. Connect USB UART (Mini-USB) to your host PC +#. Connect the DAC output(s) to a spectrum analyzer via SMA cables +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Connect the power supply for the FPGA +#. Turn on the power switch on the FPGA board +#. Observe Kernel and serial console output messages on your terminal (use + the first ttyUSB or COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + U-Boot 2018.01-21442-gf06dec3cab (Oct 17 2024 - 08:58:28 +0300) Xilinx Zynq ZC706, Build: jenkins-development-build_uboot-35 + + Model: Zynq ZC706 Development Board + Board: Xilinx Zynq + Silicon: v3.1 + I2C: ready + DRAM: ECC disabled 1 GiB + MMC: sdhci@e0100000: 0 (SD) + SF: Detected s25fl128s_64k with page size 512 Bytes, erase size 128 KiB, total 32 MiB + In: serial@e0001000 + Out: serial@e0001000 + Err: serial@e0001000 + Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id + eth0: ethernet@e000b000 + reading uEnv.txt + 407 bytes read in 23 ms (16.6 KiB/s) + Importing environment from SD ... + Hit any key to stop autoboot: 0 + Device: sdhci@e0100000 + Manufacturer ID: 1d + OEM: 4144 + Name: 00000 + Tran Speed: 50000000 + Rd Block Len: 512 + SD version 3.0 + High Capacity: Yes + Capacity: 29.1 GiB + Bus Width: 4-bit + Erase Group Size: 512 Bytes + reading uEnv.txt + 407 bytes read in 24 ms (15.6 KiB/s) + Loaded environment from uEnv.txt + Importing environment from SD ... + Running uenvcmd ... + Copying Linux from SD to RAM... + reading uImage + 8410448 bytes read in 488 ms (16.4 MiB/s) + reading devicetree.dtb + 23194 bytes read in 30 ms (754.9 KiB/s) + ** Unable to read file uramdisk.image.gz ** + ## Booting kernel from Legacy Image at 03000000 ... + Image Name: Linux-6.1.70-284094-g54eb23f4b5c + Image Type: ARM Linux Kernel Image (uncompressed) + Data Size: 8410384 Bytes = 8 MiB + Load Address: 00008000 + Entry Point: 00008000 + Verifying Checksum ... OK + ## Flattened Device Tree blob at 02a00000 + Booting using the fdt blob at 0x2a00000 + Loading Kernel Image ... OK + Loading Device Tree to 1fff7000, end 1ffffa99 ... OK + + Starting kernel ... + + Booting Linux on physical CPU 0x0 + Linux version 6.1.70-284094-g54eb23f4b5c6 (jenkins@romlxbuild1) (arm-xilinx-linux-gnueabi-gcc.real (GCC) 12.2.0, GNU ld (GNU Binutils) 2.39.0.20220819) #209 SMP PREEMPT Fri Nov 8 06:39:15 EET 2024 + CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d + CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache + OF: fdt: Machine model: Xilinx Zynq ZC706 + OF: fdt: earlycon: stdout-path /amba@0/uart@E0001000 not found + Memory policy: Data cache writealloc + cma: Reserved 128 MiB at 0x38000000 + Zone ranges: + Normal [mem 0x0000000000000000-0x000000002fffffff] + HighMem [mem 0x0000000030000000-0x000000003fffffff] + Movable zone start for each node + Early memory node ranges + node 0: [mem 0x0000000000000000-0x000000003fffffff] + Initmem setup node 0 [mem 0x0000000000000000-0x000000003fffffff] + percpu: Embedded 11 pages/cpu s14420 r8192 d22444 u45056 + Built 1 zonelists, mobility grouping on. Total pages: 260608 + Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1 + Dentry cache hash table entries: 131072 (order: 7, 524288 bytes, linear) + Inode-cache hash table entries: 65536 (order: 6, 262144 bytes, linear) + mem auto-init: stack:all(zero), heap alloc:off, heap free:off + Memory: 881952K/1048576K available (12288K kernel code, 818K rwdata, 10376K rodata, 1024K init, 470K bss, 35552K reserved, 131072K cma-reserved, 131072K highmem) + rcu: Preemptible hierarchical RCU implementation. + rcu: RCU event tracing is enabled. + rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. + rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies. + rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 + NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 + efuse mapped to (ptrval) + slcr mapped to (ptrval) + L2C: platform modifies aux control register: 0x72360000 -> 0x72760000 + L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000 + L2C-310 erratum 769419 enabled + L2C-310 enabling early BRESP for Cortex-A9 + L2C-310 full line of zeros enabled for Cortex-A9 + L2C-310 ID prefetch enabled, offset 1 lines + L2C-310 dynamic clock gating enabled, standby mode enabled + L2C-310 cache controller enabled, 8 ways, 512 kB + L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001 + rcu: srcu_init: Setting srcu_struct sizes based on contention. + zynq_clock_init: clkc starts at (ptrval) + Zynq clock init + sched_clock: 64 bits at 167MHz, resolution 6ns, wraps every 4398046511103ns + clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x26703d7dd8, max_idle_ns: 440795208065 ns + Switching to timer-based delay loop, resolution 6ns + clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns + timer #0 at (ptrval), irq=25 + Console: colour dummy device 80x30 + Calibrating delay loop (skipped), value calculated using timer frequency.. 333.33 BogoMIPS (lpj=1666666) + CPU: Testing write buffer coherency: ok + CPU0: Spectre v2: using BPIALL workaround + pid_max: default: 32768 minimum: 301 + Mount-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) + Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes, linear) + CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 + Setting up static identity map for 0x100000 - 0x100060 + rcu: Hierarchical SRCU implementation. + rcu: Max phase no-delay instances is 1000. + smp: Bringing up secondary CPUs ... + CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 + CPU1: Spectre v2: using BPIALL workaround + smp: Brought up 1 node, 2 CPUs + SMP: Total of 2 processors activated (666.66 BogoMIPS). + CPU: All CPU(s) started in SVC mode. + devtmpfs: initialized + VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 + clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns + futex hash table entries: 512 (order: 3, 32768 bytes, linear) + pinctrl core: initialized pinctrl subsystem + NET: Registered PF_NETLINK/PF_ROUTE protocol family + DMA: preallocated 256 KiB pool for atomic coherent allocations + thermal_sys: Registered thermal governor 'step_wise' + platform axi: Fixed dependency cycle(s) with /axi/interrupt-controller@f8f01000 + amba f8801000.etb: Fixed dependency cycle(s) with /replicator/out-ports/port@1/endpoint + amba f8803000.tpiu: Fixed dependency cycle(s) with /replicator/out-ports/port@0/endpoint + amba f8804000.funnel: Fixed dependency cycle(s) with /replicator/in-ports/port/endpoint + amba f889c000.ptm: Fixed dependency cycle(s) with /axi/funnel@f8804000/in-ports/port@0/endpoint + amba f889d000.ptm: Fixed dependency cycle(s) with /axi/funnel@f8804000/in-ports/port@1/endpoint + hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. + hw-breakpoint: maximum watchpoint size is 4 bytes. + e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 27, base_baud = 3125000) is a xuartps + printk: console [ttyPS0] enabled + SCSI subsystem initialized + usbcore: registered new interface driver usbfs + usbcore: registered new interface driver hub + usbcore: registered new device driver usb + mc: Linux media interface: v0.10 + videodev: Linux video capture interface: v2.00 + pps_core: LinuxPPS API ver. 1 registered + pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti + PTP clock support registered + jesd204: created con: id=0, topo=0, link=0, /axi/spi@e0006000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@44A60000 + jesd204: created con: id=1, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@44A60000 <-> /fpga-axi@0/axi-jesd204-tx@44A90000 + jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@44A90000 <-> /fpga-axi@0/axi-ad9172-hpc@44A04000 + jesd204: created con: id=3, topo=0, link=0, /fpga-axi@0/axi-ad9172-hpc@44A04000 <-> /axi/spi@e0006000/ad9172@1 + jesd204: /axi/spi@e0006000/ad9172@1: JESD204[0:0] transition uninitialized -> initialized + jesd204: found 5 devices and 1 topologies + FPGA manager framework + Advanced Linux Sound Architecture Driver Initialized. + clocksource: Switched to clocksource arm_global_timer + NET: Registered PF_INET protocol family + IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear) + tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear) + Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) + TCP established hash table entries: 8192 (order: 3, 32768 bytes, linear) + TCP bind hash table entries: 8192 (order: 5, 131072 bytes, linear) + TCP: Hash tables configured (established 8192 bind 8192) + UDP hash table entries: 512 (order: 2, 16384 bytes, linear) + UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear) + NET: Registered PF_UNIX/PF_LOCAL protocol family + RPC: Registered named UNIX socket transport module. + RPC: Registered udp transport module. + RPC: Registered tcp transport module. + RPC: Registered tcp NFSv4.1 backchannel transport module. + armv7-pmu f8891000.pmu: hw perfevents: no interrupt-affinity property, guessing. + hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available + workingset: timestamp_bits=30 max_order=18 bucket_order=0 + NFS: Registering the id_resolver key type + Key type id_resolver registered + Key type id_legacy registered + nfs4filelayout_init: NFSv4 File Layout Driver Registering... + nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... + fuse: init (API version 7.37) + bounce: pool size: 64 pages + io scheduler mq-deadline registered + io scheduler kyber registered + zynq-pinctrl 700.pinctrl: zynq pinctrl initialized + dma-pl330 f8003000.dma-controller: Loaded driver for PL330 DMAC-241330 + dma-pl330 f8003000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 + brd: module loaded + loop: module loaded + Registered mathworks_ip class + SPI driver spidev has no spi_device_id for adi,swspi + spi-nor spi1.0: found s25fl128s1, expected n25q128a11 + spi-nor spi1.0: s25fl128s1 (16384 Kbytes) + 5 fixed-partitions partitions found on MTD device spi1.0 + Creating 5 MTD partitions on "spi1.0": + 0x000000000000-0x000000500000 : "boot" + 0x000000500000-0x000000520000 : "bootenv" + 0x000000520000-0x000000540000 : "config" + 0x000000540000-0x000000fc0000 : "image" + 0x000000fc0000-0x000001000000 : "spare" + MACsec IEEE 802.1AE + tun: Universal TUN/TAP device driver, 1.6 + macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 44 (00:0a:35:00:01:22) + usbcore: registered new interface driver asix + usbcore: registered new interface driver ax88179_178a + usbcore: registered new interface driver cdc_ether + usbcore: registered new interface driver net1080 + usbcore: registered new interface driver cdc_subset + usbcore: registered new interface driver zaurus + usbcore: registered new interface driver cdc_ncm + usbcore: registered new interface driver r8153_ecm + usbcore: registered new interface driver uas + usbcore: registered new interface driver usb-storage + usbcore: registered new interface driver usbserial_generic + usbserial: USB Serial support registered for generic + usbcore: registered new interface driver ftdi_sio + usbserial: USB Serial support registered for FTDI USB Serial Device + usbcore: registered new interface driver upd78f0730 + usbserial: USB Serial support registered for upd78f0730 + ULPI transceiver vendor/product ID 0x0424/0x0007 + Found SMSC USB3320 ULPI transceiver. + ULPI integrity check: passed. + ci_hdrc ci_hdrc.0: EHCI Host Controller + ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 + ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 + usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.01 + usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 + usb usb1: Product: EHCI Host Controller + usb usb1: Manufacturer: Linux 6.1.70-284094-g54eb23f4b5c6 ehci_hcd + usb usb1: SerialNumber: ci_hdrc.0 + hub 1-0:1.0: USB hub found + hub 1-0:1.0: 1 port detected + SPI driver ads7846 has no spi_device_id for ti,tsc2046 + SPI driver ads7846 has no spi_device_id for ti,ads7843 + SPI driver ads7846 has no spi_device_id for ti,ads7845 + SPI driver ads7846 has no spi_device_id for ti,ads7873 + i2c_dev: i2c /dev entries driver + si570 1-005d: registered, current frequency 156250000 Hz + i2c i2c-0: Added multiplexed i2c bus 1 + i2c 2-0039: Fixed dependency cycle(s) with /fpga-axi@0/axi_hdmi@70e00000/port/endpoint + adv7511 2-0039: supply avdd not found, using dummy regulator + adv7511 2-0039: supply dvdd not found, using dummy regulator + adv7511 2-0039: supply pvdd not found, using dummy regulator + adv7511 2-0039: supply bgvdd not found, using dummy regulator + adv7511 2-0039: supply dvdd-3v not found, using dummy regulator + adv7511: probe of 2-0039 failed with error -5 + i2c i2c-0: Added multiplexed i2c bus 2 + at24 3-0054: supply vcc not found, using dummy regulator + at24 3-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write + i2c i2c-0: Added multiplexed i2c bus 3 + pca953x 4-0021: supply vcc not found, using dummy regulator + pca953x 4-0021: using no AI + i2c i2c-0: Added multiplexed i2c bus 4 + rtc rtc0: invalid alarm value: 2026-04-23T35:84:00 + rtc-pcf8563 5-0051: registered as rtc0 + rtc-pcf8563 5-0051: setting system clock to 2026-04-23T12:08:35 UTC (1776946115) + i2c i2c-0: Added multiplexed i2c bus 5 + at24 6-0050: supply vcc not found, using dummy regulator + at24 6-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write + i2c i2c-0: Added multiplexed i2c bus 6 + i2c i2c-0: Added multiplexed i2c bus 7 + i2c i2c-0: Added multiplexed i2c bus 8 + pca954x 0-0074: registered 8 multiplexed busses for I2C switch pca9548 + gspca_main: v2.14.0 registered + usbcore: registered new interface driver uvcvideo + cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer with timeout 10s + Xilinx Zynq CpuIdle Driver started + failed to register cpuidle driver + sdhci: Secure Digital Host Controller Interface driver + sdhci: Copyright(c) Pierre Ossman + sdhci-pltfm: SDHCI platform and OF driver helper + ledtrig-cpu: registered to indicate activity on CPUs + hid: raw HID events driver (C) Jiri Kosina + usbcore: registered new interface driver usbhid + usbhid: USB HID core driver + SPI driver fb_seps525 has no spi_device_id for syncoam,seps525 + mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA + hmc7044 spi0.0: Read/Write check failed (0x0) + mmc0: new high speed SDHC card at address 0001 + mmcblk0: mmc0:0001 00000 29.1 GiB + mmcblk0: p1 p2 p3 + hmc7044 spi0.0: Probed, SPI read support failed + jesd204: /axi/spi@e0006000/hmc7044@0,jesd204:0,parent=spi0.0: Using as SYSREF provider + ad9172 spi0.1: ad917x DAC Chip ID: 4 + ad9172 spi0.1: ad917x DAC Product ID: 9172 + ad9172 spi0.1: ad917x DAC Product Grade: 0 + ad9172 spi0.1: ad917x DAC Product Revision: 2 + ad9172 spi0.1: ad917x Revision: 1.1.1 + ad9172 spi0.1: CLK Input rate 368640000 + ad9172 spi0.1: PLL lock status 1, DLL lock status: 1 + ad9172 spi0.1: Serdes PLL Locked (stat: 3) + ad9172 spi0.1: Probed. + SPI driver adis16475 has no spi_device_id for adi,adis16470 + SPI driver adis16475 has no spi_device_id for adi,adis16475-1 + SPI driver adis16475 has no spi_device_id for adi,adis16475-2 + SPI driver adis16475 has no spi_device_id for adi,adis16475-3 + SPI driver adis16475 has no spi_device_id for adi,adis16477-1 + SPI driver adis16475 has no spi_device_id for adi,adis16477-2 + SPI driver adis16475 has no spi_device_id for adi,adis16477-3 + SPI driver adis16475 has no spi_device_id for adi,adis16465-1 + SPI driver adis16475 has no spi_device_id for adi,adis16465-2 + SPI driver adis16475 has no spi_device_id for adi,adis16465-3 + SPI driver adis16475 has no spi_device_id for adi,adis16467-1 + SPI driver adis16475 has no spi_device_id for adi,adis16467-2 + SPI driver adis16475 has no spi_device_id for adi,adis16467-3 + SPI driver adis16475 has no spi_device_id for adi,adis16500 + SPI driver adis16475 has no spi_device_id for adi,adis16501 + SPI driver adis16475 has no spi_device_id for adi,adis16505-1 + SPI driver adis16475 has no spi_device_id for adi,adis16505-2 + SPI driver adis16475 has no spi_device_id for adi,adis16505-3 + SPI driver adis16475 has no spi_device_id for adi,adis16507-1 + SPI driver adis16475 has no spi_device_id for adi,adis16507-2 + SPI driver adis16475 has no spi_device_id for adi,adis16507-3 + SPI driver adis16475 has no spi_device_id for adi,adis16575-2 + SPI driver adis16475 has no spi_device_id for adi,adis16575-3 + SPI driver adis16475 has no spi_device_id for adi,adis16576-2 + SPI driver adis16475 has no spi_device_id for adi,adis16576-3 + SPI driver adis16475 has no spi_device_id for adi,adis16577-2 + SPI driver adis16475 has no spi_device_id for adi,adis16577-3 + axi_adxcvr_drv 44a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTX2 at 0x44A60000. Number of lanes: 4. + axi-jesd204-tx 44a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x44A90000. Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. + axi_sysid 45000000.axi-sysid-0: AXI System ID core version (1.01.a) found + axi_sysid 45000000.axi-sysid-0: [dac_fmc_ebz] [JESD:M=4 L=4 S=1 NP=16 LINKS=1 DEVICE_CODE=5 DAC_DEVICE=AD9172 DAC_MODE=04 DAC_FIFO_ADDR_WIDTH=14] on [zc706] git branch git <2156ac7e874a1dc321d9f64a325009fafe563419> clean [2024-11-01 11:12:04] UTC + fpga_manager fpga0: Xilinx Zynq FPGA Manager registered + usbcore: registered new interface driver snd-usb-audio + NET: Registered PF_INET6 protocol family + Segment Routing with IPv6 + In-situ OAM (IOAM) with IPv6 + sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + NET: Registered PF_PACKET protocol family + NET: Registered PF_IEEE802154 protocol family + Key type dns_resolver registered + zynq_pm_remap_ocm: OCM pool is not available + zynq_pm_suspend_init: Unable to map OCM. + Registering SWP/SWPB emulation handler + of-fpga-region fpga-full: FPGA Region probed + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> initialized + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition initialized -> probed + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition probed -> idle + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition idle -> device_init + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition device_init -> link_init + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_init -> link_supported + hmc7044 spi0.0: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_supported -> link_pre_setup + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clk_sync_stage3 -> link_setup + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition clocks_enable -> link_enable + ad9172 spi0.1: Link0 code_grp_sync: f + ad9172 spi0.1: Link0 frame_sync_stat: f + ad9172 spi0.1: Link0 good_checksum_stat: f + ad9172 spi0.1: Link0 init_lane_sync_stat: f + ad9172 spi0.1: Link0 4 lanes @ 7372800 kBps + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_enable -> link_running + jesd204: /axi/spi@e0006000/ad9172@1,jesd204:1,parent=spi0.1: JESD204[0:0] transition link_running -> opt_post_running_stage + cf_axi_dds 44a04000.axi-ad9172-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x44A04000 mapped to 0x(ptrval), probed DDS AD917x + input: gpio_keys as /devices/soc0/gpio_keys/input/input0 + of_cfs_init + of_cfs_init: OK + clk: Not disabling unused clocks + ALSA device list: + No soundcards found. + EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Quota mode: disabled. + VFS: Mounted root (ext4 filesystem) on device 179:2. + devtmpfs: mounted + Freeing unused kernel image (initmem) memory: 1024K + Run /sbin/init as init process + systemd[1]: systemd 247.3-7+rpi1+deb11u6 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified) + systemd[1]: Detected architecture arm. + + Welcome to Kuiper GNU/Linux 11.2 (bullseye)! + + systemd[1]: Set hostname to . + systemd[1]: /lib/systemd/system/plymouth-start.service:16: Unit configured to use KillMode=none. This is unsafe, as it disables systemd's process lifecycle management for the service. Please update your service to use a safer KillMode=, such as 'mixed' or 'control-group'. Support for KillMode=none is deprecated and will eventually be removed. + systemd[1]: /lib/systemd/system/iiod.service:14: Invalid environment assignment, ignoring: $IIOD_EXTRA_OPTS= + systemd[1]: Queued start job for default target Graphical Interface. + random: crng init done + systemd[1]: system-getty.slice: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling. + systemd[1]: (This warning is only shown for the first unit using IP firewalling.) + systemd[1]: Created slice system-getty.slice. + [ OK ] Created slice system-getty.slice. + systemd[1]: Created slice system-modprobe.slice. + [ OK ] Created slice system-modprobe.slice. + systemd[1]: Created slice system-serial\x2dgetty.slice. + [ OK ] Created slice system-serial\x2dgetty.slice. + systemd[1]: Created slice system-systemd\x2dfsck.slice. + [ OK ] Created slice system-systemd\x2dfsck.slice. + systemd[1]: Created slice User and Session Slice. + [ OK ] Created slice User and Session Slice. + systemd[1]: Started Forward Password Requests to Wall Directory Watch. + [ OK ] Started Forward Password R…uests to Wall Directory Watch. + systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped. + systemd[1]: Reached target Slices. + [ OK ] Reached target Slices. + systemd[1]: Reached target Swap. + [ OK ] Reached target Swap. + systemd[1]: Listening on Syslog Socket. + [ OK ] Listening on Syslog Socket. + systemd[1]: Listening on fsck to fsckd communication Socket. + [ OK ] Listening on fsck to fsckd communication Socket. + systemd[1]: Listening on initctl Compatibility Named Pipe. + [ OK ] Listening on initctl Compatibility Named Pipe. + systemd[1]: Condition check resulted in Journal Audit Socket being skipped. + systemd[1]: Listening on Journal Socket (/dev/log). + [ OK ] Listening on Journal Socket (/dev/log). + systemd[1]: Listening on Journal Socket. + [ OK ] Listening on Journal Socket. + systemd[1]: Listening on udev Control Socket. + [ OK ] Listening on udev Control Socket. + systemd[1]: Listening on udev Kernel Socket. + [ OK ] Listening on udev Kernel Socket. + systemd[1]: Condition check resulted in Huge Pages File System being skipped. + systemd[1]: Condition check resulted in POSIX Message Queue File System being skipped. + systemd[1]: Mounting RPC Pipe File System... + Mounting RPC Pipe File System... + systemd[1]: Mounting Kernel Debug File System... + Mounting Kernel Debug File System... + systemd[1]: Condition check resulted in Kernel Trace File System being skipped. + systemd[1]: Condition check resulted in Kernel Module supporting RPCSEC_GSS being skipped. + systemd[1]: Starting Restore / save the current clock... + Starting Restore / save the current clock... + systemd[1]: Starting Set the console keyboard layout... + Starting Set the console keyboard layout... + systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped. + systemd[1]: Starting Load Kernel Module configfs... + Starting Load Kernel Module configfs... + systemd[1]: Starting Load Kernel Module drm... + Starting Load Kernel Module drm... + systemd[1]: Starting Load Kernel Module fuse... + Starting Load Kernel Module fuse... + systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. + systemd[1]: Condition check resulted in File System Check on Root Device being skipped. + systemd[1]: Starting Journal Service... + Starting Journal Service... + systemd[1]: Starting Load Kernel Modules... + Starting Load Kernel Modules... + systemd[1]: Starting Remount Root and Kernel File Systems... + Starting Remount Root and Kernel File Systems... + systemd[1]: Starting Coldplug All udev Devices... + Starting Coldplug All udev Devices... + systemd[1]: Mounted RPC Pipe File System. + [ OK ] Mounted RPC Pipe File System. + systemd[1]: Mounted Kernel Debug File System. + [ OK ] Mounted Kernel Debug File System. + systemd[1]: Finished Restore / save the current clock. + [ OK ] Finished Restore / save the current clock. + systemd[1]: modprobe@configfs.service: Succeeded. + systemd[1]: Finished Load Kernel Module configfs. + [ OK ] Finished Load Kernel Module configfs. + systemd[1]: modprobe@drm.service: Succeeded. + systemd[1]: Finished Load Kernel Module drm. + [ OK ] Finished Load Kernel Module drm. + systemd[1]: modprobe@fuse.service: Succeeded. + systemd[1]: Finished Load Kernel Module fuse. + [ OK ] Finished Load Kernel Module fuse. + systemd[1]: systemd-modules-load.service: Main process exited, code=exited, status=1/FAILURE + systemd[1]: systemd-modules-load.service: Failed with result 'exit-code'. + systemd[1]: Failed to start Load Kernel Modules. + [FAILED] Failed to start Load Kernel Modules. + See 'systemctl status systemd-modules-load.service' for details. + systemd[1]: Finished Set the console keyboard layout. + [ OK ] Finished Set the console keyboard layout. + systemd[1]: Started Journal Service. + [ OK ] Started Journal Service. + Mounting FUSE Control File System... + Mounting Kernel Configuration File System... + EXT4-fs (mmcblk0p2): re-mounted. Quota mode: disabled. + Starting Apply Kernel Variables... + [ OK ] Finished Remount Root and Kernel File Systems. + [ OK ] Mounted FUSE Control File System. + [ OK ] Mounted Kernel Configuration File System. + [ OK ] Finished Apply Kernel Variables. + Starting Flush Journal to Persistent Storage... + Starting Load/Save Random Seed... + Starting Create System Users... + [ OK ] Finished Coldplug All udev Devices. + [ OK ] Finished Load/Save Random Seed. + [ OK ] Finished Create System Users. + Starting Helper to synchronize boot up for ifupdown... + Starting Create Static Device Nodes in /dev... + Starting Wait for udev To …plete Device Initialization... + [ OK ] Finished Helper to synchronize boot up for ifupdown. + [ OK ] Finished Create Static Device Nodes in /dev. + [ OK ] Reached target Local File Systems (Pre). + Starting Rule-based Manage…for Device Events and Files... + [ OK ] Finished Flush Journal to Persistent Storage. + [ OK ] Started Rule-based Manager for Device Events and Files. + Starting Show Plymouth Boot Screen... + [ OK ] Started Show Plymouth Boot Screen. + [ OK ] Started Forward Password R…s to Plymouth Directory Watch. + [ OK ] Reached target Local Encrypted Volumes. + [ OK ] Found device /dev/ttyPS0. + [ OK ] Found device /dev/disk/by-partuuid/5c29002e-01. + Starting File System Check…isk/by-partuuid/5c29002e-01... + [ OK ] Started File System Check Daemon to report status. + [ OK ] Finished Wait for udev To Complete Device Initialization. + [ OK ] Finished File System Check…/disk/by-partuuid/5c29002e-01. + Mounting /boot... + [ OK ] Mounted /boot. + [ OK ] Reached target Local File Systems. + Starting Set console font and keymap... + Starting Raise network interfaces... + Starting Preprocess NFS configuration... + Starting Tell Plymouth To Write Out Runtime Data... + Starting Create Volatile Files and Directories... + [ OK ] Finished Set console font and keymap. + [ OK ] Finished Preprocess NFS configuration. + [ OK ] Finished Tell Plymouth To Write Out Runtime Data. + [ OK ] Reached target NFS client services. + [ OK ] Reached target Remote File Systems (Pre). + [ OK ] Reached target Remote File Systems. + [ OK ] Finished Create Volatile Files and Directories. + Starting Network Time Synchronization... + Starting Update UTMP about System Boot/Shutdown... + [ OK ] Finished Update UTMP about System Boot/Shutdown. + Starting Load Kernel Modules... + [ OK ] Started Network Time Synchronization. + [ OK ] Finished Raise network interfaces. + [ OK ] Reached target System Time Set. + [ OK ] Reached target System Time Synchronized. + [FAILED] Failed to start Load Kernel Modules. + See 'systemctl status systemd-modules-load.service' for details. + [ OK ] Reached target System Initialization. + [ OK ] Started CUPS Scheduler. + [ OK ] Started Daily apt download activities. + [ OK ] Started Daily apt upgrade and clean activities. + [ OK ] Started Periodic ext4 Onli…ata Check for All Filesystems. + [ OK ] Started Discard unused blocks once a week. + [ OK ] Started Daily rotation of log files. + [ OK ] Started Daily man-db regeneration. + [ OK ] Started Daily Cleanup of Temporary Directories. + [ OK ] Reached target Paths. + [ OK ] Reached target Timers. + [ OK ] Listening on Avahi mDNS/DNS-SD Stack Activation Socket. + [ OK ] Listening on CUPS Scheduler. + [ OK ] Listening on D-Bus System Message Bus Socket. + [ OK ] Listening on Erlang Port Mapper Daemon Activation Socket. + [ OK ] Listening on GPS (Global P…ioning System) Daemon Sockets. + [ OK ] Listening on triggerhappy.socket. + [ OK ] Reached target Sockets. + [ OK ] Reached target Basic System. + Starting Analog Devices power up/down sequence... + Starting Avahi mDNS/DNS-SD Stack... + [ OK ] Started Regular background program processing daemon. + [ OK ] Started D-Bus System Message Bus. + Starting dphys-swapfile - …unt, and delete a swap file... + Starting Remove Stale Onli…t4 Metadata Check Snapshots... + [ OK ] Started fan-control. + Starting Fix DP audio and X11 for Jupiter... + Starting Creating IIOD Context Attributes...... + Starting Authorization Manager... + Starting DHCP Client Daemon... + Starting LSB: Switch to on…nless shift key is pressed)... + Starting LSB: rng-tools (Debian variant)... + Starting System Logging Service... + Starting User Login Management... + Starting triggerhappy global hotkey daemon... + Starting Disk Manager... + Starting WPA supplicant... + [ OK ] Started triggerhappy global hotkey daemon. + [ OK ] Started System Logging Service. + [ OK ] Finished Fix DP audio and X11 for Jupiter. + [ OK ] Started DHCP Client Daemon. + [ OK ] Finished dphys-swapfile - …mount, and delete a swap file. + [ OK ] Started WPA supplicant. + [ OK ] Started LSB: rng-tools (Debian variant). + [ OK ] Started Authorization Manager. + [ OK ] Started Avahi mDNS/DNS-SD Stack. + [ OK ] Reached target Network. + [ OK ] Reached target Network is Online. + Starting Modem Manager... + Starting CUPS Scheduler... + [ OK ] Started Erlang Port Mapper Daemon. + Starting HTTP based time synchronization tool... + Starting Internet superserver... + Starting /etc/rc.local Compatibility... + Starting OpenBSD Secure Shell server... + Starting Permit User Sessions... + [ OK ] Finished Analog Devices power up/down sequence. + [ OK ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots. + [ OK ] Started /etc/rc.local Compatibility. + [ OK ] Started User Login Management. + [ OK ] Started Internet superserver. + [ OK ] Started Unattended Upgrades Shutdown. + [ OK ] Finished Permit User Sessions. + Starting Light Display Manager... + Starting Hold until boot process finishes up... + [ OK ] Started CUPS Scheduler. + [ OK ] Started Make remote CUPS printers available locally. + [ OK ] Started HTTP based time synchronization tool. + [ OK ] Started LSB: Switch to ond…(unless shift key is pressed). + [ OK ] Started Modem Manager. + [ OK ] Started Disk Manager. + [FAILED] Failed to start VNC Server for X11. + + Raspbian GNU/Linux 11 analog ttyPS0 + + analog login: root (automatic login) + + Linux analog 6.1.70-284094-g54eb23f4b5c6 #209 SMP PREEMPT Fri Nov 8 06:39:15 EET 2024 armv7l + + The programs included with the Debian GNU/Linux system are free software; + the exact distribution terms for each program are described in the + individual files in /usr/share/doc/*/copyright. + + Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent + permitted by applicable law. + Last login: Thu Apr 23 13:06:11 BST 2026 on ttyPS0 + root@analog:~# + +Useful commands for the serial terminal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The below commands are to be run in the serial terminal connected to the FPGA. + +**Login Information** + +user: analog +password: analog + +To find out the IP of the FPGA board, run the following command and take the +IP specified at "eth0 inet": + +.. shell:: + + $ifconfig + +To see the IIO devices detected, run: + +.. shell:: + + $iio_info | grep iio:device + root@analog:~# iio_info | grep iio:device + iio:device0: xadc + iio:device1: hmc7044 + iio:device2: axi-ad9172-hpc (buffer capable) + +To use the :dokuwiki:`JESD204 status utility `, +run: + +.. shell:: + + $jesd_status + (DEVICES) Found 1 JESD204 Link Layer peripherals + + (0): axi-jesd204-tx/44a90000.axi-jesd204-tx [*] + + (STATUS) + Link is enabled + Link Status DATA + Measured Link Clock (MHz) 184.325 + Reported Link Clock (MHz) 184.320 + Measured Device Clock (MHz) 184.325 + Reported Device Clock (MHz) 184.320 + Desired Device Clock (MHz) 184.320 + Lane rate (MHz) 7372.800 + Lane rate / 40 (MHz) 184.320 + LMFC rate (MHz) 11.520 + SYSREF captured Yes + SYSREF alignment error No + SYNC~ deasserted + + You can also use 'q' to quit and 'a' or 'd' to move between devices! + F1axi-jesd204-tx/44a90000.axi-jesd204-txF9Quit + +To power off the system, run the following command, and wait for the final +message to be printed, then power off the FPGA board from the switch as well. + +.. shell:: + + $poweroff + +To reboot the system, run: + +.. shell:: + + $reboot + +.. important:: + + Even though this is Linux, this is a persistent file system. Care should + be taken not to corrupt the file system -- please shut down things, don't + just turn off the power switch. Depending on your monitor, the standard + power off could be hiding. You can do this from the terminal as well with + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. + +Scopy +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. important:: + + Make sure to download/update to the latest version of + :external+scopy:doc:`Scopy `. + +:external+scopy:doc:`Scopy ` can be used to connect remotetly to the +setup and control it. Configure the DAC plugin with the desired waveform and +frequency. + +In the below example the :adi:`EVAL-AD9172 ` had no external clock +generator connected to it, the DAC0 pin was connected to a spectrum +analyzer using a SMA cable: + +- Connect to the setup (DAC plugin) using setup's IP address + + .. image:: ../images/scopy_1_ad9172_zc706.png + :width: 800 + +- Chose the waveform + + .. image:: ../images/scopy_2_ad9172_zc706.png + :width: 800 + +- Visualising the waveform using an exterenal spectrum analyzer + + .. image:: ../images/scopy_spectrum_analyzer_ad9172_zc706.jpg + :width: 800 + +IIO Oscilloscope +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. important:: + + Make sure to download/update to the latest version of + :git-iio-oscilloscope:`IIO Oscilloscope `. + +Once done with the installation or an update of the latest IIO Oscilloscope, +open the application. The user needs to supply a URI which will be used in the +context creation of the IIO Oscilloscope. + +In the below example the :adi:`EVAL-AD9172 ` had no external clock +generator connected to it, the DAC0 pin was connected to a spectrum +analyzer using a SMA cable: + +- Press ``Refresh`` to display available IIO Devices and press ``Connect``. + + .. image:: ../images/iio_osc_1_ad9172_zc706.png + :width: 800 + +- After the board is connected, you can set the device to output a waveform + + .. image:: ../images/iio_osc_2_ad9172_zc706.png + :width: 800 + +- Visualising the waveform using an exterenal spectrum analyzer + + .. image:: ../images/iio_osc_spectrum_analyzer_ad9172_zc706.jpg + :width: 800 + +Using no-OS as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot file: ``system_top.xsa`` +- no-OS project: :git-no-os:`projects/ad9172` + +Instructions on how to build the boot files from source can be found here: + +- :external+no-OS:doc:`projects/dac/ad9172` - no-OS project documentation +- :external+hdl:ref:`dac_fmc_ebz`. More HDL build details at + :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx Vivado and Vitis (downloading Vitis from + `here `_ + will include Vivado as well) +- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZC706` Rev 1.2 or higher FPGA board and its power supply +- :adi:`EVAL-AD9172 ` FMC evaluation board +- 2x Mini-USB cables, one for UART and one for JTAG +- (Optional) USB keyboard & mouse and a HDMI-compatible monitor + +More details as to why you need these, can be found at +:ref:`dac-fmc-ebz prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../images/ad9172_zc706_noos.jpg + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9172 ` FMC board to the ZC706 + **HPC** FMC socket +#. Configure :xilinx:`ZC706` for JTAG boot mode (Set SW11: + **1: Down, 2: Down, 3: Down, 4: Down, 5: Down**) +#. Connect USB UART (Mini-USB) to your host PC +#. Connect USB JTAG (Mini-USB) to your host PC +#. Turn on the power switch on the FPGA board +#. Observe console output messages on your terminal (use the first ttyUSB or + COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + Zynq MP First Stage Boot Loader + Release 2023.2 Apr 16 2026 - 12:10:38 + PMU-FW is not running, certain applications may not be supported. + WARNING: Read/Write check failed (0x0) + Probed, SPI read support failed + Using JESD FSM + ad917x DAC Chip ID: 4 + ad917x DAC Product ID: 9172 + ad917x DAC Product Grade: 0 + ad917x DAC Product Revision: 2 + ad917x Revision: 1.1.1 + CLK Input rate 8 + PLL lock status 1, DLL lock status: 1 + Serdes PLL Locked (stat: 3) + ad9172_init : AD917x Rev 1 successfully initialized + WARNING: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode + tx_adxcvr: OK (7372800 kHz) + Link0 code_grp_sync: f + Link0 frame_sync_stat: f + Link0 good_checksum_stat: f + Link0 init_lane_sync_stat: f + Link0 4 lanes @ 7372800 kBps + tx_dac: Successfully initialized (368649291 Hz) + tx_jesd status: + Link is enabled + Measured Link Clock: 184.325 MHz + Reported Link Clock: 184.320 MHz + Lane rate: 7372.800 MHz + Lane rate / 40: 184.320 MHz + LMFC rate: 11.520 MHz + SYNC~: deasserted + Link status: DATA + SYSREF captured: Yes + SYSREF alignment error: No + Set dds frequency at 40 MHz + Bye \ No newline at end of file diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zcu102.rst b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zcu102.rst new file mode 100644 index 00000000000..03d4b4ee542 --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/quickstart/zcu102.rst @@ -0,0 +1,1256 @@ +.. _dac-fmc-ebz quickstart zcu102: + +ZCU102 & EVAL-AD9172 Quick Start +=============================================================================== + +This guide provides quick instructions on how to setup the +:adi:`EVAL-AD9172 ` on: + +- :xilinx:`ZCU102` FMC HPC0 + +.. image:: ../../images/zcu102.jpg + :width: 900 + +.. esd-warning:: + +Using Linux as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. note:: + + The SD card includes several folders in the root directory of the BOOT + partition. In order to configure the SD card to work with a specific FPGA + board and ADI hardware, several files must be copied onto the root directory. + Using the host PC, drag and drop the required files onto the BOOT partition, + and use the EJECT function when removing the SD card from the reader. + +The following files are needed for the system to boot: + +- HDL boot image: ``BOOT.BIN`` +- Linux Kernel image: ``Image`` +- Linux device tree: ``system.dtb`` + +They can either be taken from the SD card -- already generated by us, or you +can build them manually: + +- Instructions on how to choose the boot files from the SD card can be found in + the **Platform-Specific Manual Steps** section from here: + :external+kuiper:ref:`hardware-configuration`. +- Instructions on how to manually build the boot files from source can be found + here: + + - :ref:`linux-kernel zynqmp` + - :external+hdl:ref:`dac_fmc_ebz` build documentation. More HDL build + details at :external+hdl:ref:`build_hdl`. + +.. important:: + + Some projects provide multiple devicetree files in the SD card's boot + folders. Make sure you select the devicetree that matches your specific use + case. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- SD Card 16GB imaged with :external+kuiper:doc:`Kuiper ` + (check out that guide on how to do it, then come back to this section) +- A UART terminal (Putty/Tera Term/Minicom, etc.) with baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZCU102` Rev 1.0 FPGA board and its power supply +- :adi:`EVAL-AD9172 ` FMC evaluation board +- SD card with at least 16GB of memory +- Micro-USB cable (UART) +- LAN cable (Ethernet) +- SMA cables +- Spectrum analyzer +- (Optional) USB keyboard & mouse and a HDMI compatible monitor + +More details as to why you need these, can be found at +:ref:`dac-fmc-ebz prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../images/ad9172_zcu102_linux.jpg + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9172 ` FMC board to the ZCU102 + **HPC0** FMC socket +#. Insert SD card into the SD card socket on the FPGA +#. Configure :xilinx:`ZCU102` for SD card boot mode (mode SW6[4:1] switch in + the position **OFF,OFF,OFF,ON** as seen in the below picture) + + .. image:: ../../images/zcu102_1p0_bootmode.jpg + :width: 400 + +#. Plug-in an Ethernet cable from your router/switch to the Ethernet port on + the FPGA board +#. Connect USB UART J83 (Micro USB) to your host PC +#. Connect the DAC output(s) to a spectrum analyzer via SMA cables +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Connect the power supply for the FPGA +#. Turn on the power switch on the FPGA board +#. Observe Kernel and serial console output messages on your terminal (use + the first ttyUSB or COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + U-Boot 2018.01-01677-geb93226123b (Mar 09 2026 - 12:20:54 +0200) Xilinx ZynqMP ZCU102 revA, Build: jenkins-development-build_uboot-69 + + I2C: ready + DRAM: 4 GiB + EL Level: EL2 + Chip ID: zu9eg + MMC: sdhci@ff170000: 0 (SD) + *** Warning - bad CRC, using default environment + + In: serial@ff000000 + Out: serial@ff000000 + Err: serial@ff000000 + Bootmode: LVL_SHFT_SD_MODE1 + Net: ZYNQ GEM: ff0e0000, phyaddr 15, interface rgmii-id + + Warning: ethernet@ff0e0000 using MAC address from ROM + eth0: ethernet@ff0e0000 + Hit any key to stop autoboot: 0 + switch to partitions #0, OK + mmc0 is current device + Device: sdhci@ff170000 + Manufacturer ID: 3 + OEM: 5344 + Name: SD32G + Tran Speed: 50000000 + Rd Block Len: 512 + SD version 3.0 + High Capacity: Yes + Capacity: 29.7 GiB + Bus Width: 4-bit + Erase Group Size: 512 Bytes + reading system.dtb + 58811 bytes read in 25 ms (2.2 MiB/s) + reading Image + 42959360 bytes read in 2874 ms (14.3 MiB/s) + ## Flattened Device Tree blob at 04000000 + Booting using the fdt blob at 0x4000000 + Loading Device Tree to 000000000ffee000, end 000000000ffff5ba ... OK + + Starting kernel ... + + [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] + [ 0.000000] Linux version 6.12.77-ge2f9fe8e3654 (root@fcb2e2309be5) (aarch64-linux-gnu-gcc (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0, GNU ld (GNU Binutils for Ubuntu) 2.42) #1 SMP Thu Mar 26 12:20:17 UTC 2026 + [ 0.000000] Machine model: ZynqMP ZCU102 Rev1.0 + [ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8') + [ 0.000000] printk: legacy bootconsole [cdns0] enabled + [ 0.000000] efi: UEFI not found. + [ 0.000000] OF: reserved mem: 0x000000003ed00000..0x000000003ed3ffff (256 KiB) nomap non-reusable memory@3ed00000 + [ 0.000000] OF: reserved mem: 0x000000003ef00000..0x000000003ef3ffff (256 KiB) nomap non-reusable memory@3ef00000 + [ 0.000000] Zone ranges: + [ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff] + [ 0.000000] DMA32 empty + [ 0.000000] Normal [mem 0x0000000100000000-0x000000087fffffff] + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000000000000-0x000000003ecfffff] + [ 0.000000] node 0: [mem 0x000000003ed00000-0x000000003ed3ffff] + [ 0.000000] node 0: [mem 0x000000003ed40000-0x000000003eefffff] + [ 0.000000] node 0: [mem 0x000000003ef00000-0x000000003ef3ffff] + [ 0.000000] node 0: [mem 0x000000003ef40000-0x000000007fffffff] + [ 0.000000] node 0: [mem 0x0000000800000000-0x000000087fffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff] + [ 0.000000] cma: Reserved 256 MiB at 0x0000000070000000 on node -1 + [ 0.000000] psci: probing for conduit method from DT. + [ 0.000000] psci: PSCIv1.1 detected in firmware. + [ 0.000000] psci: Using standard PSCI v0.2 function IDs + [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. + [ 0.000000] psci: SMC Calling Convention v1.5 + [ 0.000000] percpu: Embedded 21 pages/cpu s45592 r8192 d32232 u86016 + [ 0.000000] Detected VIPT I-cache on CPU0 + [ 0.000000] CPU features: detected: ARM erratum 845719 + [ 0.000000] alternatives: applying boot alternatives + [ 0.000000] Kernel command line: earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait + [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048576 + [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off + [ 0.000000] software IO TLB: area num 4. + [ 0.000000] software IO TLB: mapped [mem 0x000000006c000000-0x0000000070000000] (64MB) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 + [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 + [ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000 + [ 0.000000] Root IRQ handler: gic_handle_irq + [ 0.000000] GIC: Using split EOI/Deactivate mode + [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. + [ 0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys). + [ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns + [ 0.000000] sched_clock: 57 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns + [ 0.008332] Console: colour dummy device 80x25 + [ 0.012465] printk: legacy console [tty0] enabled + [ 0.017129] printk: legacy bootconsole [cdns0] disabled + [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034] + [ 0.000000] Linux version 6.12.77-ge2f9fe8e3654 (root@fcb2e2309be5) (aarch64-linux-gnu-gcc (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0, GNU ld (GNU Binutils for Ubuntu) 2.42) #1 SMP Thu Mar 26 12:20:17 UTC 2026 + [ 0.000000] Machine model: ZynqMP ZCU102 Rev1.0 + [ 0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8') + [ 0.000000] printk: legacy bootconsole [cdns0] enabled + [ 0.000000] efi: UEFI not found. + [ 0.000000] OF: reserved mem: 0x000000003ed00000..0x000000003ed3ffff (256 KiB) nomap non-reusable memory@3ed00000 + [ 0.000000] OF: reserved mem: 0x000000003ef00000..0x000000003ef3ffff (256 KiB) nomap non-reusable memory@3ef00000 + [ 0.000000] Zone ranges: + [ 0.000000] DMA [mem 0x0000000000000000-0x00000000ffffffff] + [ 0.000000] DMA32 empty + [ 0.000000] Normal [mem 0x0000000100000000-0x000000087fffffff] + [ 0.000000] Movable zone start for each node + [ 0.000000] Early memory node ranges + [ 0.000000] node 0: [mem 0x0000000000000000-0x000000003ecfffff] + [ 0.000000] node 0: [mem 0x000000003ed00000-0x000000003ed3ffff] + [ 0.000000] node 0: [mem 0x000000003ed40000-0x000000003eefffff] + [ 0.000000] node 0: [mem 0x000000003ef00000-0x000000003ef3ffff] + [ 0.000000] node 0: [mem 0x000000003ef40000-0x000000007fffffff] + [ 0.000000] node 0: [mem 0x0000000800000000-0x000000087fffffff] + [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x000000087fffffff] + [ 0.000000] cma: Reserved 256 MiB at 0x0000000070000000 on node -1 + [ 0.000000] psci: probing for conduit method from DT. + [ 0.000000] psci: PSCIv1.1 detected in firmware. + [ 0.000000] psci: Using standard PSCI v0.2 function IDs + [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. + [ 0.000000] psci: SMC Calling Convention v1.5 + [ 0.000000] percpu: Embedded 21 pages/cpu s45592 r8192 d32232 u86016 + [ 0.000000] Detected VIPT I-cache on CPU0 + [ 0.000000] CPU features: detected: ARM erratum 845719 + [ 0.000000] alternatives: applying boot alternatives + [ 0.000000] Kernel command line: earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait + [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) + [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) + [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1048576 + [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off + [ 0.000000] software IO TLB: area num 4. + [ 0.000000] software IO TLB: mapped [mem 0x000000006c000000-0x0000000070000000] (64MB) + [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 + [ 0.000000] rcu: Hierarchical RCU implementation. + [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. + [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. + [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4 + [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 + [ 0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000 + [ 0.000000] Root IRQ handler: gic_handle_irq + [ 0.000000] GIC: Using split EOI/Deactivate mode + [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. + [ 0.000000] arch_timer: cp15 timer(s) running at 100.00MHz (phys). + [ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns + [ 0.000000] sched_clock: 57 bits at 100MHz, resolution 10ns, wraps every 4398046511100ns + [ 0.008332] Console: colour dummy device 80x25 + [ 0.012465] printk: legacy console [tty0] enabled + [ 0.017129] printk: legacy bootconsole [cdns0] disabled + [ 0.022351] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=400000) + [ 0.022370] pid_max: default: 32768 minimum: 301 + [ 0.022474] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.022498] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) + [ 0.023911] rcu: Hierarchical SRCU implementation. + [ 0.023922] rcu: Max phase no-delay instances is 1000. + [ 0.024157] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level + [ 0.024262] EFI services will not be available. + [ 0.024433] smp: Bringing up secondary CPUs ... + [ 0.024841] Detected VIPT I-cache on CPU1 + [ 0.024905] CPU1: Booted secondary processor 0x0000000001 [0x410fd034] + [ 0.025353] Detected VIPT I-cache on CPU2 + [ 0.025397] CPU2: Booted secondary processor 0x0000000002 [0x410fd034] + [ 0.025806] Detected VIPT I-cache on CPU3 + [ 0.025851] CPU3: Booted secondary processor 0x0000000003 [0x410fd034] + [ 0.025910] smp: Brought up 1 node, 4 CPUs + [ 0.025948] SMP: Total of 4 processors activated. + [ 0.025957] CPU: All CPU(s) started at EL2 + [ 0.025965] CPU features: detected: 32-bit EL0 Support + [ 0.025976] CPU features: detected: CRC32 instructions + [ 0.026018] alternatives: applying system-wide alternatives + [ 0.027007] Memory: 3738368K/4194304K available (18944K kernel code, 1952K rwdata, 17364K rodata, 3584K init, 725K bss, 190200K reserved, 262144K cma-reserved) + [ 0.027746] devtmpfs: initialized + [ 0.034239] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns + [ 0.034268] futex hash table entries: 1024 (order: 4, 65536 bytes, linear) + [ 0.039676] 22080 pages in range for non-PLT usage + [ 0.039696] 513600 pages in range for PLT usage + [ 0.039808] pinctrl core: initialized pinctrl subsystem + [ 0.040871] NET: Registered PF_NETLINK/PF_ROUTE protocol family + [ 0.041566] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations + [ 0.041688] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations + [ 0.041866] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations + [ 0.041905] audit: initializing netlink subsys (disabled) + [ 0.042156] audit: type=2000 audit(0.032:1): state=initialized audit_enabled=0 res=1 + [ 0.042431] cpuidle: using governor menu + [ 0.042521] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. + [ 0.042619] ASID allocator initialised with 65536 entries + [ 0.049412] /axi/interrupt-controller@f9010000: Fixed dependency cycle(s) with /axi/interrupt-controller@f9010000 + [ 0.049570] /axi/pcie@fd0e0000: Fixed dependency cycle(s) with /axi/pcie@fd0e0000 + [ 0.052157] /axi/pcie@fd0e0000: Fixed dependency cycle(s) with /axi/pcie@fd0e0000 + [ 0.052233] /axi/pcie@fd0e0000: Fixed dependency cycle(s) with /axi/pcie@fd0e0000/legacy-interrupt-controller + [ 0.056027] /axi/display@fd4a0000: Fixed dependency cycle(s) with /dpcon + [ 0.056102] /dpcon: Fixed dependency cycle(s) with /axi/display@fd4a0000 + [ 0.057402] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages + [ 0.057415] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page + [ 0.057428] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages + [ 0.057438] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page + [ 0.057449] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages + [ 0.057459] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page + [ 0.057471] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages + [ 0.057480] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page + [ 0.122683] raid6: neonx8 gen() 2269 MB/s + [ 0.190751] raid6: neonx4 gen() 2213 MB/s + [ 0.258815] raid6: neonx2 gen() 2115 MB/s + [ 0.326897] raid6: neonx1 gen() 1816 MB/s + [ 0.394964] raid6: int64x8 gen() 1415 MB/s + [ 0.463028] raid6: int64x4 gen() 1567 MB/s + [ 0.531098] raid6: int64x2 gen() 1398 MB/s + [ 0.599178] raid6: int64x1 gen() 1038 MB/s + [ 0.599188] raid6: using algorithm neonx8 gen() 2269 MB/s + [ 0.667219] raid6: .... xor() 1654 MB/s, rmw enabled + [ 0.667230] raid6: using neon recovery algorithm + [ 0.667633] iommu: Default domain type: Translated + [ 0.667645] iommu: DMA domain TLB invalidation policy: strict mode + [ 0.667996] SCSI subsystem initialized + [ 0.668178] usbcore: registered new interface driver usbfs + [ 0.668213] usbcore: registered new interface driver hub + [ 0.668248] usbcore: registered new device driver usb + [ 0.668441] mc: Linux media interface: v0.10 + [ 0.668482] videodev: Linux video capture interface: v2.00 + [ 0.668534] pps_core: LinuxPPS API ver. 1 registered + [ 0.668546] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti + [ 0.668566] PTP clock support registered + [ 0.668605] EDAC MC: Ver: 3.0.0 + [ 0.668937] zynqmp-ipi-mbox mailbox@ff9905c0: Registered ZynqMP IPI mbox with TX/RX channels. + [ 0.669481] jesd204: created con: id=0, topo=0, link=0, /axi/spi@ff040000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@84a60000 + [ 0.669515] jesd204: created con: id=1, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@84a60000 <-> /fpga-axi@0/axi-jesd204-tx@84a90000 + [ 0.669542] jesd204: created con: id=2, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@84a90000 <-> /fpga-axi@0/axi-ad9172-hpc@84a04000 + [ 0.669596] jesd204: created con: id=3, topo=0, link=0, /fpga-axi@0/axi-ad9172-hpc@84a04000 <-> /axi/spi@ff040000/ad9172@1 + [ 0.669631] jesd204: /axi/spi@ff040000/ad9172@1: JESD204[0:0] transition uninitialized -> initialized + [ 0.669655] jesd204: found 5 devices and 1 topologies + [ 0.669713] FPGA manager framework + [ 0.669758] Advanced Linux Sound Architecture Driver Initialized. + [ 0.670346] Bluetooth: Core ver 2.22 + [ 0.670375] NET: Registered PF_BLUETOOTH protocol family + [ 0.670386] Bluetooth: HCI device and connection manager initialized + [ 0.670400] Bluetooth: HCI socket layer initialized + [ 0.670412] Bluetooth: L2CAP socket layer initialized + [ 0.670429] Bluetooth: SCO socket layer initialized + [ 0.670861] vgaarb: loaded + [ 0.671103] clocksource: Switched to clocksource arch_sys_counter + [ 0.671294] VFS: Disk quotas dquot_6.6.0 + [ 0.671317] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) + [ 0.677032] NET: Registered PF_INET protocol family + [ 0.677202] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) + [ 0.679958] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) + [ 0.680004] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) + [ 0.680023] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) + [ 0.680245] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear) + [ 0.681059] TCP: Hash tables configured (established 32768 bind 32768) + [ 0.681144] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) + [ 0.681228] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) + [ 0.681390] NET: Registered PF_UNIX/PF_LOCAL protocol family + [ 0.681816] RPC: Registered named UNIX socket transport module. + [ 0.681830] RPC: Registered udp transport module. + [ 0.681839] RPC: Registered tcp transport module. + [ 0.681848] RPC: Registered tcp-with-tls transport module. + [ 0.681857] RPC: Registered tcp NFSv4.1 backchannel transport module. + [ 0.682824] PCI: CLS 0 bytes, default 64 + [ 0.683815] Initialise system trusted keyrings + [ 0.683926] workingset: timestamp_bits=62 max_order=20 bucket_order=0 + [ 0.684390] NFS: Registering the id_resolver key type + [ 0.684417] Key type id_resolver registered + [ 0.684428] Key type id_legacy registered + [ 0.684451] nfs4filelayout_init: NFSv4 File Layout Driver Registering... + [ 0.684464] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... + [ 0.684489] jffs2: version 2.2. (NAND) (SUMMARY) © 2001-2006 Red Hat, Inc. + [ 0.684554] fuse: init (API version 7.41) + [ 0.741053] NET: Registered PF_ALG protocol family + [ 0.741070] xor: measuring software checksum speed + [ 0.742382] 8regs : 2518 MB/sec + [ 0.743706] 32regs : 2498 MB/sec + [ 0.745103] arm64_neon : 2368 MB/sec + [ 0.745113] xor: using function: 8regs (2518 MB/sec) + [ 0.745124] Key type asymmetric registered + [ 0.745135] Asymmetric key parser 'x509' registered + [ 0.745180] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246) + [ 0.745195] io scheduler mq-deadline registered + [ 0.745205] io scheduler kyber registered + [ 0.745224] io scheduler bfq registered + [ 0.749326] ledtrig-cpu: registered to indicate activity on CPUs + [ 0.785532] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled + [ 0.793035] brd: module loaded + [ 0.796477] loop: module loaded + [ 0.796900] Registered mathworks_ip class + [ 0.797460] mtdoops: mtd device (mtddev=name/number) must be supplied + [ 0.800894] tun: Universal TUN/TAP device driver, 1.6 + [ 0.801019] CAN device driver interface + [ 0.801583] SPI driver wl1271_spi has no spi_device_id for ti,wl1271 + [ 0.801596] SPI driver wl1271_spi has no spi_device_id for ti,wl1273 + [ 0.801606] SPI driver wl1271_spi has no spi_device_id for ti,wl1281 + [ 0.801616] SPI driver wl1271_spi has no spi_device_id for ti,wl1283 + [ 0.801626] SPI driver wl1271_spi has no spi_device_id for ti,wl1285 + [ 0.801635] SPI driver wl1271_spi has no spi_device_id for ti,wl1801 + [ 0.801645] SPI driver wl1271_spi has no spi_device_id for ti,wl1805 + [ 0.801655] SPI driver wl1271_spi has no spi_device_id for ti,wl1807 + [ 0.801664] SPI driver wl1271_spi has no spi_device_id for ti,wl1831 + [ 0.801674] SPI driver wl1271_spi has no spi_device_id for ti,wl1835 + [ 0.801683] SPI driver wl1271_spi has no spi_device_id for ti,wl1837 + [ 0.801811] usbcore: registered new interface driver asix + [ 0.801850] usbcore: registered new interface driver ax88179_178a + [ 0.801887] usbcore: registered new interface driver cdc_ether + [ 0.801927] usbcore: registered new interface driver net1080 + [ 0.801964] usbcore: registered new interface driver cdc_subset + [ 0.802003] usbcore: registered new interface driver zaurus + [ 0.802042] usbcore: registered new interface driver cdc_ncm + [ 0.802079] usbcore: registered new interface driver r8153_ecm + [ 0.803304] usbcore: registered new interface driver uas + [ 0.803346] usbcore: registered new interface driver usb-storage + [ 0.803421] usbcore: registered new interface driver usbserial_generic + [ 0.803448] usbserial: USB Serial support registered for generic + [ 0.803480] usbcore: registered new interface driver ftdi_sio + [ 0.803504] usbserial: USB Serial support registered for FTDI USB Serial Device + [ 0.803537] usbcore: registered new interface driver upd78f0730 + [ 0.803561] usbserial: USB Serial support registered for upd78f0730 + [ 0.805272] rtc_zynqmp ffa60000.rtc: registered as rtc0 + [ 0.805297] rtc_zynqmp ffa60000.rtc: setting system clock to 2026-04-16T11:23:06 UTC (1776338586) + [ 0.805374] i2c_dev: i2c /dev entries driver + [ 0.806036] usbcore: registered new interface driver uvcvideo + [ 0.807516] Bluetooth: HCI UART driver ver 2.3 + [ 0.807531] Bluetooth: HCI UART protocol H4 registered + [ 0.807541] Bluetooth: HCI UART protocol BCSP registered + [ 0.807566] Bluetooth: HCI UART protocol LL registered + [ 0.807577] Bluetooth: HCI UART protocol ATH3K registered + [ 0.807603] Bluetooth: HCI UART protocol Three-wire (H5) registered + [ 0.807649] Bluetooth: HCI UART protocol Intel registered + [ 0.807673] Bluetooth: HCI UART protocol QCA registered + [ 0.807713] usbcore: registered new interface driver bcm203x + [ 0.807754] usbcore: registered new interface driver bpa10x + [ 0.807792] usbcore: registered new interface driver bfusb + [ 0.807833] usbcore: registered new interface driver btusb + [ 0.807888] usbcore: registered new interface driver ath3k + [ 0.807994] EDAC MC: ECC not enabled + [ 0.808349] sdhci: Secure Digital Host Controller Interface driver + [ 0.808361] sdhci: Copyright(c) Pierre Ossman + [ 0.808370] sdhci-pltfm: SDHCI platform and OF driver helper + [ 0.808621] SMCCC: SOC_ID: ID = jep106:0049:0000 Revision = 0x24738093 + [ 0.808705] zynqmp_firmware_probe Platform Management API v1.1 + [ 0.808750] zynqmp_firmware_probe Trustzone version v1.0 + [ 0.839766] zynqmp-aes zynqmp-aes.0: will run requests pump with realtime priority + [ 0.839988] zynqmp_rsa zynqmp_rsa.0: This driver is deprecated. Please migrate to xilinx-rsa driver + [ 0.840560] usbcore: registered new interface driver usbhid + [ 0.840573] usbhid: USB HID core driver + [ 0.840729] SPI driver fb_seps525 has no spi_device_id for syncoam,seps525 + [ 0.849223] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 (0,8000003f) counters available + [ 0.849771] axi_sysid 85000000.axi-sysid-0: AXI System ID core version (1.01.a) found + [ 0.849966] axi_sysid 85000000.axi-sysid-0: [dac_fmc_ebz] [JESD:M=4 L=4 S=1 NP=16 LINKS=1 DEVICE_CODE=5 DAC_DEVICE=AD9172 DAC_MODE=04 DAC_OFFLOAD:TYPE=0 SIZE=262144] on [zcu102] git branch git <5da8736cb717e92a827934dd1c272b5c07c8e871> clean [2026-03-20 18:23:21] UTC + [ 0.850717] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered + [ 0.851144] usbcore: registered new interface driver snd-usb-audio + [ 0.852694] pktgen: Packet Generator for packet performance testing. Version: 2.75 + [ 0.853233] Initializing XFRM netlink socket + [ 0.853294] NET: Registered PF_INET6 protocol family + [ 0.853874] Segment Routing with IPv6 + [ 0.853919] In-situ OAM (IOAM) with IPv6 + [ 0.853984] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver + [ 0.854346] NET: Registered PF_PACKET protocol family + [ 0.854365] NET: Registered PF_KEY protocol family + [ 0.854474] can: controller area network core + [ 0.854511] NET: Registered PF_CAN protocol family + [ 0.854523] can: raw protocol + [ 0.854534] can: broadcast manager protocol + [ 0.854546] can: netlink gateway - max_hops=1 + [ 0.854631] Bluetooth: RFCOMM TTY layer initialized + [ 0.854647] Bluetooth: RFCOMM socket layer initialized + [ 0.854670] Bluetooth: RFCOMM ver 1.11 + [ 0.854684] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 + [ 0.854695] Bluetooth: BNEP filters: protocol multicast + [ 0.854707] Bluetooth: BNEP socket layer initialized + [ 0.854717] Bluetooth: HIDP (Human Interface Emulation) ver 1.2 + [ 0.854730] Bluetooth: HIDP socket layer initialized + [ 0.854917] 9pnet: Installing 9P2000 support + [ 0.854938] NET: Registered PF_IEEE802154 protocol family + [ 0.854968] Key type dns_resolver registered + [ 0.863162] registered taskstats version 1 + [ 0.863177] Loading compiled-in X.509 certificates + [ 0.868852] Btrfs loaded, zoned=no, fsverity=no + [ 0.869095] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa) + [ 0.882142] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 22, base_baud = 6249999) is a xuartps + [ 0.882200] printk: legacy console [ttyPS0] enabled + [ 2.555387] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 23, base_baud = 6249999) is a xuartps + [ 2.569640] hmc7044 spi1.0: Read/Write check failed (0x0) + [ 2.618004] hmc7044 spi1.0: Probed, SPI read support failed + [ 2.623889] jesd204: /axi/spi@ff040000/hmc7044@0,jesd204:0,parent=spi1.0: Using as SYSREF provider + [ 2.635786] ad9172 spi1.1: ad917x DAC Chip ID: 4 + [ 2.640416] ad9172 spi1.1: ad917x DAC Product ID: 9172 + [ 2.645566] ad9172 spi1.1: ad917x DAC Product Grade: 0 + [ 2.650706] ad9172 spi1.1: ad917x DAC Product Revision: 2 + [ 2.656114] ad9172 spi1.1: ad917x Revision: 1.1.1 + [ 2.660819] ad9172 spi1.1: CLK Input rate 368640000 + [ 2.991223] ad9172 spi1.1: PLL lock status 1, DLL lock status: 1 + [ 3.215164] ad9172 spi1.1: Serdes PLL Locked (stat: 3) + [ 3.220542] ad9172 spi1.1: Probed. + [ 3.224736] spi-nor spi0.0: SPI-NOR-UniqueID 4a960c00191f0016007c7bc4aaf2 + [ 3.231541] spi-nor spi0.0: found mt25qu512a, expected m25p80 + [ 3.237883] 4 fixed-partitions partitions found on MTD device spi0.0 + [ 3.244255] Creating 4 MTD partitions on "spi0.0": + [ 3.249046] 0x000000000000-0x000000100000 : "qspi-fsbl-uboot" + [ 3.255753] 0x000000100000-0x000000600000 : "qspi-linux" + [ 3.261860] 0x000000600000-0x000000620000 : "qspi-device-tree" + [ 3.268487] 0x000000620000-0x000000c00000 : "qspi-rootfs" + [ 3.279579] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM + [ 3.286270] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM + [ 3.292877] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM + [ 3.299485] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM + [ 3.306819] i2c i2c-0: using pinctrl states for GPIO recovery + [ 3.312757] i2c i2c-0: using generic GPIOs for recovery + [ 3.318394] pca953x 0-0020: supply vcc not found, using dummy regulator + [ 3.325110] pca953x 0-0020: using no AI + [ 3.330684] pca953x 0-0021: supply vcc not found, using dummy regulator + [ 3.337376] pca953x 0-0021: using no AI + [ 3.342092] pca954x 0-0075: supply vdd not found, using dummy regulator + [ 3.349284] ina2xx 2-0040: supply vs not found, using dummy regulator + [ 3.356557] ina2xx 2-0040: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.363192] ina2xx 2-0041: supply vs not found, using dummy regulator + [ 3.370383] ina2xx 2-0041: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.376982] ina2xx 2-0042: supply vs not found, using dummy regulator + [ 3.384174] ina2xx 2-0042: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.390785] ina2xx 2-0043: supply vs not found, using dummy regulator + [ 3.397976] ina2xx 2-0043: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.404572] ina2xx 2-0044: supply vs not found, using dummy regulator + [ 3.411746] ina2xx 2-0044: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.418351] ina2xx 2-0045: supply vs not found, using dummy regulator + [ 3.425542] ina2xx 2-0045: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.432143] ina2xx 2-0046: supply vs not found, using dummy regulator + [ 3.439338] ina2xx 2-0046: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.445947] ina2xx 2-0047: supply vs not found, using dummy regulator + [ 3.453132] ina2xx 2-0047: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.459739] ina2xx 2-004a: supply vs not found, using dummy regulator + [ 3.466925] ina2xx 2-004a: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.473544] ina2xx 2-004b: supply vs not found, using dummy regulator + [ 3.480729] ina2xx 2-004b: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.487175] i2c i2c-0: Added multiplexed i2c bus 2 + [ 3.492357] ina2xx 3-0040: supply vs not found, using dummy regulator + [ 3.499622] ina2xx 3-0040: power monitor ina226 (Rshunt = 2000 uOhm) + [ 3.506233] ina2xx 3-0041: supply vs not found, using dummy regulator + [ 3.513416] ina2xx 3-0041: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.520022] ina2xx 3-0042: supply vs not found, using dummy regulator + [ 3.527209] ina2xx 3-0042: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.533823] ina2xx 3-0043: supply vs not found, using dummy regulator + [ 3.541006] ina2xx 3-0043: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.547612] ina2xx 3-0044: supply vs not found, using dummy regulator + [ 3.554792] ina2xx 3-0044: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.561397] ina2xx 3-0045: supply vs not found, using dummy regulator + [ 3.568601] ina2xx 3-0045: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.575216] ina2xx 3-0046: supply vs not found, using dummy regulator + [ 3.582397] ina2xx 3-0046: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.589003] ina2xx 3-0047: supply vs not found, using dummy regulator + [ 3.596203] ina2xx 3-0047: power monitor ina226 (Rshunt = 5000 uOhm) + [ 3.602633] i2c i2c-0: Added multiplexed i2c bus 3 + [ 3.654411] i2c i2c-0: Added multiplexed i2c bus 4 + [ 3.659417] i2c i2c-0: Added multiplexed i2c bus 5 + [ 3.664219] pca954x 0-0075: registered 4 multiplexed busses for I2C mux pca9544 + [ 3.671626] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 40 + [ 3.678668] i2c i2c-1: using pinctrl states for GPIO recovery + [ 3.684622] i2c i2c-1: using generic GPIOs for recovery + [ 3.690276] pca954x 1-0074: supply vdd not found, using dummy regulator + [ 3.697383] at24 6-0054: supply vcc not found, using dummy regulator + [ 3.704313] at24 6-0054: 1024 byte 24c08 EEPROM, writable, 1 bytes/write + [ 3.711102] i2c i2c-1: Added multiplexed i2c bus 6 + [ 3.716507] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.723833] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.731147] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.738461] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.745778] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.753089] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.760408] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.767721] si5341 7-0036: no regulator set, defaulting vdd_sel to 2.5V for out + [ 3.775802] si5341 7-0036: Chip: 5341 Grade: 1 Rev: 3 + [ 3.804621] i2c i2c-1: Added multiplexed i2c bus 7 + [ 3.811696] si570 8-005d: registered, current frequency 300000000 Hz + [ 3.818120] i2c i2c-1: Added multiplexed i2c bus 8 + [ 3.825203] si570 9-005d: registered, current frequency 156250000 Hz + [ 3.831626] i2c i2c-1: Added multiplexed i2c bus 9 + [ 3.836687] si5324 10-0069: si5328 probed + [ 3.892893] si5324 10-0069: si5328 probe successful + [ 3.897836] i2c i2c-1: Added multiplexed i2c bus 10 + [ 3.902897] i2c i2c-1: Added multiplexed i2c bus 11 + [ 3.907972] i2c i2c-1: Added multiplexed i2c bus 12 + [ 3.913039] i2c i2c-1: Added multiplexed i2c bus 13 + [ 3.917929] pca954x 1-0074: registered 8 multiplexed busses for I2C switch pca9548 + [ 3.925713] pca954x 1-0075: supply vdd not found, using dummy regulator + [ 3.933048] ad7291 14-002f: probe with driver ad7291 failed with error -5 + [ 3.940033] at24 14-0050: supply vcc not found, using dummy regulator + [ 3.946795] at24 14-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write + [ 3.953563] i2c i2c-1: Added multiplexed i2c bus 14 + [ 3.958638] i2c i2c-1: Added multiplexed i2c bus 15 + [ 3.963724] i2c i2c-1: Added multiplexed i2c bus 16 + [ 3.968800] i2c i2c-1: Added multiplexed i2c bus 17 + [ 3.973883] i2c i2c-1: Added multiplexed i2c bus 18 + [ 3.978952] i2c i2c-1: Added multiplexed i2c bus 19 + [ 3.984023] i2c i2c-1: Added multiplexed i2c bus 20 + [ 3.989088] i2c i2c-1: Added multiplexed i2c bus 21 + [ 3.993979] pca954x 1-0075: registered 8 multiplexed busses for I2C switch pca9548 + [ 4.001610] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 41 + [ 4.010975] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s + [ 4.035720] cf_axi_dds 84a04000.axi-ad9172-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.02.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD917x + [ 4.053034] mmc0: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit + [ 4.076654] axi_adxcvr_drv 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.05.a) using QPLL on GTH4. Number of lanes: 4. + [ 4.087505] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed + [ 4.098227] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> initialized + [ 4.103084] mmc0: new high speed SDHC card at address aaaa + [ 4.108925] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed + [ 4.125119] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> idle + [ 4.125371] mmcblk0: mmc0:aaaa SD32G 29.7 GiB + [ 4.135208] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init + [ 4.141038] mmcblk0: p1 p2 p3 + [ 4.150068] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init + [ 4.164106] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported + [ 4.175560] hmc7044 spi1.0: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode + [ 4.209452] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup + [ 4.233255] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 + [ 4.245015] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 + [ 4.256858] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 + [ 4.268700] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage4 + [ 4.282555] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage4 -> link_setup + [ 4.293963] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 + [ 4.305464] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 + [ 4.317486] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 + [ 4.329507] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 + [ 4.341518] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 + [ 4.353531] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable + [ 4.366156] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable + [ 4.383462] ad9172 spi1.1: Link0 code_grp_sync: f + [ 4.388175] ad9172 spi1.1: Link0 frame_sync_stat: f + [ 4.393063] ad9172 spi1.1: Link0 good_checksum_stat: f + [ 4.398207] ad9172 spi1.1: Link0 init_lane_sync_stat: f + [ 4.403432] ad9172 spi1.1: Link0 4 lanes @ 7372800 kbps + [ 4.408718] ad9172 spi1.1: Link0 invalid dyn. link latency: 0xc + [ 4.414642] ad9172 spi1.1: Failed JESD204 link status (-22) + [ 4.420225] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] In link_running got error from cb: -22 + [ 4.431460] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -22 + [ 4.442271] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running + [ 4.454395] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> link_enable + [ 4.465650] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> clocks_enable + [ 4.476987] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> opt_setup_stage5 + [ 4.488753] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> opt_setup_stage4 + [ 4.500783] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage3 + [ 4.512823] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage2 + [ 4.524857] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage1 + [ 4.536891] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> link_setup + [ 4.548402] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> clk_sync_stage4 + [ 4.559824] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage4 -> clk_sync_stage3 + [ 4.571682] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage2 + [ 4.583538] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage1 + [ 4.595395] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> link_pre_setup + [ 4.607165] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> link_supported + [ 4.618852] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_init + [ 4.630103] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> device_init + [ 4.641094] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> idle + [ 4.651628] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> initialized + [ 4.662163] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition initialized -> probed + [ 4.672874] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition probed -> idle + [ 4.682978] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition idle -> device_init + [ 4.693520] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition device_init -> link_init + [ 4.704490] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_init -> link_supported + [ 4.715816] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_supported -> link_pre_setup + [ 4.739621] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 + [ 4.751384] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 + [ 4.763230] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 + [ 4.775064] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage3 -> clk_sync_stage4 + [ 4.788919] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clk_sync_stage4 -> link_setup + [ 4.800322] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_setup -> opt_setup_stage1 + [ 4.811823] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 + [ 4.823845] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 + [ 4.835864] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 + [ 4.847879] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 + [ 4.859900] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable + [ 4.872521] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition clocks_enable -> link_enable + [ 4.891581] ad9172 spi1.1: Link0 code_grp_sync: f + [ 4.896294] ad9172 spi1.1: Link0 frame_sync_stat: f + [ 4.901182] ad9172 spi1.1: Link0 good_checksum_stat: f + [ 4.906325] ad9172 spi1.1: Link0 init_lane_sync_stat: f + [ 4.911551] ad9172 spi1.1: Link0 4 lanes @ 7372800 kbps + [ 4.916837] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_enable -> link_running + [ 4.928074] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition link_running -> opt_post_setup_stage1 + [ 4.940181] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_post_setup_stage1 -> opt_post_setup_stage2 + [ 4.953068] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_post_setup_stage2 -> opt_post_setup_stage3 + [ 4.966711] jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] transition opt_post_setup_stage3 -> opt_post_running_stage + [ 4.979690] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a). Encoder 8b10b, width 4/4, lanes 4, jesd204-fsm. + [ 4.991460] nwl-pcie fd0e0000.pcie: host bridge /axi/pcie@fd0e0000 ranges: + [ 4.998372] nwl-pcie fd0e0000.pcie: MEM 0x00e0000000..0x00efffffff -> 0x00e0000000 + [ 5.006398] nwl-pcie fd0e0000.pcie: MEM 0x0600000000..0x07ffffffff -> 0x0600000000 + [ 5.014560] nwl-pcie fd0e0000.pcie: Link is DOWN + [ 5.019663] nwl-pcie fd0e0000.pcie: PCI host bridge to bus 0000:00 + [ 5.025858] pci_bus 0000:00: root bus resource [bus 00-ff] + [ 5.031362] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff] + [ 5.038246] pci_bus 0000:00: root bus resource [mem 0x600000000-0x7ffffffff pref] + [ 5.045774] pci 0000:00:00.0: [10ee:d021] type 01 class 0x060400 PCIe Root Port + [ 5.053110] pci 0000:00:00.0: PCI bridge to [bus 00] + [ 5.058085] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff] + [ 5.064885] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref] + [ 5.072686] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot + [ 5.080888] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring + [ 5.089027] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 + [ 5.095665] pci 0000:00:00.0: PCI bridge to [bus 01] + [ 5.100644] pci_bus 0000:00: resource 4 [mem 0xe0000000-0xefffffff] + [ 5.106918] pci_bus 0000:00: resource 5 [mem 0x600000000-0x7ffffffff pref] + [ 5.114098] ahci-ceva fd0c0000.ahci: supply ahci not found, using dummy regulator + [ 5.121681] ahci-ceva fd0c0000.ahci: supply phy not found, using dummy regulator + [ 5.129177] ahci-ceva fd0c0000.ahci: supply target not found, using dummy regulator + [ 5.137081] ahci-ceva fd0c0000.ahci: AHCI vers 0001.0301, 32 command slots, 6 Gbps, platform mode + [ 5.145979] ahci-ceva fd0c0000.ahci: 2/2 ports implemented (port mask 0x3) + [ 5.152859] ahci-ceva fd0c0000.ahci: flags: 64bit ncq sntf pm clo only pmp fbs pio slum part ccc sds apst + [ 5.163487] scsi host0: ahci-ceva + [ 5.167139] scsi host1: ahci-ceva + [ 5.170567] ata1: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x100 irq 49 lpm-pol 0 + [ 5.179365] ata2: SATA max UDMA/133 mmio [mem 0xfd0c0000-0xfd0c1fff] port 0x180 irq 49 lpm-pol 0 + [ 5.192272] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 37 (00:0a:35:07:fe:31) + [ 5.219989] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller + [ 5.225509] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1 + [ 5.233289] xhci-hcd xhci-hcd.1.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x0000808002000810 + [ 5.242733] xhci-hcd xhci-hcd.1.auto: irq 50, io mem 0xfe200000 + [ 5.248768] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller + [ 5.254263] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2 + [ 5.261934] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed + [ 5.268607] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.12 + [ 5.276888] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 + [ 5.284127] usb usb1: Product: xHCI Host Controller + [ 5.289010] usb usb1: Manufacturer: Linux 6.12.77-ge2f9fe8e3654 xhci-hcd + [ 5.295716] usb usb1: SerialNumber: xhci-hcd.1.auto + [ 5.300982] hub 1-0:1.0: USB hub found + [ 5.304768] hub 1-0:1.0: 1 port detected + [ 5.309050] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 6.12 + [ 5.317322] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 + [ 5.324554] usb usb2: Product: xHCI Host Controller + [ 5.329434] usb usb2: Manufacturer: Linux 6.12.77-ge2f9fe8e3654 xhci-hcd + [ 5.336143] usb usb2: SerialNumber: xhci-hcd.1.auto + [ 5.341318] hub 2-0:1.0: USB hub found + [ 5.345097] hub 2-0:1.0: 1 port detected + [ 5.355588] input: gpio-keys as /devices/platform/gpio-keys/input/input0 + [ 5.362652] of_cfs_init + [ 5.365124] of_cfs_init: OK + [ 5.368000] cfg80211: Loading compiled-in X.509 certificates for regulatory database + [ 5.413680] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' + [ 5.420131] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600' + [ 5.427394] clk: Not disabling unused clocks + [ 5.431667] PM: genpd: Disabling unused power domains + [ 5.437068] ALSA device list: + [ 5.440034] No soundcards found. + [ 5.443793] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 + [ 5.452422] cfg80211: failed to load regulatory.db + [ 5.501381] ata2: SATA link down (SStatus 0 SControl 330) + [ 5.506816] ata1: SATA link down (SStatus 0 SControl 330) + [ 5.680139] EXT4-fs (mmcblk0p2): mounted filesystem 9effbc73-dcc3-4a5e-81e8-572f95b9fe33 r/w with ordered data mode. Quota mode: none. + [ 5.692320] VFS: Mounted root (ext4 filesystem) on device 179:2. + [ 5.698936] devtmpfs: mounted + [ 5.702834] Freeing unused kernel memory: 3584K + [ 5.707460] Run /sbin/init as init process + [ 6.365869] systemd[1]: Failed to find module 'autofs4' + [ 6.439184] systemd[1]: systemd 257.9-1~deb13u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +IPE +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBCRYPTSETUP_PLUGINS +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD +BPF_FRAMEWORK +BTF -XKBCOMMON -UTMP +SYSVINIT +LIBARCHIVE) + [ 6.473469] systemd[1]: Detected architecture arm64. + + Welcome to Debian GNU/Linux 13 (trixie)! + + [ 6.515889] systemd[1]: Hostname set to . + [ 6.622600] systemd[1]: bpf-restrict-fs: BPF LSM hook not enabled in the kernel, BPF LSM not supported. + [ 8.125803] systemd[1]: /usr/lib/systemd/system/iiod.service:16: Invalid environment assignment, ignoring: $IIOD_EXTRA_OPTS= + [ 8.375745] systemd[1]: Queued start job for default target graphical.target. + [ 8.388794] systemd[1]: Created slice system-getty.slice - Slice /system/getty. + [ OK ] Created slice system-getty.slice - Slice /system/getty. + [ 8.408147] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe. + [ OK ] Created slice system-modprobe.slice - Slice /system/modprobe. + [ 8.428092] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty. + [ OK ] Created slice system-serial\x2dget…slice - Slice /system/serial-getty. + [ 8.448043] systemd[1]: Created slice system-systemd\x2dfsck.slice - Slice /system/systemd-fsck. + [ OK ] Created slice system-systemd\x2dfs…slice - Slice /system/systemd-fsck. + [ 8.467564] systemd[1]: Created slice user.slice - User and Session Slice. + [ OK ] Created slice user.slice - User and Session Slice. + [ 8.487373] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch. + [ OK ] Started systemd-ask-password-wall.…d Requests to Wall Directory Watch. + [ 8.511338] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc). + [ 8.530726] systemd[1]: Expecting device dev-disk-by\x2dpartuuid-3aa3f66d\x2d01.device - /dev/disk/by-partuuid/3aa3f66d-01... + Expecting device dev-disk-by\x2dpa…dev/disk/by-partuuid/3aa3f66d-01... + [ 8.555173] systemd[1]: Expecting device dev-ttyGS0.device - /dev/ttyGS0... + Expecting device dev-ttyGS0.device - /dev/ttyGS0... + [ 8.575175] systemd[1]: Expecting device dev-ttyGS1.device - /dev/ttyGS1... + Expecting device dev-ttyGS1.device - /dev/ttyGS1... + [ 8.595157] systemd[1]: Expecting device dev-ttyPS0.device - /dev/ttyPS0... + Expecting device dev-ttyPS0.device - /dev/ttyPS0... + [ 8.615163] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0... + Expecting device dev-ttyS0.device - /dev/ttyS0... + [ 8.635316] systemd[1]: Reached target nss-user-lookup.target - User and Group Name Lookups. + [ OK ] Reached target nss-user-lookup.target - User and Group Name Lookups. + [ 8.655210] systemd[1]: Reached target remote-fs.target - Remote File Systems. + [ OK ] Reached target remote-fs.target - Remote File Systems. + [ 8.675200] systemd[1]: Reached target slices.target - Slice Units. + [ OK ] Reached target slices.target - Slice Units. + [ 8.695236] systemd[1]: Reached target swap.target - Swaps. + [ OK ] Reached target swap.target - Swaps. + [ 8.715563] systemd[1]: Listening on systemd-creds.socket - Credential Encryption/Decryption. + [ OK ] Listening on systemd-creds.socket - Credential Encryption/Decryption. + [ 8.735455] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe. + [ OK ] Listening on systemd-initctl.socke…- initctl Compatibility Named Pipe. + [ 8.755466] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log). + [ OK ] Listening on systemd-journald-dev-…socket - Journal Socket (/dev/log). + [ 8.775484] systemd[1]: Listening on systemd-journald.socket - Journal Sockets. + [ OK ] Listening on systemd-journald.socket - Journal Sockets. + [ 8.795289] systemd[1]: systemd-pcrextend.socket - TPM PCR Measurements was skipped because of an unmet condition check (ConditionSecurity=measured-uki). + [ 8.809120] systemd[1]: systemd-pcrlock.socket - Make TPM PCR Policy was skipped because of an unmet condition check (ConditionSecurity=measured-uki). + [ 8.822952] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket. + [ OK ] Listening on systemd-udevd-control.socket - udev Control Socket. + [ 8.843356] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket. + [ OK ] Listening on systemd-udevd-kernel.socket - udev Kernel Socket. + [ 8.866211] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System... + Mounting dev-hugepages.mount - Huge Pages File System... + [ 8.889510] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System... + Mounting dev-mqueue.mount - POSIX Message Queue File System... + [ 8.913755] systemd[1]: Mounting run-lock.mount - Legacy Locks Directory /run/lock... + Mounting run-lock.mount - Legacy Locks Directory /run/lock... + [ 8.940066] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System... + Mounting sys-kernel-debug.mount - Kernel Debug File System... + [ 8.963647] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing). + [ 8.981774] systemd[1]: Mounting tmp.mount - Temporary Directory /tmp... + Mounting tmp.mount - Temporary Directory /tmp... + [ 9.002240] systemd[1]: Starting fake-hwclock-load.service - Restore the current clock... + Starting fake-hwclock-load.service - Restor[ 9.011340] systemd[1]: kmod-static-nodes.service - Create List of Static Device Nodes was skipped because of an unmet condition check (ConditionFileNotEmpty=/lib/modules/6.12.77-ge2f9fe8e3654/modules.devname). + e the current clock... + [ 9.038101] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs... + Starting modprobe@configfs.service - Load Kernel Module configfs... + [ 9.085996] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm... + Starting modprobe@drm.service - Load Kernel Module drm... + [ 9.113217] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore... + Starting modprobe@efi_pstore.servi… - Load Kernel Module efi_pstore... + [ 9.141974] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse... + Starting modprobe@fuse.service - Load Kernel Module fuse... + [ 9.167758] systemd[1]: systemd-hibernate-clear.service - Clear Stale Hibernate Storage Info was skipped because of an unmet condition check (ConditionPathExists=/sys/firmware/efi/efivars/HibernateLocation-8cf2644b-4b0b-428f-9387-6d876050dc67). + [ 9.190628] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling. + [ 9.203525] systemd[1]: systemd-journald.service: (This warning is only shown for the first unit using IP firewalling.) + [ 9.216439] systemd[1]: Starting systemd-journald.service - Journal Service... + Starting systemd-journald.service - Journal Service... + [ 9.239147] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules... + Starting systemd-modules-load.service - Load Kernel Modules... + [ 9.259359] systemd[1]: systemd-pcrmachine.service - TPM PCR Machine ID Measurement was skipped because of an unmet condition check (ConditionSecurity=measured-uki). + [ 9.300582] systemd[1]: Starting systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully... + Starting systemd-tmpfiles-setup-de… Device Nodes in /dev gracefully... + [ 9.327321] systemd[1]: systemd-tpm2-setup-early.service - Early TPM SRK Setup was skipped because of an unmet condition check (ConditionSecurity=measured-uki). + [ 9.344560] systemd[1]: Starting systemd-udev-load-credentials.service - Load udev Rules from Credentials... + Starting systemd-udev-load-credent…Load udev Rules from Credentials... + [ 9.375609] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices... + Starting systemd-udev-trigger.service - Coldplug All udev Devices... + [ 9.394460] systemd-journald[195]: Collecting audit messages is disabled. + [ 9.409749] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System. + [ OK ] Mounted dev-hugepages.mount - Huge Pages File System. + [ 9.429288] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System. + [ OK ] Mounted dev-mqueue.mount - POSIX Message Queue File System. + [ 9.451768] systemd[1]: Mounted run-lock.mount - Legacy Locks Directory /run/lock. + [ OK ] Mounted run-lock.mount - Legacy Locks Directory /run/lock. + [ 9.475677] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System. + [ OK ] Mounted sys-kernel-debug.mount - Kernel Debug File System. + [ 9.499862] systemd[1]: Mounted tmp.mount - Temporary Directory /tmp. + [ OK ] Mounted tmp.mount - Temporary Directory /tmp. + [ 9.524024] systemd[1]: fake-hwclock-load.service: Deactivated successfully. + [ 9.531516] systemd[1]: Finished fake-hwclock-load.service - Restore the current clock. + [ OK ] Finished fake-hwclock-load.service - Restore the current clock. + [ 9.556343] systemd[1]: modprobe@configfs.service: Deactivated successfully. + [ 9.563936] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs. + [ OK ] Finished modprobe@configfs.service - Load Kernel Module configfs. + [ 9.588184] systemd[1]: modprobe@drm.service: Deactivated successfully. + [ 9.595317] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm. + [ OK ] Finished modprobe@drm.service - Load Kernel Module drm. + [ 9.619868] systemd[1]: Started systemd-journald.service - Journal Service. + [ OK ] Started systemd-journald.service - Journal Service. + [ OK ] Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore. + [ OK ] Finished modprobe@fuse.service - Load Kernel Module fuse. + [ OK ] Finished systemd-modules-load.service - Load Kernel Modules. + [ OK ] Finished systemd-tmpfiles-setup-de…ic Device Nodes in /dev gracefully. + [ OK ] Finished systemd-udev-load-credent…- Load udev Rules from Credentials. + Mounting sys-fs-fuse-connections.mount - FUSE Control File System... + Mounting sys-kernel-config.mount - Kernel Configuration File System... + Starting systemd-remount-fs.servic…unt Root and Kernel File Systems... + Starting systemd-sysctl.service - Apply Kernel Variables... + [ OK ] Mounted sys-fs-fuse-connections.mount - FUSE Control File System. + [ OK ] Mounted sys-kernel-config.mount - Kernel Configuration File System. + [ OK ] Finished systemd-sysctl.service - Apply Kernel Variables. + [ OK ] Finished systemd-remount-fs.servic…mount Root and Kernel File Systems. + Starting systemd-journal-flush.ser…sh Journal to Persistent Storage... + Starting systemd-random-seed.service - Load/Save OS Random Seed... + Starting systemd-tmpfiles-setup-de…eate Static Device Nodes in /dev... + [ OK ] Finished systemd-tmpfiles-setup-de…Create Static Device Nodes in /dev. + [ OK ] Reached target local-fs-pre.target…Preparation for Local File Systems. + Starting systemd-udevd.service - R…ager for Device Events and Files... + [ OK ] Finished systemd-udev-trigger.service - Coldplug All udev Devices. + Starting ifupdown-pre.service - He…synchronize boot up for ifupdown... + Starting systemd-udev-settle.servi…o Complete Device Initialization... + [ OK ] Finished systemd-journal-flush.ser…lush Journal to Persistent Storage. + [ OK ] Finished systemd-random-seed.service - Load/Save OS Random Seed. + [ OK ] Finished ifupdown-pre.service - He…o synchronize boot up for ifupdown. + [ OK ] Started systemd-udevd.service - Ru…anager for Device Events and Files. + Starting plymouth-start.service - Show Plymouth Boot Screen... + [ OK ] Found device dev-ttyPS0.device - /dev/ttyPS0. + mtdoops: mtd device (mtddev=name/number) must be supplied + [ OK ] Started plymouth-start.service - Show Plymouth Boot Screen. + ad7291 14-002f: probe with driver ad7291 failed with error -5 + ad9172 spi1.1: Link0 invalid dyn. link latency: 0xc + ad9172 spi1.1: Failed JESD204 link status (-22) + jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: JESD204[0:0] In link_running got error from cb: -22 + jesd204: /axi/spi@ff040000/ad9172@1,jesd204:1,parent=spi1.1: Rolling back from 'link_enable', got error -22 + systemd[1]: Failed to find module 'autofs4' + [ OK ] Found device dev-disk-by\x2dpartuu… /dev/disk/by-partuuid/3aa3f66d-01. + [ OK ] Finished systemd-udev-settle.servi… To Complete Device Initialization. + [ OK ] Started systemd-ask-password-plymo…quests to Plymouth Directory Watch. + [ OK ] Reached target paths.target - Path Units. + [ OK ] Listening on systemd-rfkill.socket…ll Switch Status /dev/rfkill Watch. + Starting systemd-fsck@dev-disk-by\…dev/disk/by-partuuid/3aa3f66d-01... + [ OK ] Finished systemd-fsck@dev-disk-by\… /dev/disk/by-partuuid/3aa3f66d-01. + Mounting boot.mount - /boot... + [ OK ] Mounted boot.mount - /boot. + [ OK ] Reached target local-fs.target - Local File Systems. + [ OK ] Listening on systemd-sysext.socket… System Extension Image Management. + Starting networking.service - Raise network interfaces... + Starting plymouth-read-write.servi…ymouth To Write Out Runtime Data... + Starting systemd-tmpfiles-setup.se…ate System Files and Directories... + [ OK ] Finished plymouth-read-write.servi…Plymouth To Write Out Runtime Data. + [ OK ] Finished systemd-tmpfiles-setup.se…reate System Files and Directories. + [ OK ] Reached target sysinit.target - System Initialization. + [ OK ] Started apt-daily.timer - Daily apt download activities. + [ OK ] Started apt-daily-upgrade.timer - …y apt upgrade and clean activities. + [ OK ] Started dpkg-db-backup.timer - Daily dpkg database backup timer. + [ OK ] Started e2scrub_all.timer - Period…Metadata Check for All Filesystems. + [ OK ] Started fake-hwclock-save.timer - Periodically save current clock. + [ OK ] Started fstrim.timer - Discard unused filesystem blocks once a week. + [ OK ] Started logrotate.timer - Daily rotation of log files. + [ OK ] Started man-db.timer - Daily man-db regeneration. + [ OK ] Started ntpsec-rotate-stats.timer - Rotate ntpd stats daily. + [ OK ] Started systemd-tmpfiles-clean.tim…y Cleanup of Temporary Directories. + [ OK ] Reached target timers.target - Timer Units. + [ OK ] Listening on avahi-daemon.socket -…DNS/DNS-SD Stack Activation Socket. + [ OK ] Listening on dbus.socket - D-Bus System Message Bus Socket. + [ OK ] Listening on sshd-unix-local.socke…temd-ssh-generator, AF_UNIX Local). + [ OK ] Listening on systemd-hostnamed.socket - Hostname Service Socket. + [ OK ] Reached target sockets.target - Socket Units. + [ OK ] Reached target basic.target - Basic System. + Starting accounts-daemon.service - Accounts Service... + Starting adi-power.service - Analog Devices power up/down sequence... + Starting avahi-daemon.service - Avahi mDNS/DNS-SD Stack... + Starting blueman-mechanism.service - Bluetooth management mechanism... + [ OK ] Started cron.service - Regular background program processing daemon. + Starting dbus.service - D-Bus System Message Bus... + Starting e2scrub_reap.service - Re…ne ext4 Metadata Check Snapshots... + [ OK ] Started fan-control.service - fan-control. + Starting fix-display-port.service - Fix DP audio and X11... + Starting iiod_context_attr.service…ating IIOD Context Attributes...... + Starting systemd-logind.service - User Login Management... + Starting udisks2.service - Disk Manager... + Starting xserver.service - ADI X Server... + [ OK ] Finished networking.service - Raise network interfaces. + [ OK ] Started systemd-logind.service - User Login Management. + [ OK ] Finished fix-display-port.service - Fix DP audio and X11. + [ OK ] Started dbus.service - D-Bus System Message Bus. + Starting NetworkManager.service - Network Manager... + Starting wpa_supplicant.service - WPA supplicant... + [ OK ] Started avahi-daemon.service - Avahi mDNS/DNS-SD Stack. + Starting polkit.service - Authorization Manager... + [ OK ] Created slice user-1000.slice - User Slice of UID 1000. + Starting user-runtime-dir@1000.ser…Runtime Directory /run/user/1000... + [ OK ] Finished user-runtime-dir@1000.ser…r Runtime Directory /run/user/1000. + [ OK ] Started wpa_supplicant.service - WPA supplicant. + [ OK ] Finished adi-power.service - Analog Devices power up/down sequence. + [ OK ] Started polkit.service - Authorization Manager. + [ OK ] Started accounts-daemon.service - Accounts Service. + [ OK ] Finished iiod_context_attr.service…reating IIOD Context Attributes.... + Starting systemd-hostnamed.service - Hostname Service... + [ OK ] Finished e2scrub_reap.service - Re…line ext4 Metadata Check Snapshots. + [ OK ] Started udisks2.service - Disk Manager. + [ OK ] Started systemd-hostnamed.service - Hostname Service. + Starting NetworkManager-dispatcher…anager Script Dispatcher Service... + [ OK ] Started NetworkManager.service - Network Manager. + [ OK ] Reached target network.target - Network. + Starting htpdate.service - HTTP based time synchronization tool... + [ OK ] Started iiod.service - IIO Daemon. + Starting ntpsec.service - Network Time Service... + Starting ssh.service - OpenBSD Secure Shell server... + Starting systemd-user-sessions.service - Permit User Sessions... + [ OK ] Started udiskie.service - Udiskie …rvice for managing removable media. + [ OK ] Started NetworkManager-dispatcher.… Manager Script Dispatcher Service. + [ OK ] Started htpdate.service - HTTP based time synchronization tool. + [ OK ] Finished systemd-user-sessions.service - Permit User Sessions. + Starting plymouth-quit-wait.servic…d until boot process finishes up... + Starting user@1000.service - User Manager for UID 1000... + [ OK ] Started ntpsec.service - Network Time Service. + [ OK ] Started ssh.service - OpenBSD Secure Shell server. + [ OK ] Started blueman-mechanism.service - Bluetooth management mechanism. + [ OK ] Started user@1000.service - User Manager for UID 1000. + [ OK ] Started session-c1.scope - Session c1 of User analog. + [ OK ] Finished xserver.service - ADI X Server. + Starting lightdm.service - Light Display Manager... + Starting x11vnc.service - VNC Server for X11... + [FAILED] Failed to start x11vnc.service - VNC Server for X11. + + Debian GNU/Linux 13 analog ttyPS0 + + analog login: root (automatic login) + + Linux analog 6.12.77-ge2f9fe8e3654 #1 SMP Thu Mar 26 12:20:17 UTC 2026 aarch64 + + The programs included with the Debian GNU/Linux system are free software; + the exact distribution terms for each program are described in the + individual files in /usr/share/doc/*/copyright. + + Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent + permitted by applicable law. + root@analog:~# + +Useful commands for the serial terminal +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The below commands are to be run in the serial terminal connected to the FPGA. + +To find out the IP of the FPGA board, run the following command and take the +IP specified at "eth0 inet": + +.. shell:: + + $ifconfig + +To see the IIO devices detected, run: + +.. shell:: + + $iio_info | grep iio:device + root@analog:~# iio_info | grep iio:device + iio:device0: xadc + iio:device1: hmc7044 + iio:device2: axi-ad9172-hpc (buffer capable) + +To use the :dokuwiki:`JESD204 status utility `, +run: + +.. shell:: + + $jesd_status + (DEVICES) Found 1 JESD204 Link Layer peripherals + + (0): axi-jesd204-tx/44a90000.axi-jesd204-tx [*] + + (STATUS) + Link is enabled + Link Status DATA + Measured Link Clock (MHz) 184.325 + Reported Link Clock (MHz) 184.320 + Measured Device Clock (MHz) 184.325 + Reported Device Clock (MHz) 184.320 + Desired Device Clock (MHz) 184.320 + Lane rate (MHz) 7372.800 + Lane rate / 40 (MHz) 184.320 + LMFC rate (MHz) 11.520 + SYSREF captured Yes + SYSREF alignment error No + SYNC~ deasserted + + You can also use 'q' to quit and 'a' or 'd' to move between devices! + F1axi-jesd204-tx/44a90000.axi-jesd204-txF9Quit + +To power off the system, run the following command, and wait for the final +message to be printed, then power off the FPGA board from the switch as well. + +.. shell:: + + $poweroff + +To reboot the system, run: + +.. shell:: + + $reboot + +.. important:: + + Even though this is Linux, this is a persistent file system. Care should + be taken not to corrupt the file system -- please shut down things, don't + just turn off the power switch. Depending on your monitor, the standard + power off could be hiding. You can do this from the terminal as well with + :code:`sudo shutdown -h now` or the above-mentioned command for powering + off. + +Scopy +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. important:: + + Make sure to download/update to the latest version of + :external+scopy:doc:`Scopy `. + +:external+scopy:doc:`Scopy ` can be used to connect remotetly to the +setup and control it. Configure the DAC plugin with the desired waveform and +frequency. + +In the below example the :adi:`EVAL-AD9172 ` had no external clock +generator connected to it, the DAC0 pin was connected to a spectrum +analyzer using a SMA cable: + +- Connect to the setup (DAC plugin) using setup's IP address + + .. image:: ../images/scopy_1_ad9172_zcu102.png + :width: 800 + +- Chose the waveform + + .. image:: ../images/scopy_2_ad9172_zcu102.png + :width: 800 + +- Visualising the waveform using an exterenal spectrum analyzer + + .. image:: ../images/scopy_spectrum_analyzer_ad9172_zcu102.jpg + :width: 800 + +IIO Oscilloscope +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. important:: + + Make sure to download/update to the latest version of + :git-iio-oscilloscope:`IIO Oscilloscope `. + +Once done with the installation or an update of the latest IIO Oscilloscope, +open the application. The user needs to supply a URI which will be used in the +context creation of the IIO Oscilloscope. + +In the below example the :adi:`EVAL-AD9172 ` had no external clock +generator connected to it, the DAC0 pin was connected to a spectrum +analyzer using a SMA cable: + +- Press ``Refresh`` to display available IIO Devices and press ``Connect``. + + .. image:: ../images/iio_osc_1_ad9172_zcu102.png + :width: 800 + +- After the board is connected, you can set the device to output a waveform + + .. image:: ../images/iio_osc_2_ad9172_zcu102.png + :width: 800 + +- Visualising the waveform using an exterenal spectrum analyzer + + .. image:: ../images/iio_osc_spectrum_analyzer_ad9172_zcu102.jpg + :width: 800 + +Using no-OS as software +------------------------------------------------------------------------------- + +Necessary files +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The following files are needed for the system to boot: + +- HDL boot file: ``system_top.xsa`` +- no-OS project: :git-no-os:`projects/ad9172` + +Instructions on how to build the boot files from source can be found here: + +- :external+no-OS:doc:`projects/dac/ad9172` - no-OS project documentation +- :external+hdl:ref:`dac_fmc_ebz`. More HDL build details at + :external+hdl:ref:`build_hdl`. + +Required Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx Vivado and Vitis (downloading Vitis from + `here `_ + will include Vivado as well) +- An UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1) + +Required Hardware +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- AMD Xilinx :xilinx:`ZCU102` Rev 1.0 FPGA board and its power supply +- :adi:`EVAL-AD9172 ` FMC evaluation board +- 2x Micro-USB cables, one for UART and one for JTAG +- (Optional) USB keyboard & mouse and a HDMI-compatible monitor + +More details as to why you need these, can be found at +:ref:`dac-fmc-ebz prerequisites`. + +Testing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Creating the setup +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: ../images/ad9172_zcu102_noos.jpg + :width: 800 + +Follow the steps in this order, to avoid damaging the components: + +#. Connect the :adi:`EVAL-AD9172 ` FMC board to the ZCU102 + **HPC0** FMC socket +#. Configure :xilinx:`ZCU102` for JTAG boot mode (mode SW6[4:1] switch in + the position **ON,ON,ON,ON**) +#. Connect USB UART J83 (Micro USB) to your host PC +#. Connect USB JTAG (Micro USB) to your host PC +#. (Optional) Connect a monitor to the FPGA by HDMI, and a mouse and a keyboard +#. Turn on the power switch on the FPGA board +#. Observe console output messages on your terminal (use the first ttyUSB or + COM port registered) + +Boot messages +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The following is what is printed in the serial console, after you have +connected to the proper ttyUSB or COM port: + +.. collapsible:: Complete boot log + + :: + + Zynq MP First Stage Boot Loader + Release 2023.2 Apr 16 2026 - 12:10:38 + PMU-FW is not running, certain applications may not be supported. + WARNING: Read/Write check failed (0x0) + Probed, SPI read support failed + Using JESD FSM + ad917x DAC Chip ID: 4 + ad917x DAC Product ID: 9172 + ad917x DAC Product Grade: 0 + ad917x DAC Product Revision: 2 + ad917x Revision: 1.1.1 + CLK Input rate 368640000 + PLL lock status 1, DLL lock status: 1 + Serdes PLL Locked (stat: 3) + ad9172_init : AD917x Rev 1 successfully initialized + WARNING: hmc7044_jesd204_link_pre_setup: Link0 forcing continuous SYSREF mode + tx_adxcvr: OK (7372800 kHz) + Link0 code_grp_sync: f + Link0 frame_sync_stat: f + Link0 good_checksum_stat: f + Link0 init_lane_sync_stat: f + Link0 4 lanes @ 7372800 kBps + tx_dac: Successfully initialized (368640136 Hz) + tx_jesd status: + Link is enabled + Measured Link Clock: 184.320 MHz + Reported Link Clock: 184.320 MHz + Lane rate: 7372.800 MHz + Lane rate / 40: 184.320 MHz + LMFC rate: 11.520 MHz + SYNC~: deasserted + Link status: DATA + SYSREF captured: Yes + SYSREF alignment error: No + Set dds frequency at 40 MHz + Bye \ No newline at end of file diff --git a/docs/solutions/reference-designs/dac-fmc-ebz/resources/ad9135-fmc-ebz_revb_bom_customer.xlsx b/docs/solutions/reference-designs/dac-fmc-ebz/resources/ad9135-fmc-ebz_revb_bom_customer.xlsx new file mode 100644 index 00000000000..ef215d882fe --- /dev/null +++ b/docs/solutions/reference-designs/dac-fmc-ebz/resources/ad9135-fmc-ebz_revb_bom_customer.xlsx @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid 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through the DPG3 connector (P4). +- **Via FMC connector** -- when using an ADS7-V2 or FPGA carrier board, power + is supplied through the FMC connector (+12V, +3.3V, VADJ). + +TBA -- Power supply details per board variant + +Clock Configuration +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +All DAC-FMC-EBZ boards include an AD9516 clock distribution chip that provides: + +- DACCLK -- the main DAC sampling clock +- REFCLK / SYSREF -- JESD204B reference and synchronization clocks +- DPG3/ADS7 interface clock + +A low phase noise external clock source should be connected to the SMA +connector J1 (CLK_IN). + +TBA -- Clock configuration details per board variant + +Schematic, PCB Layout, and BOM +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Design files for each board variant are available in the respective evaluation +board pages: + +- :doc:`AD9136 & AD9135 Evaluation Boards ` +- :doc:`AD9144 Evaluation Boards ` +- :doc:`AD9152 Evaluation Board ` +- :doc:`AD9154 Evaluation Boards ` +- :doc:`AD917x Evaluation Board ` + +Software Guide +------------------------------------------------------------------------------- + +ACE Software +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The preferred evaluation software is +:dokuwiki:`ACE (Analysis | Control | Evaluation) `. +ACE provides a graphical interface for configuring the DAC and clock +distribution chip via SPI, and is used in conjunction with the DPG Downloader +for waveform generation. + +TBA -- ACE software usage overview + +DPG Downloader +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The :dokuwiki:`DPG Downloader ` is used +to generate and download test waveforms (single tone, multi-carrier, custom +vectors) into the DPG3 or ADS7 pattern generator. + +TBA -- DPG Downloader usage overview + +Linux Driver Support +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For FPGA-based evaluation using Linux, the following drivers are available: + +TBA -- Linux driver details, IIO devices, channel mapping