From b844772571cb90f1982f01ef5164eb5821dd3222 Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Fri, 17 Apr 2026 17:11:03 +0100 Subject: [PATCH 1/6] HTML removed. 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+51,6 @@ System-level control via Python, MATLAB, or QIQ using libIIO APIs. ## Platforms -```{toctree} -:maxdepth: 1 -:hidden: - -Phaser (CN0566) -Pluto SDR -``` - For more information on each of ADC Platforms, please click on the links below: @@ -84,6 +76,15 @@ Low-cost SDR system based on the AD9361 ```` ````` +````{card} Triton +:ref: adc triton + +16T/16R X-Band System Platform + +```{image} resources/ADXBAND16EBZ_top-angle-evaluation-board.png +``` +```` + ## Platform Pilots ```{image} resources/pilot_ships.svg @@ -138,4 +139,13 @@ We have a Catalyst centres in: Co-develop system-level solutions with customers and ADI design teams. +```{toctree} +:maxdepth: 1 +:hidden: + +Phaser (CN0566) +Pluto SDR +Triton +``` + diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bysnc-1-3-alignment.png b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bysnc-1-3-alignment.png new file mode 100644 index 00000000000..c58ba6ca468 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bysnc-1-3-alignment.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7eb77c9c02b8d5553338c5e2c511736bd913c4bbc24bfa1d95cf34725a4c475b +size 207716 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-evb-connections.png b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-evb-connections.png new file mode 100644 index 00000000000..a5dcb38bbe8 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-evb-connections.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:a0b40ece58025ec3441292460c992f0b9b651204bea97c3ee837fc70afa735eb +size 2699615 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-evb-interposer-block-diagram.png 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sha256:d908c853721f1334aa9e3d4a242b3df94c76eee6e88d0916d5e34b5f9488fff0 +size 1553769 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md new file mode 100644 index 00000000000..974e9ee8b90 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md @@ -0,0 +1,98 @@ +# Aion EVB Initialisation + +This section provides guidance on how to successfully setup and initialise the Aion Evaluation Board and accompanying Interposer Board. We require the Aion Eval Board to provide the External BSYNC signals to each of the Triton Development Platforms. Triton is setup to operate at 26.4 Gbps JESD rate so this requires 12.5 MHz BSYNC frequency to be set (26.4 Gbps / 66 / 32x decimation = 12.5 MHz). + +## Hardware Requirements + +For a deep dive on the EVAL-ADF4030, we suggest you review the product home page, the link is shared at the bottom of this page. + +As shown in the picture below, we require five connections to the EVAL-ADF4030 & SDP-K1 control board and ADF4030 Interposer Board: +- On the SDP-K1: + - There is a USB-C connection which needs to be connected to the control PC + - This will allow the Python software to control the system + + +- On the EVAL-ADF4030, we will connect: + - 10MHz REF_CLK from the Signal Generator supplying the 400MHz to the Triton Platforms + (this can be the 10MHz_REF BNC from the rear of most signal generators) + - 12V DC Input using the supplied DC Adaptor with the evaluation kit + - BSYNC_1 will be connected to CLK_4 on the Interposer Board using the supplied Twinax cables with the evaluation kit + - BSYNC_3 will be connected to CLK_5 on the Interposer Board using the supplied Twinax cables with the evaluation kit + - To ensure the communication to the EVAL-ADF4030 is correct, ensure the dip switches are setup as shown in the image below + +**Aion Evaluation Board Connections:** +```{image} images/dual-triton-mcs-aion-evb-connections.png +:width: 700px +:align: center +``` + +**Aion Interposer Board Connections:** +```{image} images/dual-triton-mcs-aion-interposer-connections.png +:width: 700px +:align: center +``` + +**Aion EVB & Interposer Board Block Diagram:** +```{image} images/dual-triton-mcs-aion-evb-interposer-block-diagram.png +:width: 700px +:align: center +``` + +## Software Requirements + +At the time of writing, the software associated with this demo is not for general release and is therefore not on the public ADI PyIIO repo. + +The software to setup the Aion Eval Board, can be found at the following link [ADF4030 Python Eval Source](https://github.com/adi-innersource/bfg-py-scripts) + +The following are the steps to install the software correctly: + +- Create a directory on your control PC (assuming Windows), e.g. C:\ADF4030_Eval_Control + +- Using your preferred GIT control software, clone the repo from the link above using the following command: + - *git clone https://github.com/adi-innersource/bfg-py-scripts.git* + +- Using your preferred Python IDE, open the *bfg-py-scripts-main* folder: + - Navigate to *\iio_scripts\adf4030\delay* in a terminal + - Open the following script ahead of execution --> *adf4030_delay_test.py* + - There are a few edits needed ahead of execution: + - **Line 15:** The default Comm Port for the SDP-K1 board is COM8, you need to ensure this aligns with your Control PC by checking the Device Manager + - **Line 26:** The *ref_freq* should be changed from the default 125e6 to the required 10e6 (10 MHz) which we are supplying from the Signal Generator + - **Lines 32/33:** Both the *bsync_freq* parameters should be edited from the 100e6 default to the required 12.5e6 for this setup + - **Line 37:** The second channel to be configured should be Channel 3, not the default 2 + - **Line 41:** The *tdc_measurement* variable should be changed from the default 2 to 3, so we are measuring on the required BSYNC_3 channel + - **Line 47:** The channel to align should be changed from default 2 to the required 3 + - **Line 48:** The *single_ch_alignment* variable should be changed from default 2 to the required 3 + - **Line 50:** The *tdc_measurement* should be changed from the default 2 to the required 3 + - The Python software is now configured to align BSYNC_1 and BSYNC_3 outputs + +- Ahead of execution, there is a final modification that is needed to the SDP-K1 board, the firmware needs to be updated to support this mode. + - The firmware file, can be found in zip format in the *bfg-py-scripts\sdp-k1_bin* directory + - Unzip this file which will present *adf4030.bin* file + - Open a Windows Explorer window on the Control PC and you should see a SDP-K1 D: Drive present + - The *adf4030.bin* file should be dragged to this D: drive and this will update the firmware on the SDP-K1 board + - You can monitor the SDP-K1 board and observe a flashing Orange LED during the update process and then the board will reset + - Finally, you should press the reset button on the SDP-K1 board before moving to the next step + +## Python Code Execution + +- Now that the Python software is modified to align to our hardware configuration and the SDP-K1 firmware is updated, we are in a position to run the script + - In Python IDE terminal, run the following command: + *python -m iio_scripts.adf4030.delay.adf4030_delay_test* + - This will first measure the delay between BSYNC_1 and BSYNC_3 ports of the ADF4030 Evaluation Board and it will report the delay in fsec, highlighted in red below + - The user will then be prompted to press Enter to align these channels + - Once aligned, the updated and aligned delta will be printed on the console with a passing delay of less than 1000 fsec, as highlighted in green below + +**Aion BSYNC_1 and BSYNC_3 Alignment:** +```{image} images/dual-triton-mcs-aion-bsync-1-3-alignment.png +:width: 700px +:align: center +``` + +****The Aion EVB and Interposer Board is now configured as needed and you can move to the Triton Initialization steps**** + +## Additional Links + +- [Analog Devices Main Website](https://www.analog.com/) +- [ADI Wiki](https://wiki.analog.com/) +- [Engineering Zone Forums](https://ez.analog.com/) +- [ADF4030 EVAL Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-adf4030.html) diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-block-diagram.png b/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-block-diagram.png new file mode 100644 index 00000000000..56a4e0a5943 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-block-diagram.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:362633fe8ee85236dd2a703b0f926886b227365621116e670a8f893f383034ec +size 108355 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-pmod-connections.png b/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-pmod-connections.png new file mode 100644 index 00000000000..c24a5dd9b91 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/images/dual-triton-mcs-pmod-connections.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e3e7b4f3a96dbc3aba7e0d4f7eb9efbd0ed2c897dc88ff1b490a24b8b905e757 +size 805220 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/index.md new file mode 100644 index 00000000000..1b30b0a9130 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/index.md @@ -0,0 +1,60 @@ +# Dual Triton MultiChip Sync (MCS) Pilot Overview + +This section provides the steps required to setup the Dual Triton MCS Demo, which consists of two 16T/16R Triton Development Platforms and a [**Aion (ADF4030) Evaluation Board**](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-adf4030.html). The pilot demonstrates the usage of the Aion sync device to align the BSYNCs from the EVAL-ADF4030 and have these drive each Triton as external BSYNC inputs. The pilot then has the Leader Triton transmit a DAC signal and loop it back into one of its own ADCs and also send it to an ADC on the Follower Triton. The ADC data from both platforms are then post processed and the delay calculated to demonstrate accuracy of +/-5 picoseconds. + +## Block Diagram + +The figure below provides a high level block diagram of the required connections for the system as well as the PMOD connections required for triggering of the system. + +```{image} images/dual-triton-mcs-block-diagram.png +:width: 700px +:align: center +``` + +```{image} images/dual-triton-mcs-pmod-connections.png +:width: 700px +:align: center +``` + +## Hardware Requirements + +The following hardware is needed to successfully setup this pilot: +- 2 x [Triton Development Platforms](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) +- 1 x [Aion (ADF4030) Evaluation Platform + Interposer Board](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-adf4030.html) +- 2 x [Xilinx/AMD VCU118 FPGA Board](https://www.amd.com/en/products/adaptive-socs-and-fpgas/evaluation-boards/vcu118.html) +- 1 x RF Signal Generator supporting up to 400MHz as a reference frequency for each Triton +- 1 x RF Power Splitter to distribute the 400MHz to each Triton [2-Way Power Splitter 0.5 - 600MHz (Mini-Circuits)](https://www.minicircuits.com/WebStore/dashboard.html?model=Z99SC-62-S%2B) +- 1 x RF Power Splitter to distribute the DAC Transmission at X-Band to the Leader & Follower ADC's [4-Way Power Splitter 500 - 26500 MHz (Mini-Circuits)](https://www.minicircuits.com/WebStore/dashboard.html?model=ZC4PD-5R263-S%2B) + +## Software Requirements + +As there are two Triton Platforms used in this pilot, one as a Leader and the other a Follower, we need to load these with two different HDL images. + +```{warning} + Weblinks must be updated following release - placeholder only +``` + +- [Triton Leader HDL Image](https://www.minicircuits.com/WebStore/dashboard.html?model=ZC4PD-5R263-S%2B) +- [Triton Follower HDL Image](https://www.minicircuits.com/WebStore/dashboard.html?model=ZC4PD-5R263-S%2B) + +## Bring Up Steps +```{toctree} +:maxdepth: 4 + +Aion EVB Initialization +Triton Initialization +Python Script Execution + +``` + +```{note} +This resource list is regularly updated. For the most current information and additional resources, please visit the individual product pages and the ADI wiki. +``` + + +## Additional Links + +- [Analog Devices Main Website](https://www.analog.com/) +- [ADI Wiki](https://wiki.analog.com/) +- [Engineering Zone Forums](https://ez.analog.com/) +- [Triton Development Platform Product Page](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/python-exe/image.png b/docs/solutions/platforms/triton/dual-triton-mcs/python-exe/image.png new file mode 100644 index 00000000000..bb1247061c1 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/python-exe/image.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:85bea952907d45321548fdc049ae8c59c6828d636ec3ae5c68f6dfefcd63929f +size 32729 diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/python-exe/images/github-cloning.png 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the code + +```{note} +It is assumed that the user has gone through the standard bring up documentation for Triton as outlined earlier. If this is not the case please return to the Triton Home Page and familiarize yourself with this before executing the Dual Triton MCS Pilot. +``` + +Before setting up and executing the Python scripts, it is expected the user has been through the Aion EVB initialisation and the initialisation of both Leader and Follower Triton platforms. As outlined earlier in the Software Requirements section, there are different images for Triton #1 (Leader) and Triton #2 (Follower). You should follow this list of steps to bring up the Triton Hardware ahead of script execution. + +## Dual Triton GitHub - Clone the Branch + +At the time of writing this is a development branch and solely available to those internal to ADI. The user should clone the following branch and open the resulting folder in Visual Studio: + +[Dual Triton MCS - Development Branch](https://github.com/analogdevicesinc/pyadi-iio.git) + + +Use the following commands to clone the required branch, one these are executed you should see the branch at your chosen location as shown in the screenshot below using GitBash scripting. + + git clone https://github.com/analogdevicesinc/pyadi-iio.git + + git switch staging/dual-triton + +```{image} images/github-cloning.png +:width: 700px +:align: center +``` + + +## Python IDE - Setup + +With the correct branch cloned, we will now summarize the steps needed to configure the virtual environment ahead of script execution. The only IDE used for verification is Visual Studio and therefore we suggest you also use this for your setup. + +- Open Visual Studio application +- Using the File menu, open a folder within the application and navigate to the location where you cloned the PyIIO repository +- Using the Terminal menu, create a new terminal to setup the virtual environment +- Send the following commands to set it up correctly + - *`python -m venv dual_triton_venv`* + - *`.\dual_triton_venv\Scripts\activate`* + - *`python -m pip install --upgrade pip`* + - *`pip install -r requirements.txt`* + - *`pip install matplotlib`* + - *`pip install pandas`* + - *`pip install scipy`* + - *`pip install pyadi-iio`* + +This completes the setup of your Python Virtual Environment. + + +## Python Script Preparation + +The python script to execute can be found in the following location in the PyIIO Branch: + +*`"..\pyadi-iio\examples\dual_triton_sync_start.py"`* + +There are three configurations that must be set before executing the script: + +1. **Configure the Triton #1 and Triton #2 IP Addresses** + - These variables are entered in lines 16 & 17 as shown below and the correct IP Addresses assigned to the platforms should be configured here + + + ```{image} images/python-script-ip-address-config.png + :width: 500px + :align: center + ``` + +2. **Configure the TX and RX NCO Frequencies** + - There are two variables at lines 25 & 26 to configure the TX And RX NCO frequencies, these are applied to all channels on the Triton Platforms + - The variables are represented in Hertz + - The default settings are: + - 10000000000 for TX, representing 10 GHz + - -2800000000 for RX, representing 10 GHz in the second Nyquist zone for a 12.8 GSPS sample rate + + ```{image} images/python-script-nco-config.png + :width: 500px + :align: center + ``` + +3. **Zeroing the NCO Phase for Triton #2 Receivers** + - At line 37, there is a variable in milli-degrees for adjusting the NCO phase of the Rx NCO's on the second Triton Platform + - This should be set to zero for the initial execution and then post calibration, we will adjust to a static value for future runs + + ```{image} images/python-script-rx-triton-2-phase-adjustment.png + :width: 500px + :align: center + ``` + +## Python Script Execution & Expected Results + +We are now ready to execute the *`"dual_triton_sync_start.py"`* test script. To demonstrate the results successfully, the pilot will run the script three times: +- **Run 1** will measure me the NCO Phase offset between the Triton Platforms +- **Run 2** will apply this offset to the test software and we will re-measure the ADC capture delta between the systems demonstrating the +/-5psec accuracy +- **Run 3** will re-run Run 2 but after a 60-minute delay to show that it holds the +/-5psec accuracy and repeatability + +Below is a sample set of results from the execution of these three steps and you should be able to execute these on your setup if all the steps have been followed. + +### RUN 1 Results ### + +- We can see on the screenshots below, “SECOND_RX_MAIN_NCO_PHASE = 0” and when we execute the python script, we can see that the Phase delta between the Primary and Secondary Triton Platforms has a mean value of 33.94 degrees +- The lower graph shows the applied DAC signal in light blue and then the resulting ADC captures on each Triton ADC over the 10 iterations +- **Conclusion:** The Phase Delay is equivalent run to run with an overall mean of 33.94 degrees which is approximately 117.85 picoseconds delay + + ```{image} images/python-script-run-1-console-results.png + :width: 700px + :align: center + ``` + + ```{image} images/python-script-run-1-graph-results.png + :width: 700px + :align: center + ``` + +### RUN 2 Results ### + +- We can see on the screenshots below, “SECOND_RX_MAIN_NCO_PHASE = -33940”, which represents 33940 milli-degrees adjustment in the negative direction for the next execution +- We can see the Primary to Secondary phase delta is now reduced to an average of -0.46 degrees +- The lower graph shows the applied DAC signal in light blue and then the resulting ADC captures on each Triton ADC over the 10 iterations +- **Conclusion:** The Phase Delay is equivalent run to run with an overall mean of -0.46 degrees which is approximately -1.6 picoseconds delay + + ```{image} images/python-script-run-2-console-results.png + :width: 700px + :align: center + ``` + + ```{image} images/python-script-run-2-graph-results.png + :width: 700px + :align: center + ``` + +### RUN 3 Results ### + +- We re-measure the delta between the ADC data captured on Triton #1 and Triton #2 with “SECOND_RX_MAIN_NCO_PHASE = -33940” from the previous run but having waited 60 minutes +- We can see the Primary to Secondary phase delta is maintained at -1.05 degrees +- The lower graph shows the applied DAC signal in light blue and then the resulting ADC captures on each Triton ADC over the 10 iterations +- **Conclusion:** The Phase Delay holds after a one hour settling time with an overall mean of -1.05 degrees which is approximately -3.65 picoseconds delay + + ```{image} images/python-script-run-3-console-results.png + :width: 700px + :align: center + ``` + + ```{image} images/python-script-run-3-graph-results.png + :width: 700px + :align: center + ``` + + diff --git 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a/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md new file mode 100644 index 00000000000..4d8b36b6aa1 --- /dev/null +++ b/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md @@ -0,0 +1,181 @@ +# Triton Platform Initialization + +This section will cover the setup and initialization of the Triton Platform
+ +```{note} +It is assumed that the user has gone through the standard bring up documentation for Triton as outlined earlier. If this is not the case please return to the Triton Home Page and familiarize yourself with this before executing the Dual Triton MCS Pilot. +``` + +As outlined earlier in the Software Requirements section, there are different images for Triton #1 (Leader) and Triton #2 (Follower). You should follow this list of steps to bring up the Triton Hardware ahead of script execution. + +## 400MHz REF Clock Connection + +As outlined in the documentation earlier, each of the Triton boards needs to have a 400 MHz REF_CLOCK connected to the board before the system is powered on. This should be connected to SMP RF Connector **J34** as shown below on each of the boards. As per the block diagram, both Tritons should have the same 400MHz source through an RF Splitter. + +Once this clock is connected to the Triton Platforms, you can move to the next step + +```{image} images/triton-400mhz-ref-smp-connection.png +:width: 700px +:align: center +``` + +## Triton #1 JTAG Programming & Boot Up + +With the 400 MHZ REF_CLK connected, you can now power up the VCU118 and the Triton #1 Board. You should observe the Fans turning on above the Triton Heatsink and you should also see a blue LED illuminated confirming that the 400 MHz clock is connected correctly, **reference the image below** + +```{image} images/triton-400mhz-led.png +:width: 700px +:align: center +``` + +### Triton #1 JTAG Programming +On your PC, open a Vivado 2023.1 Tcl Shell, this will appear similar to a cmd or powershell window. It will communicate with the VCU118 over USB JTAG and program the FPGA and Microblaze image after which the Triton Platform will boot to Linux. You should also open a COMM port connection to the Triton #1 board, this can be identified in your PC's Device Manager. + +With the Vivado Tcl Shell open, you need to navigate to the location where you have stored the *primary* Triton image, load the debug shell and then program the platform. This can be achieved using the following commands. Reference the images below for guidance on pre-programming commands as well as expected response. + + cd C:\\Triton_Images\\Dual_Triton_MCS_Development\\vcu118_quad_ad9084_26p4_revB_ext_ms\\primary + + xsdb + + source run_triton_1.tcl + + +```{image} images/triton-1-vivado-programming.png +:width: 700px +:align: center +``` + +```{image} images/triton-1-vivado-programming-response.png +:width: 700px +:align: center +``` + +### Triton #1 UART Boot Up Verification +Having successfully programmed the Triton Platform over JTAG, you should move to monitor the COMM port console using the application of your choosing, e.g. Putty. As shown in the screenshots below, you will see an initial console output and then after about 2.5 mins, the system will complete its boot up sequence and you will be prompted to login to the system. + + + Username: root + + Password: analog + + +```{image} images/triton-1-uart-initial-console-output.png +:width: 700px +:align: center +``` + + + +```{image} images/triton-1-uart-bootup-completed.png +:width: 700px +:align: center +``` + +## Triton #2 JTAG Programming & Boot Up + +With the 400 MHZ REF_CLK connected, you can now power up the VCU118 and the Triton #2 Board. You should observe the Fans turning on above the Triton Heatsink and you should also see a blue LED illuminated confirming that the 400 MHz clock is connected correctly, reference the image below. + +```{image} images/triton-400mhz-led.png +:width: 700px +:align: center +``` + + +### Triton #2 JTAG Programming +On your PC, open a Vivado 2023.1 Tcl Shell, this will appear similar to a cmd or powershell window. It will communicate with the VCU118 over USB JTAG and program the FPGA and Microblaze image after which the Triton Platform will boot to Linux. You should also open a COMM port connection to the Triton #2 board, this can be identified in your PC's Device Manager. + +With the Vivado Tcl Shell open, you need to navigate to the location where you have stored the *second* Triton image, load the debug shell and then program the platform. This can be achieved using the following commands. Reference the images below for guidance on pre-programming commands as well as expected response. + + cd C:\\Triton_Images\\Dual_Triton_MCS_Development\\vcu118_quad_ad9084_26p4_revB_ext_ms\\second + + xsdb + + source run_triton_2.tcl + + +```{image} images/triton-2-vivado-programming.png +:width: 700px +:align: center +``` + +```{image} images/triton-2-vivado-programming-response.png +:width: 700px +:align: center +``` + +### Triton #2 UART Boot Up Verification +Having successfully programmed the Triton Platform over JTAG, you should move to monitor the COMM port console using the application of your choosing, e.g. Putty. As shown in the screenshots below, you will see an initial console output and then after about 2.5 mins, the system will complete its boot up sequence and you will be prompted to login to the system. + + Username: root + + Password: analog + +```{image} images/triton-2-uart-initial-console-output.png +:width: 700px +:align: center +``` + +```{image} images/triton-2-uart-bootup-completed.png +:width: 700px +:align: center +``` + +## IP Address Verification + +Primary and Secondary images for this pilot have configured the platforms to have independent MAC Addresses to ensure that each of the platforms are assigned independent IP Addresses to ensure independent control. We can check what these IP addresses using the *ifconfig* on each of the UART consoles and we note the address as it will be needed for the Python code execution. + +```{image} images/triton-1-ip-address-check.png +:width: 500px +:align: center +``` + +```{image} images/triton-2-ip-address-check.png +:width: 500px +:align: center +``` + + +## IIO Device Verification + +The Python scripts will communicate using Pyiio so we need to ensure that we have the expected devices listed on each of the systems. We can check these using the *iio_attr -d* and review the response for the expected 38 devices as shown below. + +**IMPORTANT:** If you do not see the same number of devices, please check that you have loaded the correct image. + +```{image} images/triton-iio-devices-check.png +:width: 500px +:align: center +``` + +## JESD Status Verification + +The last check we need to execute on each of the platforms before moving to the Python code execution is to check the JESD status. We can check this using the *jesd_status* command and this will show the status for both DAC's and ADC's. You can toggle between the two using the 'a' key. Ahead of running the command however, to ensure the formatting of the response is correct, we need to send a *resize* command to the UART terminal. + +For both the ADC and DAC JESD Status', the checks you are looking for are: + +- Ensure the *Link is* response is **enabled** +- Ensure the *Link Status* response is **DATA** +- Ensure the *Device and Link Clocks are* response is **400 MHz approx** +- Ensure the *Lane Rate MHz* response is **26400.000** +- Ensure the *Lane Rate / 66 MHz* response is **400.000** +- Ensure the *SYSREF captured* response is **Yes** +- Ensure the *SYSREF alignment error* response is **No** + +```{image} images/triton-resize-response.png +:width: 300px +:align: center +``` + +```{image} images/triton-jesd-adc-status.png +:width: 700px +:align: center +``` + +```{image} images/triton-jesd-dac-status.png +:width: 500px +:align: center +``` + + +****ONCE THE ABOVE CHECKS ARE COMPLETED SUCCESSFULLY MOVE TO THE PYTHON SCRIPT SETUP & EXECUTION**** + + diff --git a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png new file mode 100644 index 00000000000..8f82742f2c7 --- /dev/null +++ b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9940ba17cf1a365a0b0acbc211a38612de656879d4586001fdbf0f2545cc0d69 +size 44623 diff --git a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png new file mode 100644 index 00000000000..292cad0964d --- /dev/null +++ b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6b26c2c4c389f0834889f414fe140c8608797b4200e62b53129d9da831055a3f +size 382944 diff --git a/docs/solutions/platforms/triton/index.md b/docs/solutions/platforms/triton/index.md new file mode 100644 index 00000000000..da6d34b1591 --- /dev/null +++ b/docs/solutions/platforms/triton/index.md @@ -0,0 +1,61 @@ +(adc triton)= +# Triton (Quad Apollo) Development Platform + +The Quad-Apollo MxFE™ (mixed-signal front-end) X-band direct sampling digital beamforming platform is an advanced, every-element digital, direct RF-sampling solution that serves as a complete reference architecture for next-generation digital beamforming systems. Designed to highlight the capabilities of Analog Devices’ MxFE® technology, the platform integrates all critical subsystems—RF signal conditioning, precision clocking, multichip synchronization, and DC power management—into a unified, high performance environment that supports coherent, scalable signal processing across multiple channels. + +The platform enables quick time-to-market development programs for: Phased-Array, RADAR, Electronic Warfare and SATCOM + +The system is designed to mate with a [VCU118](https://www.xilinx.com/VCU118) Evaluation Board from Xilinx®, featuring the Virtex™ UltraScale+™ XCVU9P-L2FLGA2104E FPGA, with provided reference software, HDL code, and MATLAB/Python system-level interfacing. + +```{image} images/ADXBAND16EBZ-top-angle-evaluation-board.png +:width: 700px +:align: center +``` + + +## Triton Documentation Support + +As a released platform, Triton has its own product page where the user guide, bring up guide and associated technical articles are hosted to assist users of the system. Below are the links: + +```{warning} + Weblinks must be updated following release - placeholder only +``` + +- [**Triton Development Platform - Product Page**](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) +- [**Triton Development Platform - User Guide**](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) +- [**Triton Development Platform - Bring Up Guide**](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) +- [**Triton Development Platform - Technical Articles**](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) + +## Triton Software Support + +The Triton Quad Apollo has two HDL Images (Hardware Description Language) available for users. As outlined in the table below, both images are operating at 12.8 GHz Sample Clock and the only difference between the two configurations is the resulting usable instantaneous Bandwidth (iBW); 320 MHz vs. 640 MHz +Below are the links to the two images and the user should reference the Bring Up Guide documentation for the steps to program the system. + +```{warning} + Weblinks must be updated following release - placeholder only +``` +- [** 320 MHz iBW **](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) +- [** 640 MHz iBW **](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) + +```{image} images/ADXBAND16EBZ-available-configurations.png +:width: 700px +:align: center +``` + +## Triton System Platforms - Demo & Pilots + +The System Platform team are here to support customers in the integration of this platform, whether that is as a standalone system or a sub-assembly in a larger system, we can help. To this end, we have generated the following pilot we believe you will find useful + + +```{toctree} +:maxdepth: 2 + +Dual Triton MultiChip Sync (MCS) Pilot +``` + +```{note} +For questions or help with the Triton Development Platform, please visit: +
+[https://ez.analog.com/adef-system-platforms/](https://ez.analog.com/adef-system-platforms/) +``` + From 3a1b2638337b59944ce46b70cc6add7d06af0f1c Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Fri, 17 Apr 2026 17:15:54 +0100 Subject: [PATCH 2/6] Fixed front page syntax. --- docs/solutions/platforms/index.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/solutions/platforms/index.md b/docs/solutions/platforms/index.md index d548b9a2c39..f3e6e8e51cb 100644 --- a/docs/solutions/platforms/index.md +++ b/docs/solutions/platforms/index.md @@ -74,7 +74,7 @@ Low-cost SDR system based on the AD9361 ```{image} resources/pluto.png ``` ```` -````` + ````{card} Triton :ref: adc triton @@ -84,6 +84,7 @@ Low-cost SDR system based on the AD9361 ```{image} resources/ADXBAND16EBZ_top-angle-evaluation-board.png ``` ```` +````` ## Platform Pilots From 7c4f5f2e022b675b529112ddc6604dd993255bbc Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Fri, 17 Apr 2026 17:24:52 +0100 Subject: [PATCH 3/6] Addition of missing image. Signed-off-by: ANALOG\IDerring --- .../resources/ADXBAND16EBZ_top-angle-evaluation-board.png | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 docs/solutions/platforms/resources/ADXBAND16EBZ_top-angle-evaluation-board.png diff --git a/docs/solutions/platforms/resources/ADXBAND16EBZ_top-angle-evaluation-board.png b/docs/solutions/platforms/resources/ADXBAND16EBZ_top-angle-evaluation-board.png new file mode 100644 index 00000000000..292cad0964d --- /dev/null +++ b/docs/solutions/platforms/resources/ADXBAND16EBZ_top-angle-evaluation-board.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6b26c2c4c389f0834889f414fe140c8608797b4200e62b53129d9da831055a3f +size 382944 From 52c2354e4100130a393cceec3a743916ad0834a3 Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Fri, 17 Apr 2026 17:52:03 +0100 Subject: [PATCH 4/6] Addition of missing image. Signed-off-by: ANALOG\IDerring --- ...alignment.png => dual-triton-mcs-aion-bsync-1-3-alignment.png} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/{dual-triton-mcs-aion-bysnc-1-3-alignment.png => dual-triton-mcs-aion-bsync-1-3-alignment.png} (100%) diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bysnc-1-3-alignment.png b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bsync-1-3-alignment.png similarity index 100% rename from docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bysnc-1-3-alignment.png rename to docs/solutions/platforms/triton/dual-triton-mcs/aion-init/images/dual-triton-mcs-aion-bsync-1-3-alignment.png From 017e8b5640cf1d70cdae62b0a97ac48bc6488ff9 Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Mon, 20 Apr 2026 14:45:17 +0100 Subject: [PATCH 5/6] removed images with caps on --- .../triton/images/ADXBAND16EBZ-available-configurations.png | 3 --- .../triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png | 3 --- 2 files changed, 6 deletions(-) delete mode 100644 docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png delete mode 100644 docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png diff --git a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png deleted file mode 100644 index 8f82742f2c7..00000000000 --- a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-available-configurations.png +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:9940ba17cf1a365a0b0acbc211a38612de656879d4586001fdbf0f2545cc0d69 -size 44623 diff --git a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png b/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png deleted file mode 100644 index 292cad0964d..00000000000 --- a/docs/solutions/platforms/triton/images/ADXBAND16EBZ-top-angle-evaluation-board.png +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:6b26c2c4c389f0834889f414fe140c8608797b4200e62b53129d9da831055a3f -size 382944 From b485c57a4b00e961ff410c7e45789893759dbf73 Mon Sep 17 00:00:00 2001 From: "ANALOG\\IDerring" Date: Mon, 20 Apr 2026 14:46:01 +0100 Subject: [PATCH 6/6] Added images with lower case names --- .../triton/dual-triton-mcs/aion-init/index.md | 5 +++-- .../platforms/triton/dual-triton-mcs/index.md | 6 +++--- .../triton/dual-triton-mcs/triton-init/index.md | 11 +++++------ .../images/adxband16ebx-available-configurations.png | 3 +++ .../adxband16ebx-top-angle-evaluation-board.png | 3 +++ docs/solutions/platforms/triton/index.md | 4 ++-- 6 files changed, 19 insertions(+), 13 deletions(-) create mode 100644 docs/solutions/platforms/triton/images/adxband16ebx-available-configurations.png create mode 100644 docs/solutions/platforms/triton/images/adxband16ebx-top-angle-evaluation-board.png diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md index 974e9ee8b90..82e868d4734 100644 --- a/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md +++ b/docs/solutions/platforms/triton/dual-triton-mcs/aion-init/index.md @@ -87,8 +87,9 @@ The following are the steps to install the software correctly: :width: 700px :align: center ``` - -****The Aion EVB and Interposer Board is now configured as needed and you can move to the Triton Initialization steps**** +```{attention} + The Aion EVB and Interposer Board is now configured as needed and you can move to the Triton Initialization steps +``` ## Additional Links diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/index.md index 1b30b0a9130..10d2f74445a 100644 --- a/docs/solutions/platforms/triton/dual-triton-mcs/index.md +++ b/docs/solutions/platforms/triton/dual-triton-mcs/index.md @@ -31,11 +31,11 @@ The following hardware is needed to successfully setup this pilot: As there are two Triton Platforms used in this pilot, one as a Leader and the other a Follower, we need to load these with two different HDL images. ```{warning} - Weblinks must be updated following release - placeholder only + Weblinks are to the System Platforms Teams Channel, these will be updated following release ``` -- [Triton Leader HDL Image](https://www.minicircuits.com/WebStore/dashboard.html?model=ZC4PD-5R263-S%2B) -- [Triton Follower HDL Image](https://www.minicircuits.com/WebStore/dashboard.html?model=ZC4PD-5R263-S%2B) +- [Triton Leader HDL Image](https://analog.sharepoint.com/:f:/r/sites/ADC_System_Platforms_Team/Shared%20Documents/General/Transfer/Temp_Dual_Triton_MCS/primary?csf=1&web=1&e=bQhbBD) +- [Triton Follower HDL Image](https://analog.sharepoint.com/:f:/r/sites/ADC_System_Platforms_Team/Shared%20Documents/General/Transfer/Temp_Dual_Triton_MCS/second?csf=1&web=1&e=0MEBLD) ## Bring Up Steps ```{toctree} diff --git a/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md b/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md index 4d8b36b6aa1..33541b71a92 100644 --- a/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md +++ b/docs/solutions/platforms/triton/dual-triton-mcs/triton-init/index.md @@ -1,6 +1,6 @@ # Triton Platform Initialization -This section will cover the setup and initialization of the Triton Platform
+This section will cover the setup and initialization of the Triton Platform ```{note} It is assumed that the user has gone through the standard bring up documentation for Triton as outlined earlier. If this is not the case please return to the Triton Home Page and familiarize yourself with this before executing the Dual Triton MCS Pilot. @@ -174,8 +174,7 @@ For both the ADC and DAC JESD Status', the checks you are looking for are: :width: 500px :align: center ``` - - -****ONCE THE ABOVE CHECKS ARE COMPLETED SUCCESSFULLY MOVE TO THE PYTHON SCRIPT SETUP & EXECUTION**** - - + +```{attention} + The Triton boards are now initialised and configured as needed and you can move to the Python Execution steps +``` diff --git a/docs/solutions/platforms/triton/images/adxband16ebx-available-configurations.png b/docs/solutions/platforms/triton/images/adxband16ebx-available-configurations.png new file mode 100644 index 00000000000..8f82742f2c7 --- /dev/null +++ b/docs/solutions/platforms/triton/images/adxband16ebx-available-configurations.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9940ba17cf1a365a0b0acbc211a38612de656879d4586001fdbf0f2545cc0d69 +size 44623 diff --git a/docs/solutions/platforms/triton/images/adxband16ebx-top-angle-evaluation-board.png b/docs/solutions/platforms/triton/images/adxband16ebx-top-angle-evaluation-board.png new file mode 100644 index 00000000000..292cad0964d --- /dev/null +++ b/docs/solutions/platforms/triton/images/adxband16ebx-top-angle-evaluation-board.png @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:6b26c2c4c389f0834889f414fe140c8608797b4200e62b53129d9da831055a3f +size 382944 diff --git a/docs/solutions/platforms/triton/index.md b/docs/solutions/platforms/triton/index.md index da6d34b1591..991f9bd4732 100644 --- a/docs/solutions/platforms/triton/index.md +++ b/docs/solutions/platforms/triton/index.md @@ -7,7 +7,7 @@ The platform enables quick time-to-market development programs for: Phased-Array The system is designed to mate with a [VCU118](https://www.xilinx.com/VCU118) Evaluation Board from Xilinx®, featuring the Virtex™ UltraScale+™ XCVU9P-L2FLGA2104E FPGA, with provided reference software, HDL code, and MATLAB/Python system-level interfacing. -```{image} images/ADXBAND16EBZ-top-angle-evaluation-board.png +```{image} images/adxband16ebz-top-angle-evaluation-board.png :width: 700px :align: center ``` @@ -37,7 +37,7 @@ Below are the links to the two images and the user should reference the Bring Up - [** 320 MHz iBW **](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) - [** 640 MHz iBW **](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adxband16ebz.html) -```{image} images/ADXBAND16EBZ-available-configurations.png +```{image} images/adxband16ebz-available-configurations.png :width: 700px :align: center ```