diff --git a/.mill-version b/.mill-version new file mode 100644 index 0000000..e5cbde3 --- /dev/null +++ b/.mill-version @@ -0,0 +1 @@ +0.11.6 diff --git a/Makefile b/Makefile index 738a3a6..75dc3c6 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -SBT?=sbt +MILL?=./mill DRIVER?=DMAController.DMADriver TB=ControllerSpec @@ -9,29 +9,28 @@ IMG=bunny.png TAG:=$(shell git describe --tags --abbrev=0) export TAG - verilog: - $(SBT) "runMain $(DRIVER) $(CONFIG_FILE)" + $(MILL) vdma.runMain --mainClass $(DRIVER) -- $(CONFIG_FILE) testsetup: convert -resize $(SIZE_HALF)x$(SIZE_HALF) $(IMG) img0.rgba convert -resize $(SIZE)x$(SIZE) $(IMG) img1.rgba testM2M: testsetup - $(SBT) "Test / testOnly -t *$(TB)" + $(MILL) vdma.test.testOnly "*$(TB)" convert -size $(SIZE)x$(SIZE) -depth 8 outAXI_AXIL_AXI.rgba outM2M.png testS2M: testsetup - $(SBT) "Test / testOnly -t *$(TB)" + $(MILL) vdma.test.testOnly "*$(TB)" convert -size $(SIZE)x$(SIZE) -depth 8 outAXIS_AXIL_AXI.rgba outS2M.png test: testS2M testM2M testall: test - $(SBT) "test" + $(MILL) vdma.test clean: - $(SBT) clean + $(MILL) clean .PHONY: verilog test testall diff --git a/build.sbt b/build.sbt deleted file mode 100644 index 3eacff9..0000000 --- a/build.sbt +++ /dev/null @@ -1,57 +0,0 @@ -// See README.md for license details. - -def scalacOptionsVersion(scalaVersion: String): Seq[String] = { - Seq() ++ { - // If we're building with Scala > 2.11, enable the compile option - // switch to support our anonymous Bundle definitions: - // https://github.com/scala/bug/issues/10047 - CrossVersion.partialVersion(scalaVersion) match { - case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq() - case _ => Seq("-Xsource:2.11") - } - } -} - -def javacOptionsVersion(scalaVersion: String): Seq[String] = { - Seq() ++ { - // Scala 2.12 requires Java 8. We continue to generate - // Java 7 compatible code for Scala 2.11 - // for compatibility with old clients. - CrossVersion.partialVersion(scalaVersion) match { - case Some((2, scalaMajor: Long)) if scalaMajor < 12 => - Seq("-source", "1.7", "-target", "1.7") - case _ => - Seq("-source", "1.8", "-target", "1.8") - } - } -} - -name := "chisel-dma" - -version := "3.5.3" - -scalaVersion := "2.12.13" - -crossScalaVersions := Seq("2.11.12", "2.12.13") - -resolvers ++= Seq( - Resolver.sonatypeRepo("snapshots"), - Resolver.sonatypeRepo("releases") -) -// Chisel 3.5 -addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full) - -// Provide a managed dependency on X if -DXVersion="" is supplied on the command line. -val defaultVersions = Map( - "chisel3" -> "3.5.+", - "chiseltest" -> "0.5.0", - "chisel-iotesters" -> "2.5.5+" - ) -libraryDependencies ++= Seq("chisel3","chiseltest","chisel-iotesters").map { - dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) } - -libraryDependencies += "com.typesafe.play" %% "play-json" % "2.8.+" - -scalacOptions ++= scalacOptionsVersion(scalaVersion.value) - -javacOptions ++= javacOptionsVersion(scalaVersion.value) diff --git a/build.sc b/build.sc new file mode 100644 index 0000000..e8be2cc --- /dev/null +++ b/build.sc @@ -0,0 +1,131 @@ +import mill._ +import mill.scalalib._ +import mill.scalalib.scalafmt._ + +object ivys { + val scalaVersion = "2.13.12" + + val ivyVersions = Map( + "org.chipsalliance::chisel" -> "6.0.0", + "org.chipsalliance:::chisel-plugin" -> "$chisel", + "edu.berkeley.cs::chiseltest" -> "6.0-LOCAL-SNAPSHOT", + "com.lihaoyi::mainargs" -> "0.5.4+", + "org.scala-lang:scala-reflect" -> scalaVersion, + "com.typesafe.play::play-json" -> "2.10.4+" + ) + + lazy val nameMap = Map.from(ivyVersions.map { case (k, v) => + val kSplit = k.split(':') + kSplit.last -> (k, v) + }) + + def lookup(name: String): (String, String) = + nameMap.getOrElse(name, (name, ivyVersions(name))) + + @annotation.tailrec + def getVersion(version: String): String = { + if (version.startsWith("$")) { + val v = lookup(version.stripPrefix("$"))._2 + getVersion(v) + } else version + } + + def dep(name: String): Dep = { + val (fqn, v) = lookup(name) + ivy"$fqn:${getVersion(v)}" + } +} + +trait CommonModule extends mill.Module with CoursierModule { + + override def repositoriesTask = T.task { + import coursier.maven.MavenRepository + + super.repositoriesTask() ++ Seq( // + MavenRepository("https://oss.sonatype.org/content/repositories/releases"), + MavenRepository( + "https://oss.sonatype.org/content/repositories/snapshots" + ), + MavenRepository( + "https://s01.oss.sonatype.org/content/repositories/releases" + ), + MavenRepository( + "https://s01.oss.sonatype.org/content/repositories/snapshots" + ), + MavenRepository("https://jitpack.io"), + MavenRepository(s"file://${os.home}/.m2/repository") + ) + } + + def dep(name: String) = ivys.dep(name) +} + +trait CommonScalaModule + extends CommonModule + with ScalaModule + with ScalafmtModule { + override def scalaVersion = ivys.scalaVersion + + override def scalacOptions = Seq( + // checks + "-deprecation", + "-feature", + "-Xcheckinit", + // warnings + // "-Wunused", + "-Xlint:adapted-args", + "-Wconf:cat=unused&msg=parameter .* in .* never used:silent", + "-Wconf:src=dependencies/.*:silent" + ) +} + +trait ChiselModule extends CommonScalaModule { + override def ivyDeps = super.ivyDeps() ++ Agg( + dep("chisel") + ) + + override def scalacPluginIvyDeps = Agg( + dep("chisel-plugin") + ) + + override def scalacOptions = super.scalacOptions() ++ Seq( + // chisel: + "-Ymacro-annotations", + "-language:reflectiveCalls", + // ignore warning for arguments starting with an underscore + "-Wconf:cat=unused&msg=parameter _.* in .* is never used:s", + "-Wconf:cat=deprecation&msg=Importing from firrtl is deprecated:s", + "-Wconf:cat=deprecation&msg=will not be supported as part of the migration to the MLIR-based FIRRTL Compiler:s" + ) +} + +trait InnerChiselTestModule + extends CommonScalaModule + with TestModule.ScalaTest { + override def ivyDeps = super.ivyDeps() ++ Agg( + dep("chiseltest") + ) +} + +trait MacrosModule extends ChiselModule { + override def ivyDeps = super.ivyDeps() ++ Agg( + dep("scala-reflect") + ) + + override def scalacOptions = super.scalacOptions() ++ Seq( + "-language:experimental.macros" + ) +} + +///=============================================================================================/// + +object vdma extends SbtModule with ChiselModule { + override def millSourcePath = super.millSourcePath / os.up + object test extends InnerChiselTestModule with SbtModuleTests { + // + } + override def ivyDeps = super.ivyDeps() ++ Agg( + dep("play-json") + ) +} +///=============================================================================================/// diff --git a/mill b/mill new file mode 100755 index 0000000..9d343ff --- /dev/null +++ b/mill @@ -0,0 +1,241 @@ +#!/usr/bin/env sh + +# This is a wrapper script, that automatically download mill from GitHub release pages +# You can give the required mill version with --mill-version parameter +# If no version is given, it falls back to the value of DEFAULT_MILL_VERSION +# +# Project page: https://github.com/lefou/millw +# Script Version: 0.4.11 +# +# If you want to improve this script, please also contribute your changes back! +# +# Licensed under the Apache License, Version 2.0 + +set -e + +if [ -z "${DEFAULT_MILL_VERSION}" ] ; then + DEFAULT_MILL_VERSION="0.11.4" +fi + + +if [ -z "${GITHUB_RELEASE_CDN}" ] ; then + GITHUB_RELEASE_CDN="" +fi + + +MILL_REPO_URL="https://github.com/com-lihaoyi/mill" + +if [ -z "${CURL_CMD}" ] ; then + CURL_CMD=curl +fi + +# Explicit commandline argument takes precedence over all other methods +if [ "$1" = "--mill-version" ] ; then + shift + if [ "x$1" != "x" ] ; then + MILL_VERSION="$1" + shift + else + echo "You specified --mill-version without a version." 1>&2 + echo "Please provide a version that matches one provided on" 1>&2 + echo "${MILL_REPO_URL}/releases" 1>&2 + false + fi +fi + +# Please note, that if a MILL_VERSION is already set in the environment, +# We reuse it's value and skip searching for a value. + +# If not already set, read .mill-version file +if [ -z "${MILL_VERSION}" ] ; then + if [ -f ".mill-version" ] ; then + MILL_VERSION="$(head -n 1 .mill-version 2> /dev/null)" + elif [ -f ".config/mill-version" ] ; then + MILL_VERSION="$(head -n 1 .config/mill-version 2> /dev/null)" + fi +fi + +MILL_USER_CACHE_DIR="${XDG_CACHE_HOME:-${HOME}/.cache}/mill" + +if [ -z "${MILL_DOWNLOAD_PATH}" ] ; then + MILL_DOWNLOAD_PATH="${MILL_USER_CACHE_DIR}/download" +fi + +# If not already set, try to fetch newest from Github +if [ -z "${MILL_VERSION}" ] ; then + # TODO: try to load latest version from release page + echo "No mill version specified." 1>&2 + echo "You should provide a version via '.mill-version' file or --mill-version option." 1>&2 + + mkdir -p "${MILL_DOWNLOAD_PATH}" + LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest" 2>/dev/null || ( + # we might be on OSX or BSD which don't have -d option for touch + # but probably a -A [-][[hh]mm]SS + touch "${MILL_DOWNLOAD_PATH}/.expire_latest"; touch -A -010000 "${MILL_DOWNLOAD_PATH}/.expire_latest" + ) || ( + # in case we still failed, we retry the first touch command with the intention + # to show the (previously suppressed) error message + LANG=C touch -d '1 hour ago' "${MILL_DOWNLOAD_PATH}/.expire_latest" + ) + + # POSIX shell variant of bash's -nt operator, see https://unix.stackexchange.com/a/449744/6993 + # if [ "${MILL_DOWNLOAD_PATH}/.latest" -nt "${MILL_DOWNLOAD_PATH}/.expire_latest" ] ; then + if [ -n "$(find -L "${MILL_DOWNLOAD_PATH}/.latest" -prune -newer "${MILL_DOWNLOAD_PATH}/.expire_latest")" ]; then + # we know a current latest version + MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null) + fi + + if [ -z "${MILL_VERSION}" ] ; then + # we don't know a current latest version + echo "Retrieving latest mill version ..." 1>&2 + LANG=C ${CURL_CMD} -s -i -f -I ${MILL_REPO_URL}/releases/latest 2> /dev/null | grep --ignore-case Location: | sed s'/^.*tag\///' | tr -d '\r\n' > "${MILL_DOWNLOAD_PATH}/.latest" + MILL_VERSION=$(head -n 1 "${MILL_DOWNLOAD_PATH}"/.latest 2> /dev/null) + fi + + if [ -z "${MILL_VERSION}" ] ; then + # Last resort + MILL_VERSION="${DEFAULT_MILL_VERSION}" + echo "Falling back to hardcoded mill version ${MILL_VERSION}" 1>&2 + else + echo "Using mill version ${MILL_VERSION}" 1>&2 + fi +fi + +MILL="${MILL_DOWNLOAD_PATH}/${MILL_VERSION}" + +try_to_use_system_mill() { + if [ "$(uname)" != "Linux" ]; then + return 0 + fi + + MILL_IN_PATH="$(command -v mill || true)" + + if [ -z "${MILL_IN_PATH}" ]; then + return 0 + fi + + SYSTEM_MILL_FIRST_TWO_BYTES=$(head --bytes=2 "${MILL_IN_PATH}") + if [ "${SYSTEM_MILL_FIRST_TWO_BYTES}" = "#!" ]; then + # MILL_IN_PATH is (very likely) a shell script and not the mill + # executable, ignore it. + return 0 + fi + + SYSTEM_MILL_PATH=$(readlink -e "${MILL_IN_PATH}") + SYSTEM_MILL_SIZE=$(stat --format=%s "${SYSTEM_MILL_PATH}") + SYSTEM_MILL_MTIME=$(stat --format=%y "${SYSTEM_MILL_PATH}") + + if [ ! -d "${MILL_USER_CACHE_DIR}" ]; then + mkdir -p "${MILL_USER_CACHE_DIR}" + fi + + SYSTEM_MILL_INFO_FILE="${MILL_USER_CACHE_DIR}/system-mill-info" + if [ -f "${SYSTEM_MILL_INFO_FILE}" ]; then + parseSystemMillInfo() { + LINE_NUMBER="${1}" + # Select the line number of the SYSTEM_MILL_INFO_FILE, cut the + # variable definition in that line in two halves and return + # the value, and finally remove the quotes. + sed -n "${LINE_NUMBER}p" "${SYSTEM_MILL_INFO_FILE}" |\ + cut -d= -f2 |\ + sed 's/"\(.*\)"/\1/' + } + + CACHED_SYSTEM_MILL_PATH=$(parseSystemMillInfo 1) + CACHED_SYSTEM_MILL_VERSION=$(parseSystemMillInfo 2) + CACHED_SYSTEM_MILL_SIZE=$(parseSystemMillInfo 3) + CACHED_SYSTEM_MILL_MTIME=$(parseSystemMillInfo 4) + + if [ "${SYSTEM_MILL_PATH}" = "${CACHED_SYSTEM_MILL_PATH}" ] \ + && [ "${SYSTEM_MILL_SIZE}" = "${CACHED_SYSTEM_MILL_SIZE}" ] \ + && [ "${SYSTEM_MILL_MTIME}" = "${CACHED_SYSTEM_MILL_MTIME}" ]; then + if [ "${CACHED_SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then + MILL="${SYSTEM_MILL_PATH}" + return 0 + else + return 0 + fi + fi + fi + + SYSTEM_MILL_VERSION=$(${SYSTEM_MILL_PATH} --version | head -n1 | sed -n 's/^Mill.*version \(.*\)/\1/p') + + cat < "${SYSTEM_MILL_INFO_FILE}" +CACHED_SYSTEM_MILL_PATH="${SYSTEM_MILL_PATH}" +CACHED_SYSTEM_MILL_VERSION="${SYSTEM_MILL_VERSION}" +CACHED_SYSTEM_MILL_SIZE="${SYSTEM_MILL_SIZE}" +CACHED_SYSTEM_MILL_MTIME="${SYSTEM_MILL_MTIME}" +EOF + + if [ "${SYSTEM_MILL_VERSION}" = "${MILL_VERSION}" ]; then + MILL="${SYSTEM_MILL_PATH}" + fi +} +try_to_use_system_mill + +# If not already downloaded, download it +if [ ! -s "${MILL}" ] ; then + + # support old non-XDG download dir + MILL_OLD_DOWNLOAD_PATH="${HOME}/.mill/download" + OLD_MILL="${MILL_OLD_DOWNLOAD_PATH}/${MILL_VERSION}" + if [ -x "${OLD_MILL}" ] ; then + MILL="${OLD_MILL}" + else + case $MILL_VERSION in + 0.0.* | 0.1.* | 0.2.* | 0.3.* | 0.4.* ) + DOWNLOAD_SUFFIX="" + DOWNLOAD_FROM_MAVEN=0 + ;; + 0.5.* | 0.6.* | 0.7.* | 0.8.* | 0.9.* | 0.10.* | 0.11.0-M* ) + DOWNLOAD_SUFFIX="-assembly" + DOWNLOAD_FROM_MAVEN=0 + ;; + *) + DOWNLOAD_SUFFIX="-assembly" + DOWNLOAD_FROM_MAVEN=1 + ;; + esac + + DOWNLOAD_FILE=$(mktemp mill.XXXXXX) + + if [ "$DOWNLOAD_FROM_MAVEN" = "1" ] ; then + DOWNLOAD_URL="https://repo1.maven.org/maven2/com/lihaoyi/mill-dist/${MILL_VERSION}/mill-dist-${MILL_VERSION}.jar" + else + MILL_VERSION_TAG=$(echo "$MILL_VERSION" | sed -E 's/([^-]+)(-M[0-9]+)?(-.*)?/\1\2/') + DOWNLOAD_URL="${GITHUB_RELEASE_CDN}${MILL_REPO_URL}/releases/download/${MILL_VERSION_TAG}/${MILL_VERSION}${DOWNLOAD_SUFFIX}" + unset MILL_VERSION_TAG + fi + + # TODO: handle command not found + echo "Downloading mill ${MILL_VERSION} from ${DOWNLOAD_URL} ..." 1>&2 + ${CURL_CMD} -f -L -o "${DOWNLOAD_FILE}" "${DOWNLOAD_URL}" + chmod +x "${DOWNLOAD_FILE}" + mkdir -p "${MILL_DOWNLOAD_PATH}" + mv "${DOWNLOAD_FILE}" "${MILL}" + + unset DOWNLOAD_FILE + unset DOWNLOAD_SUFFIX + fi +fi + +if [ -z "$MILL_MAIN_CLI" ] ; then + MILL_MAIN_CLI="${0}" +fi + +MILL_FIRST_ARG="" +if [ "$1" = "--bsp" ] || [ "$1" = "-i" ] || [ "$1" = "--interactive" ] || [ "$1" = "--no-server" ] || [ "$1" = "--repl" ] || [ "$1" = "--help" ] ; then + # Need to preserve the first position of those listed options + MILL_FIRST_ARG=$1 + shift +fi + +unset MILL_DOWNLOAD_PATH +unset MILL_OLD_DOWNLOAD_PATH +unset OLD_MILL +unset MILL_VERSION +unset MILL_REPO_URL + +# We don't quote MILL_FIRST_ARG on purpose, so we can expand the empty value without quotes +# shellcheck disable=SC2086 +exec "${MILL}" $MILL_FIRST_ARG -D "mill.main.cli=${MILL_MAIN_CLI}" "$@" diff --git a/project/build.properties b/project/build.properties deleted file mode 100644 index f6acff8..0000000 --- a/project/build.properties +++ /dev/null @@ -1 +0,0 @@ -sbt.version = 1.6.2 diff --git a/project/plugins.sbt b/project/plugins.sbt deleted file mode 100644 index 14a6ca1..0000000 --- a/project/plugins.sbt +++ /dev/null @@ -1 +0,0 @@ -logLevel := Level.Warn \ No newline at end of file diff --git a/project/scalastyle-config.xml b/project/scalastyle-config.xml deleted file mode 100644 index fba0a64..0000000 --- a/project/scalastyle-config.xml +++ /dev/null @@ -1,110 +0,0 @@ - - Scalastyle standard configuration - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No lines ending with a ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]> - - - - - - - - - - - diff --git a/project/scalastyle-test-config.xml b/project/scalastyle-test-config.xml deleted file mode 100644 index 399ac02..0000000 --- a/project/scalastyle-test-config.xml +++ /dev/null @@ -1,109 +0,0 @@ - - Scalastyle configuration for Chisel3 unit tests - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - No lines ending with a ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |\|\||&&|:=|<>|<=|>=|!=|===|<<|>>|##|unary_(~|\-%?|!))$]]> - - - - - - - - - - - diff --git a/src/main/scala/DMAController/CSR/ClearCSR.scala b/src/main/scala/DMAController/CSR/ClearCSR.scala index c7d57a5..5efd313 100644 --- a/src/main/scala/DMAController/CSR/ClearCSR.scala +++ b/src/main/scala/DMAController/CSR/ClearCSR.scala @@ -13,9 +13,10 @@ SPDX-License-Identifier: Apache-2.0 */ package DMAController.CSR -import DMAController.DMADriver -import DMAUtils.DMAModule + import chisel3._ + +import DMAUtils.DMAModule import DMAController.DMAConfig.DMAConfig class ClearCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) { diff --git a/src/main/scala/DMAController/CSR/SetCSR.scala b/src/main/scala/DMAController/CSR/SetCSR.scala index 851ff47..ce7f7aa 100644 --- a/src/main/scala/DMAController/CSR/SetCSR.scala +++ b/src/main/scala/DMAController/CSR/SetCSR.scala @@ -15,9 +15,9 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.CSR import chisel3._ -import DMAUtils.DMAModule -import DMAController.DMADriver + import DMAController.DMAConfig._ +import DMAUtils.DMAModule class SetCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) { val io = IO(new Bundle { diff --git a/src/main/scala/DMAController/CSR/SimpleCSR.scala b/src/main/scala/DMAController/CSR/SimpleCSR.scala index 5fe8ce8..7381462 100644 --- a/src/main/scala/DMAController/CSR/SimpleCSR.scala +++ b/src/main/scala/DMAController/CSR/SimpleCSR.scala @@ -14,10 +14,9 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.CSR -import chisel3._ -import DMAUtils.DMAModule -import DMAController.DMADriver import DMAController.DMAConfig._ +import DMAUtils.DMAModule +import chisel3._ class SimpleCSR(config: DMAConfig) extends DMAModule(config) { val io = IO(new Bundle { diff --git a/src/main/scala/DMAController/CSR/StatusCSR.scala b/src/main/scala/DMAController/CSR/StatusCSR.scala index 8e772ae..21ad589 100644 --- a/src/main/scala/DMAController/CSR/StatusCSR.scala +++ b/src/main/scala/DMAController/CSR/StatusCSR.scala @@ -14,10 +14,9 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.CSR +import DMAController.DMAConfig._ import DMAUtils.DMAModule -import DMAController.DMADriver import chisel3._ -import DMAController.DMAConfig._ class StatusCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig){ val io = IO(new Bundle{ diff --git a/src/main/scala/DMAController/DMAConfig.scala b/src/main/scala/DMAController/DMAConfig.scala index ecb8e61..bc04d06 100644 --- a/src/main/scala/DMAController/DMAConfig.scala +++ b/src/main/scala/DMAController/DMAConfig.scala @@ -15,11 +15,6 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.DMAConfig import chisel3._ -import DMAController.Bus._ -import DMAController.CSR.CSR -import DMAController.Frontend._ -import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle} -import chisel3.util.Queue class DMAConfig( val busConfig: String = "AXI_AXIL_AXI", @@ -122,7 +117,7 @@ object DMAConfig { configurations.apply(cfg) } catch { case ex: Exception => - throw new Exception("Unsupported DMA configuration: " + cfg) + throw new Exception(s"Unsupported DMA configuration: ${ex.getMessage} \nConfiguration: $cfg") } } diff --git a/src/main/scala/DMAController/DMADriver.scala b/src/main/scala/DMAController/DMADriver.scala index ba76bbe..799f631 100644 --- a/src/main/scala/DMAController/DMADriver.scala +++ b/src/main/scala/DMAController/DMADriver.scala @@ -10,12 +10,12 @@ See the License for the specific language governing permissions and limitations under the License. SPDX-License-Identifier: Apache-2.0 -*/ + */ package DMAController -import chisel3.stage.ChiselStage -import DMAConfig._ +import circt.stage.ChiselStage + import DMAUtils.{DMAParseInput, DMALogger} import DMAController.DMAConfig._ @@ -36,5 +36,5 @@ object DMADriver extends App { } } - (new ChiselStage).emitVerilog(new DMATop(config)) + ChiselStage.emitSystemVerilogFile(new DMATop(config)) } diff --git a/src/main/scala/DMAController/DMATop.scala b/src/main/scala/DMAController/DMATop.scala index b9d8bbd..7937484 100644 --- a/src/main/scala/DMAController/DMATop.scala +++ b/src/main/scala/DMAController/DMATop.scala @@ -14,14 +14,14 @@ SPDX-License-Identifier: Apache-2.0 package DMAController -import chisel3._ -import chisel3.util._ -import DMAController.Bus._ import DMAController.CSR._ -import DMAController.Frontend._ -import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle} import DMAController.DMAConfig._ +import DMAController.Frontend._ +import DMAController.Worker.InterruptBundle +import DMAController.Worker.SyncBundle +import DMAController.Worker.WorkerCSRWrapper import DMAUtils._ +import chisel3._ class DMATop(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) { val (reader, ccsr, writer) = dmaConfig.getBusConfig() diff --git a/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala b/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala index e8746a4..abc6fb8 100644 --- a/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala +++ b/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.AXI4Lite -import DMAController.CSR.{CSR, CSRBusBundle} -import DMAController.Worker.{WorkerCSRWrapper} +import DMAController.CSR.CSRBusBundle +import DMAController.DMAConfig._ import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class AXI4LiteCSR(addrWidth: Int, dataWidth: Int, regCount: Int, dmaConfig: DMAConfig) extends CSRBus[AXI4Lite](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala b/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala index 7071988..c333486 100644 --- a/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala +++ b/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus._ -import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class AXI4LiteWriter(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[AXI4Lite](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/AXI4Reader.scala b/src/main/scala/DMAController/Frontend/AXI4Reader.scala index 9b99edb..b455c25 100644 --- a/src/main/scala/DMAController/Frontend/AXI4Reader.scala +++ b/src/main/scala/DMAController/Frontend/AXI4Reader.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus._ -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig.DMAConfig +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig.DMAConfig class AXI4Reader(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[AXI4](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/AXI4Writer.scala b/src/main/scala/DMAController/Frontend/AXI4Writer.scala index 7c2efbb..4f21f82 100644 --- a/src/main/scala/DMAController/Frontend/AXI4Writer.scala +++ b/src/main/scala/DMAController/Frontend/AXI4Writer.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus._ -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class AXI4Writer(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[AXI4](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala b/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala index fdeb6ed..53283e4 100644 --- a/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala +++ b/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.AXIStream -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class AXIStreamMaster(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[AXIStream](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala b/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala index f158ff7..a0c79ac 100644 --- a/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala +++ b/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.AXIStream -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class AXIStreamSlave(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[AXIStream](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/BusBase.scala b/src/main/scala/DMAController/Frontend/BusBase.scala index 09fa14b..3cc5359 100644 --- a/src/main/scala/DMAController/Frontend/BusBase.scala +++ b/src/main/scala/DMAController/Frontend/BusBase.scala @@ -14,13 +14,12 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus._ -import DMAController.CSR.{CSR, CSRBusBundle} -import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle} +import DMAController.CSR.CSRBusBundle +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import DMAUtils.DMAModule import chisel3._ import chisel3.util._ -import DMAController.DMADriver -import DMAController.DMAConfig._ abstract class IOBus[+T](config: DMAConfig) extends DMAModule(config) { val io : Bundle { diff --git a/src/main/scala/DMAController/Frontend/WishboneCSR.scala b/src/main/scala/DMAController/Frontend/WishboneCSR.scala index 39d9251..b6ec7d3 100644 --- a/src/main/scala/DMAController/Frontend/WishboneCSR.scala +++ b/src/main/scala/DMAController/Frontend/WishboneCSR.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.WishboneSlave -import DMAController.CSR.{CSR, CSRBusBundle} -import DMAController.Worker.WorkerCSRWrapper +import DMAController.CSR.CSRBusBundle +import DMAController.DMAConfig._ import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class WishboneCSR(addrWidth: Int, dataWidth: Int, regCount: Int, dmaConfig: DMAConfig) extends CSRBus[WishboneSlave](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala index 4119311..1167c16 100644 --- a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala +++ b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.WishboneMaster -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class WishboneClassicPipelinedReader(val addrWidth: Int, val dataWidth: Int, config: DMAConfig) extends IOBus[WishboneMaster](config) { diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala index 16102b5..3eb7019 100644 --- a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala +++ b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.WishboneMaster -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class WishboneClassicPipelinedWriter(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala b/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala index 85c21c1..31cdc85 100644 --- a/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala +++ b/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.WishboneMaster -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class WishboneClassicReader(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) { diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala b/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala index 86f71f5..ae9f237 100644 --- a/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala +++ b/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala @@ -15,11 +15,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Frontend import DMAController.Bus.WishboneMaster -import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper} -import DMAController.CSR.CSR +import DMAController.DMAConfig._ +import DMAController.Worker.XferDescBundle import chisel3._ import chisel3.util._ -import DMAController.DMAConfig._ class WishboneClassicWriter(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) { diff --git a/src/main/scala/DMAController/Worker/AddressGenerator.scala b/src/main/scala/DMAController/Worker/AddressGenerator.scala index c0d8084..7a9b376 100644 --- a/src/main/scala/DMAController/Worker/AddressGenerator.scala +++ b/src/main/scala/DMAController/Worker/AddressGenerator.scala @@ -14,11 +14,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Worker +import DMAController.DMAConfig._ +import DMAUtils.DMAModule import chisel3._ import chisel3.util._ -import DMAUtils.DMAModule -import DMAController.DMAConfig._ -import DMAController.DMATop class AddressGenerator(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig) extends DMAModule(dmaConfig) { diff --git a/src/main/scala/DMAController/Worker/InterruptController.scala b/src/main/scala/DMAController/Worker/InterruptController.scala index 2c767b0..a7c319f 100644 --- a/src/main/scala/DMAController/Worker/InterruptController.scala +++ b/src/main/scala/DMAController/Worker/InterruptController.scala @@ -14,12 +14,13 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Worker -import DMAController.CSR.{CSRRegBundle, SetCSR, SimpleCSR} +import DMAController.CSR.CSRRegBundle +import DMAController.CSR.SetCSR +import DMAController.CSR.SimpleCSR +import DMAController.DMAConfig._ +import DMAUtils.DMAModule import chisel3._ import chisel3.util.Cat -import DMAUtils.DMAModule -import DMAController.DMADriver -import DMAController.DMAConfig._ class InterruptController(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) { val io = IO(new Bundle { diff --git a/src/main/scala/DMAController/Worker/TransferSplitter.scala b/src/main/scala/DMAController/Worker/TransferSplitter.scala index a3f8774..0394522 100644 --- a/src/main/scala/DMAController/Worker/TransferSplitter.scala +++ b/src/main/scala/DMAController/Worker/TransferSplitter.scala @@ -14,11 +14,10 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.Worker +import DMAController.DMAConfig._ +import DMAUtils.DMAModule import chisel3._ import chisel3.util._ -import DMAUtils.DMAModule -import DMAController.DMAConfig._ -import DMAController.DMADriver class TransferSplitter(val addressWidth: Int, val dataWidth: Int, val maxLength: Int, val canCrossBarrier: Boolean, dmaConfig: DMAConfig diff --git a/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala b/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala index 82aa4e3..8268b8d 100644 --- a/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala +++ b/src/main/scala/DMAController/Worker/WorkerCSRWrapper.scala @@ -50,8 +50,7 @@ class WorkerCSRWrapper(cfg: DMAConfig) extends DMAModule(cfg) { val control = Wire(UInt()) val clear = Wire(UInt()) - val envTag = System.getenv("TAG") - val tag = if (envTag.isEmpty()) "v0.0" else envTag + val tag = scala.sys.env.getOrElse("TAG", "v0.0") val version = RegInit(tag.filter(_.isDigit).toInt.U) val (in, csr, out) = cfg.getBusConfig() val encConfig = RegInit((in << 8 | csr << 4 | out).U(cfg.addrWidth.W)) diff --git a/src/main/scala/DMAUtils/DMAUtils.scala b/src/main/scala/DMAUtils/DMAUtils.scala index 5db8831..8b83344 100644 --- a/src/main/scala/DMAUtils/DMAUtils.scala +++ b/src/main/scala/DMAUtils/DMAUtils.scala @@ -1,10 +1,11 @@ package DMAUtils +import DMAController.DMAConfig._ import chisel3._ import chisel3.util._ import play.api.libs.json._ -import java.io.{FileNotFoundException, IOException} -import DMAController.DMAConfig._ + +import java.io.FileNotFoundException abstract class DMAModule(config: DMAConfig) extends Module { lazy val class_name = this.getClass.getSimpleName() @@ -117,7 +118,7 @@ object DMAQueue { q.io.enq.valid := enq.valid q.io.enq.bits := enq.bits enq.ready := q.io.enq.ready - TransitName(q.io.deq, q) + q.io.deq } } } diff --git a/src/test/scala/DMAController/Bfm/Axi4SlaveBfm.scala b/src/test/scala/DMAController/Bfm/Axi4SlaveBfm.scala index 305c77b..dc79558 100644 --- a/src/test/scala/DMAController/Bfm/Axi4SlaveBfm.scala +++ b/src/test/scala/DMAController/Bfm/Axi4SlaveBfm.scala @@ -101,7 +101,7 @@ extends Axi4Bfm { } } } - peekInputs + peekInputs() } } @@ -162,7 +162,7 @@ extends Axi4Bfm { } } } - peekInputs + peekInputs() } } diff --git a/src/test/scala/DMAController/Bfm/AxiLiteMasterBfm.scala b/src/test/scala/DMAController/Bfm/AxiLiteMasterBfm.scala index edfe0e0..44e1025 100644 --- a/src/test/scala/DMAController/Bfm/AxiLiteMasterBfm.scala +++ b/src/test/scala/DMAController/Bfm/AxiLiteMasterBfm.scala @@ -118,7 +118,7 @@ class AxiLiteMasterBfm(val axi: AXI4Lite, } } - peekInputs + peekInputs() } } @@ -193,7 +193,7 @@ class AxiLiteMasterBfm(val axi: AXI4Lite, } } - peekInputs + peekInputs() } } @@ -201,8 +201,8 @@ class AxiLiteMasterBfm(val axi: AXI4Lite, // queues class Cmd(val is_read: Boolean, val addr: BigInt, val wr_data: BigInt) class Resp(val success: Boolean, val rd_data: BigInt) - private var cmdList: ListBuffer[Cmd] = new ListBuffer() - private var respList: ListBuffer[Resp] = new ListBuffer() + private val cmdList: ListBuffer[Cmd] = new ListBuffer() + private val respList: ListBuffer[Resp] = new ListBuffer() // interfaces private val read_if = new ReadIf() diff --git a/src/test/scala/DMAController/Bfm/AxiStreamMasterBfm.scala b/src/test/scala/DMAController/Bfm/AxiStreamMasterBfm.scala index 795c046..2d4918e 100644 --- a/src/test/scala/DMAController/Bfm/AxiStreamMasterBfm.scala +++ b/src/test/scala/DMAController/Bfm/AxiStreamMasterBfm.scala @@ -28,7 +28,7 @@ class AxiStreamMasterBfm(val axi: AXIStream, val println: String => Unit) extends AxiStreamBfm { - private var txList: ListBuffer[Int] = new ListBuffer() + private val txList: ListBuffer[Int] = new ListBuffer() private object State extends Enumeration { type State = Value @@ -46,7 +46,7 @@ extends AxiStreamBfm { val buffer = file.Files.readAllBytes(path) val bb = ByteBuffer.wrap(buffer) //bb.order(ByteOrder.nativeOrder) - var buf = new Array[Int](buffer.length/4) + val buf = new Array[Int](buffer.length/4) bb.asIntBuffer.get(buf) for(i <- 0 until buf.length) { txList += buf(i) @@ -79,15 +79,15 @@ extends AxiStreamBfm { if(txList.nonEmpty) { poke(axi.tvalid, 1) state = State.WriteData - putData - updateTlast + putData() + updateTlast() } } case State.WriteData => { if(tready != 0) { if(txList.nonEmpty) { - putData - updateTlast + putData() + updateTlast() if(wordCnt == packetLen) { wordCnt = 0 } else { @@ -100,6 +100,6 @@ extends AxiStreamBfm { } } } - peekInputs + peekInputs() } } diff --git a/src/test/scala/DMAController/Bfm/AxiStreamSlaveBfm.scala b/src/test/scala/DMAController/Bfm/AxiStreamSlaveBfm.scala index 32d1298..73176b2 100644 --- a/src/test/scala/DMAController/Bfm/AxiStreamSlaveBfm.scala +++ b/src/test/scala/DMAController/Bfm/AxiStreamSlaveBfm.scala @@ -25,7 +25,7 @@ class AxiStreamSlaveBfm(val axi: AXIStream, val println: String => Unit) extends AxiStreamBfm { - private var rxList: ListBuffer[BigInt] = new ListBuffer() + private val rxList: ListBuffer[BigInt] = new ListBuffer() private object State extends Enumeration { type State = Value @@ -58,7 +58,7 @@ extends AxiStreamBfm { } } } - peekInputs + peekInputs() } def loadFromFile(filename: String): Unit = { diff --git a/src/test/scala/DMAController/ComponentSpec.scala b/src/test/scala/DMAController/ComponentSpec.scala index 58a152f..813ed35 100644 --- a/src/test/scala/DMAController/ComponentSpec.scala +++ b/src/test/scala/DMAController/ComponentSpec.scala @@ -16,17 +16,16 @@ package DMAController import DMAController.Frontend._ import DMAController.Worker._ -import org.scalatest.{FlatSpec, Matchers} import chisel3._ import chiseltest._ import chiseltest.iotesters._ -import org.scalatest.freespec.AnyFreeSpec import org.scalatest.flatspec.AnyFlatSpec import DMAController.DMAConfig._ class ComponentSpec extends AnyFlatSpec with ChiselScalatestTester { val cfg = new DMAConfig("AXI_AXIL_AXI") - val testAnnotations = Seq(WriteVcdAnnotation) + // val testAnnotations = Seq(WriteVcdAnnotation) + val testAnnotations = Seq(WriteVcdAnnotation, VerilatorBackendAnnotation) def testFastVDMAComponent[T <: Module]( dutGen: => T, diff --git a/src/test/scala/DMAController/ControllerSpec.scala b/src/test/scala/DMAController/ControllerSpec.scala index 7eeda4e..770744e 100644 --- a/src/test/scala/DMAController/ControllerSpec.scala +++ b/src/test/scala/DMAController/ControllerSpec.scala @@ -10,7 +10,7 @@ See the License for the specific language governing permissions and limitations under the License. SPDX-License-Identifier: Apache-2.0 -*/ + */ package DMAController @@ -24,7 +24,8 @@ class ControllerSpec extends AnyFlatSpec with ChiselScalatestTester { val dmaConfigMM2MM = new DMAConfig("AXI_AXIL_AXI") it should "perform 2D MM2MM transfer with stride mem to mem" in { test(new DMATop(dmaConfigMM2MM)) - .withAnnotations(Seq(WriteVcdAnnotation)) + // .withAnnotations(Seq(WriteVcdAnnotation)) + .withAnnotations(Seq(VerilatorBackendAnnotation)) .runPeekPoke(dut => new ImageTransfer(dut, new DMAFullMem(dut), dmaConfigMM2MM) ) @@ -33,7 +34,8 @@ class ControllerSpec extends AnyFlatSpec with ChiselScalatestTester { val dmaConfigS2MM = new DMAConfig("AXIS_AXIL_AXI") it should "perform 2D S2MM transfer with stride stream to mem" in { test(new DMATop(dmaConfigS2MM)) - .withAnnotations(Seq(WriteVcdAnnotation)) + // .withAnnotations(Seq(WriteVcdAnnotation)) + .withAnnotations(Seq(VerilatorBackendAnnotation)) .runPeekPoke(dut => new ImageTransfer(dut, new DMAFullStream(dut), dmaConfigS2MM) ) diff --git a/src/test/scala/DMAController/DMAFull.scala b/src/test/scala/DMAController/DMAFull.scala index ba75641..bc465cb 100644 --- a/src/test/scala/DMAController/DMAFull.scala +++ b/src/test/scala/DMAController/DMAFull.scala @@ -14,8 +14,8 @@ SPDX-License-Identifier: Apache-2.0 package DMAController -import DMAController.Bfm.{ControlBfm, IOBfm} -import DMAController.Worker.{InterruptBundle, SyncBundle} +import DMAController.Bfm.ControlBfm +import DMAController.Bfm.IOBfm import chiseltest.iotesters.PeekPokeTester abstract class DMAFull(dut: DMATop) extends PeekPokeTester(dut){ diff --git a/src/test/scala/DMAController/ImageTransfer.scala b/src/test/scala/DMAController/ImageTransfer.scala index be2a6e9..f11c33c 100644 --- a/src/test/scala/DMAController/ImageTransfer.scala +++ b/src/test/scala/DMAController/ImageTransfer.scala @@ -10,28 +10,28 @@ See the License for the specific language governing permissions and limitations under the License. SPDX-License-Identifier: Apache-2.0 -*/ + */ package DMAController import scala.reflect.runtime.universe._ import DMAController.Bfm.ChiselBfm -import DMAController.Worker.{InterruptBundle, SyncBundle} import chiseltest.iotesters.PeekPokeTester -import chisel3.Bits +import chisel3._ import DMAController.DMAConfig._ -class ImageTransfer(dut: DMATop, dmaFull: DMAFull, dmaConfig: DMAConfig) extends PeekPokeTester(dut){ +class ImageTransfer(dut: DMATop, dmaFull: DMAFull, dmaConfig: DMAConfig) + extends PeekPokeTester(dut) { val width = 256 val height = 256 val min = 0 val max = width * height * 2 var cnt: Int = 0 - def waitRange(data: Bits, exp: Int, min: Int, max: Int) : Unit = { + def waitRange(data: Bits, exp: Int, min: Int, max: Int): Unit = { var cnt = 0 - while(peek(data) != exp && cnt < max){ + while (peek(data) != exp && cnt < max) { step(1) cnt += 1 } @@ -46,15 +46,15 @@ class ImageTransfer(dut: DMATop, dmaFull: DMAFull, dmaConfig: DMAConfig) extends def bfms = members.filter(_.typeSignature <:< typeOf[ChiselBfm]) def stepSingle(): Unit = { - for(bfm <- bfms){ + for (bfm <- bfms) { cls.reflectField(bfm.asTerm).get.asInstanceOf[ChiselBfm].update(cnt) } super.step(1) } override def step(n: Int): Unit = { - for(_ <- 0 until n) { - stepSingle + for (_ <- 0 until n) { + stepSingle() } } @@ -65,21 +65,21 @@ class ImageTransfer(dut: DMATop, dmaFull: DMAFull, dmaConfig: DMAConfig) extends reader.loadFromFile("./img0.rgba") writer.loadFromFile("./img1.rgba") - control.writePush(DMAConfig.Register.ReaderStartAddr, 0) - control.writePush(DMAConfig.Register.ReaderLineLen, width) - control.writePush(DMAConfig.Register.ReaderLineCnt, height) - control.writePush(DMAConfig.Register.ReaderStride, 0) + control.writePush(Register.ReaderStartAddr, 0) + control.writePush(Register.ReaderLineLen, width) + control.writePush(Register.ReaderLineCnt, height) + control.writePush(Register.ReaderStride, 0) - control.writePush(DMAConfig.Register.WriterStartAddr, height * width * 4 + width * 2) - control.writePush(DMAConfig.Register.WriterLineLen, width) - control.writePush(DMAConfig.Register.WriterLineCnt, height) - control.writePush(DMAConfig.Register.WriterStride, width) + control.writePush(Register.WriterStartAddr, height * width * 4 + width * 2) + control.writePush(Register.WriterLineLen, width) + control.writePush(Register.WriterLineCnt, height) + control.writePush(Register.WriterStride, width) step(100) - control.writePush(DMAConfig.Register.InterruptMask, 3) + control.writePush(Register.InterruptMask, 3) - control.writePush(DMAConfig.Register.Ctrl, 0xf) + control.writePush(Register.Ctrl, 0xf) waitRange(dut.io.irq.writerDone, 1, min, max) diff --git a/src/test/scala/DMAController/TestUtil.scala b/src/test/scala/DMAController/TestUtil.scala index daa8347..47cf358 100644 --- a/src/test/scala/DMAController/TestUtil.scala +++ b/src/test/scala/DMAController/TestUtil.scala @@ -14,7 +14,6 @@ SPDX-License-Identifier: Apache-2.0 package DMAController.TestUtil -import chisel3.iotesters._ object WaitRange { def waitRange(init: Int, max: Int, cond: () => Boolean): Boolean = {