From 0c96fa87b9ea758aee3bb1e204f8c80ce02a2da5 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Mon, 19 May 2025 16:46:02 +0200 Subject: [PATCH 1/3] fix: do not set ZEPHYR_SDK_INSTALL_DIR in the workflow The SDK is now automatically chosen, installed and detected by the scripts. This hardcoded path was causing issues with readelf not being found anymore. Also, this was hiding the fact that the environment was being activated too late in the workflow, requiring the user to manually source the venv/bin/activate script or have the ZEPHYR_SDK_INSTALL_DIR variable in the environment. --- .github/workflows/package_core.yml | 1 - extra/build.sh | 8 ++++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/workflows/package_core.yml b/.github/workflows/package_core.yml index d8e7ed268..2fbdbf6e7 100644 --- a/.github/workflows/package_core.yml +++ b/.github/workflows/package_core.yml @@ -10,7 +10,6 @@ jobs: name: Build and package core runs-on: ubuntu-latest env: - ZEPHYR_SDK_INSTALL_DIR: /opt/zephyr-sdk-0.16.8 CCACHE_IGNOREOPTIONS: -specs=* outputs: CORE_TAG: ${{ env.CORE_TAG }} diff --git a/extra/build.sh b/extra/build.sh index 358991505..6d7d63f12 100755 --- a/extra/build.sh +++ b/extra/build.sh @@ -2,6 +2,10 @@ set -e +source venv/bin/activate + +ZEPHYR_BASE=$(west topdir)/zephyr + if [ x$ZEPHYR_SDK_INSTALL_DIR == x"" ]; then SDK_PATH=$(west sdk list | grep path | tail -n 1 | cut -d ':' -f 2 | tr -d ' ') if [ x$SDK_PATH == x ]; then @@ -50,10 +54,6 @@ fi echo echo "Build target: $target $args" -source venv/bin/activate - -ZEPHYR_BASE=$(west topdir)/zephyr - # Get the variant name (NORMALIZED_BOARD_TARGET in Zephyr) variant=$(extra/get_variant_name.sh $target) From 69ae9ba143fc4d8c26bee6b9ba42b699d6deb8c8 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Tue, 20 May 2025 11:20:17 +0200 Subject: [PATCH 2/3] fix: frdm_rw612_rw612: fix partition size The sketch partition size was slightly overflowing the original "image-1" partition, causing corruption on the storage partition. --- variants/frdm_rw612_rw612/frdm_rw612_rw612.overlay | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/variants/frdm_rw612_rw612/frdm_rw612_rw612.overlay b/variants/frdm_rw612_rw612/frdm_rw612_rw612.overlay index e30d83f4a..f1cea15de 100644 --- a/variants/frdm_rw612_rw612/frdm_rw612_rw612.overlay +++ b/variants/frdm_rw612_rw612/frdm_rw612_rw612.overlay @@ -10,8 +10,7 @@ w25q512jvfiq: w25q512jvfiq@0 { partitions { user_sketch: partition@323000 { - label = "image-1"; - reg = <0x00323000 DT_SIZE_M(3)>; + reg = <0x00323000 (DT_SIZE_M(3) - 0x3000)>; }; }; }; From 482ee0b81639bf528279015316423000712a1790 Mon Sep 17 00:00:00 2001 From: Luca Burelli Date: Mon, 19 May 2025 16:37:34 +0200 Subject: [PATCH 3/3] zephyr: update to zephyr-arduino-20250520 - add missing cmsis_6 submodule - fix DCMI overlays - fix merged shield name --- boards.txt | 2 +- loader/llext_exports.c | 1 - .../arduino_giga_r1_stm32h747xx_m7.overlay | 12 +++++------- ...arduino_portenta_h7_stm32h747xx_m7.overlay | 19 ++++++++----------- west.yml | 5 ++++- 5 files changed, 18 insertions(+), 21 deletions(-) diff --git a/boards.txt b/boards.txt index 1a156c11e..9e16f5bcc 100644 --- a/boards.txt +++ b/boards.txt @@ -13,7 +13,7 @@ giga.menu.debug.false.postbuild_debug= giga.menu.debug.true.postbuild_debug=-debug giga.build.zephyr_target=arduino_giga_r1//m7 -giga.build.zephyr_args=--shield giga_display_shield +giga.build.zephyr_args=--shield arduino_giga_display_shield giga.build.variant=arduino_giga_r1_stm32h747xx_m7 giga.build.mcu=cortex-m7 giga.build.fpu=-mfpu=fpv5-d16 diff --git a/loader/llext_exports.c b/loader/llext_exports.c index eaadb76fe..a0dc10df5 100644 --- a/loader/llext_exports.c +++ b/loader/llext_exports.c @@ -112,7 +112,6 @@ FORCE_EXPORT_SYM(net_mgmt_NET_REQUEST_WIFI_AP_ENABLE); #if defined(CONFIG_BT) FORCE_EXPORT_SYM(bt_enable_raw); -FORCE_EXPORT_SYM(bt_hci_raw_set_mode); FORCE_EXPORT_SYM(bt_send); FORCE_EXPORT_SYM(bt_buf_get_tx); FORCE_EXPORT_SYM(net_buf_simple_pull); diff --git a/variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay b/variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay index 755825123..f397b784a 100644 --- a/variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay +++ b/variants/arduino_giga_r1_stm32h747xx_m7/arduino_giga_r1_stm32h747xx_m7.overlay @@ -148,24 +148,22 @@ &dcmi { status = "okay"; - sensor = <&gc2145>; /* ext-sdram = <&sdram1>; */ pinctrl-0 = <&dcmi_hsync_ph8 &dcmi_pixclk_pa6 &dcmi_vsync_pi5 &dcmi_d0_ph9 &dcmi_d1_ph10 &dcmi_d2_ph11 &dcmi_d3_pg11 &dcmi_d4_ph14 &dcmi_d5_pi4 &dcmi_d6_pi6 &dcmi_d7_pi7>; pinctrl-names = "default"; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - capture-rate = <1>; dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_32BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; port { dcmi_ep_in: endpoint { - remote-endpoint = <&gc2145_ep_out>; + remote-endpoint-label = "gc2145_ep_out"; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; }; }; }; diff --git a/variants/arduino_portenta_h7_stm32h747xx_m7/arduino_portenta_h7_stm32h747xx_m7.overlay b/variants/arduino_portenta_h7_stm32h747xx_m7/arduino_portenta_h7_stm32h747xx_m7.overlay index ba7e16841..247455511 100644 --- a/variants/arduino_portenta_h7_stm32h747xx_m7/arduino_portenta_h7_stm32h747xx_m7.overlay +++ b/variants/arduino_portenta_h7_stm32h747xx_m7/arduino_portenta_h7_stm32h747xx_m7.overlay @@ -27,7 +27,7 @@ port { gc2145_ep_out: endpoint { - remote-endpoint = <&dcmi_ep_in>; + remote-endpoint-label = "dcmi_ep_in"; }; }; }; @@ -41,7 +41,7 @@ port { ov7670_ep_out: endpoint { - remote-endpoint = <&dcmi_ep_in>; + remote-endpoint-label = "dcmi_ep_in"; }; }; }; @@ -132,26 +132,23 @@ &dcmi { status = "okay"; - sensor = <&gc2145>; - /* sensor = <&ov7670>; */ /* ext-sdram = <&sdram1>; */ pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pi5 &dcmi_d0_ph9 &dcmi_d1_ph10 &dcmi_d2_ph11 &dcmi_d3_ph12 &dcmi_d4_ph14 &dcmi_d5_pi4 &dcmi_d6_pi6 &dcmi_d7_pi7>; pinctrl-names = "default"; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - pixelclk-active = <0>; - capture-rate = <1>; dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | STM32_DMA_MEM_INC | STM32_DMA_PERIPH_32BITS | STM32_DMA_MEM_32BITS | STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_FULL>; //FULL for 7670, default FIFO_1_4 port { dcmi_ep_in: endpoint { - remote-endpoint = <&gc2145_ep_out>; - //remote-endpoint = <&ov7670_ep_out>; + remote-endpoint-label = "gc2145_ep_out"; + // remote-endpoint-label = "ov7670_ep_out"; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; }; }; }; diff --git a/west.yml b/west.yml index dba76fda4..163deb046 100644 --- a/west.yml +++ b/west.yml @@ -15,14 +15,17 @@ manifest: url-base: https://github.com/arduino - name: facchinm url-base: https://github.com/facchinm + - name: pillo79 + url-base: https://github.com/pillo79 projects: - name: zephyr remote: arduino - revision: arduino_core_merge_post_4.1 + revision: zephyr-arduino-20250520 import: name-allowlist: - cmsis + - cmsis_6 - hal_nordic - hal_ti - hal_ambiq