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hathachhathach
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Merge pull request hathach#2672 from tinic/master
Add support for STM32U535xx/STM32U545xx
2 parents edf1ef6 + a6d3e2a commit 007a8bd

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12 files changed

+220
-17
lines changed

12 files changed

+220
-17
lines changed

‎hw/bsp/stm32u5/boards/stm32u545nucleo/board.cmake

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set(MCU_VARIANT stm32u545xx)
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set(JLINK_DEVICE stm32u545re)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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STM32U545xx
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)
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endfunction()

‎hw/bsp/stm32u5/boards/stm32u545nucleo/board.h

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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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// LED GREEN
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#define LED_PORT GPIOA
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#define LED_PIN GPIO_PIN_5
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#define LED_STATE_ON 1
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// BUTTON
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#define BUTTON_PORT GPIOC
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#define BUTTON_PIN GPIO_PIN_13
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#define BUTTON_STATE_ACTIVE 1
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// UART Enable for STLink VCOM
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#define UART_DEV LPUART1
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#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
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#define UART_GPIO_PORT GPIOA
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#define UART_GPIO_AF GPIO_AF8_LPUART1
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#define UART_TX_PIN GPIO_PIN_2
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#define UART_RX_PIN GPIO_PIN_3
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//--------------------------------------------------------------------+
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// RCC Clock
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//--------------------------------------------------------------------+
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static void SystemClock_Config(void) {
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RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
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RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
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/* Enable Power Clock */
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__HAL_RCC_PWR_CLK_ENABLE();
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = 2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 1;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
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RCC_OscInitStruct.PLL.PLLFRACN = 0;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48;
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PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType =
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RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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}
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static void SystemPower_Config(void) {
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */

‎hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk

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CFLAGS += \
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-DSTM32U545xx \
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# All source paths should be relative to the top level.
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LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld
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SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s
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MCU_VARIANT = stm32u545xx
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# For flash-jlink target
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JLINK_DEVICE = stm32u545re

‎hw/bsp/stm32u5/boards/stm32u575eval/board.mk

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@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
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SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
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MCU_VARIANT = stm32u575xx
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# For flash-jlink target
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JLINK_DEVICE = stm32u575ai

‎hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk

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@@ -6,5 +6,6 @@ LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld
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SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s
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MCU_VARIANT = stm32u575xx
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# For flash-jlink target
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JLINK_DEVICE = stm32u575zi

‎hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk

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@@ -7,5 +7,6 @@ LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld
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SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s
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MCU_VARIANT = stm32u5a5xx
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# For flash-jlink target
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JLINK_DEVICE = stm32u575zi

‎hw/bsp/stm32u5/family.c

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@@ -72,7 +72,9 @@ void board_init(void) {
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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#ifdef GPIOF
7576
__HAL_RCC_GPIOF_CLK_ENABLE();
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#endif
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_ENABLE();
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@@ -140,6 +142,17 @@ void board_init(void) {
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GPIO_InitStruct.Alternate = GPIO_AF10_USB;
141143
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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145+
#ifdef USB_DRD_FS
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// STM32U535/STM32U545
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/* Enable USB power on Pwrctrl CR2 register */
149+
HAL_PWREx_EnableVddUSB();
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/* USB clock enable */
152+
__HAL_RCC_USB_FS_CLK_ENABLE();
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#endif
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143156
#ifdef USB_OTG_FS
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#if CFG_TUSB_OS == OPT_OS_FREERTOS
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// If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher )
@@ -170,7 +183,9 @@ void board_init(void) {
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/* USB clock enable */
171184
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
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173-
#else
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#endif
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#ifdef USB_OTG_HS
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// STM59x/Ax/Fx/Gx only have 1 USB HS port
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176191
#if CFG_TUSB_OS == OPT_OS_FREERTOS

‎hw/bsp/stm32u5/family.cmake

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@@ -102,10 +102,16 @@ function(family_configure_example TARGET RTOS)
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103103
# Add TinyUSB target and port source
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family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS})
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target_sources(${TARGET}-tinyusb PUBLIC
106-
${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
107-
#${TOP}/src/portable/st/typec/typec_stm32.c
108-
)
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if ((${MCU_VARIANT} STREQUAL "stm32u535xx") OR (${MCU_VARIANT} STREQUAL "stm32u545xx"))
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
108+
)
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else ()
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
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#${TOP}/src/portable/st/typec/typec_stm32.c
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)
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endif ()
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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111117
# Link dependencies

‎hw/bsp/stm32u5/family.mk

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@@ -27,18 +27,28 @@ LDFLAGS_GCC += \
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--specs=nosys.specs --specs=nano.specs
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SRC_C += \
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src/portable/synopsys/dwc2/dcd_dwc2.c \
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$(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \
3433
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \
35-
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_icache.c \
3635
$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \
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$(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c
4140

41+
ifeq ($(MCU_VARIANT),stm32u545xx)
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SRC_C += \
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src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
44+
else ifeq ($(MCU_VARIANT),stm32u535xx)
45+
SRC_C += \
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src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
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else
48+
SRC_C += \
49+
src/portable/synopsys/dwc2/dcd_dwc2.c
50+
endif
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INC += \
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$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
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$(TOP)/$(ST_CMSIS)/Include \

‎src/common/tusb_mcu.h

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#define TUP_DCD_ENDPOINT_MAX 8
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273273
#elif TU_CHECK_MCU(OPT_MCU_STM32U5)
274-
#define TUP_USBIP_DWC2
275-
#define TUP_USBIP_DWC2_STM32
274+
#if defined (STM32U535xx) || defined (STM32U545xx)
275+
#define TUP_USBIP_FSDEV
276+
#define TUP_USBIP_FSDEV_STM32
277+
#define TUP_DCD_ENDPOINT_MAX 8
276278

277-
// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
278-
#if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
279-
defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
280-
#define TUP_DCD_ENDPOINT_MAX 9
281-
#define TUP_RHPORT_HIGHSPEED 1
282-
#define TUP_USBIP_DWC2_TEST_MODE
283279
#else
284-
#define TUP_DCD_ENDPOINT_MAX 6
280+
#define TUP_USBIP_DWC2
281+
#define TUP_USBIP_DWC2_STM32
282+
283+
// U59x/5Ax/5Fx/5Gx are highspeed with built-in HS PHY
284+
#if defined(STM32U595xx) || defined(STM32U599xx) || defined(STM32U5A5xx) || defined(STM32U5A9xx) || \
285+
defined(STM32U5F7xx) || defined(STM32U5F9xx) || defined(STM32U5G7xx) || defined(STM32U5G9xx)
286+
#define TUP_DCD_ENDPOINT_MAX 9
287+
#define TUP_RHPORT_HIGHSPEED 1
288+
#define TUP_USBIP_DWC2_TEST_MODE
289+
#else
290+
#define TUP_DCD_ENDPOINT_MAX 6
291+
#endif
285292
#endif
286293

287294
#elif TU_CHECK_MCU(OPT_MCU_STM32L5)

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