Merge branch 'enable-vpclmulqdq-on-rust-1.89'

Author: onethumb

.github/workflows/tests.yml

@@ -13,6 +13,7 @@ jobs:
         os: [ubuntu-latest, ubuntu-22.04-arm, ubuntu-24.04-arm, macos-latest]
         rust-toolchain:
           - "1.81" # minimum for this crate
+          - "1.89" # when VPCLMULQDQ was stabilized
           - "stable"
           - "nightly"
     runs-on: ${{ matrix.os }}
@@ -44,6 +45,7 @@ jobs:
         target: [i586-unknown-linux-gnu, i686-unknown-linux-gnu]
         rust-toolchain:
           - "1.81" # minimum for this crate
+          - "1.89" # when VPCLMULQDQ was stabilized
           - "stable"
           - "nightly"
     steps:
@@ -69,6 +71,7 @@ jobs:
         target: [powerpc-unknown-linux-gnu, powerpc64-unknown-linux-gnu]
         rust-toolchain:
           - "1.81" # minimum for this crate
+          - "1.89" # when VPCLMULQDQ was stabilized
           - "stable"
           - "nightly"
     steps:

CHANGELOG.md

@@ -1,6 +1,7 @@
 # Changes for crc-fast-rust
 
 ## [1.4.0](https://github.com/awesomized/crc-fast-rust/releases/tag/1.4.0) - 2025-08-08
+* [Enable VPCLMULQDQ support on Rust 1.89+](https://github.com/awesomized/crc-fast-rust/pull/10)
 * [Support custom CRC parameters](https://github.com/awesomized/crc-fast-rust/pull/11)
 * [Add checksum command-line utility](https://github.com/awesomized/crc-fast-rust/pull/12)
 * [Remove bindgen](https://github.com/awesomized/crc-fast-rust/pull/13)

Cargo.lock

@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 keywords = ["crc", "checksum", "simd", "accelerated", "fast"]
 categories = ["algorithms", "encoding", "hardware-support"]
 repository = "https://github.com/awesomized/crc-fast-rust"
-description = "Fast, hardware-accelerated CRC-32 and CRC-64 checksum calculation using SIMD"
+description = "World's fastest generic CRC32 and CRC64 calculator using SIMD. Supplies a C-compatible shared library for use in other languages."
 readme = "README.md"
 
 # 1.69.0 added VPCLMULQDQ x86 detection support, 1.70.0 added LLVM 16 which supports PMULL2 on Aarch64
@@ -24,6 +24,7 @@ digest = {  version = "0.10", features = ["alloc"] }
 rand = "0.9"
 libc = "0.2"
 regex = "1.11"
+rustversion = "1.0"
 
 [dev-dependencies]
 criterion = "0.7"
@@ -43,10 +44,8 @@ harness = false
 [features]
 alloc = []
 
-# enable experimental VPCLMULQDQ support, which landed in Rust 1.89.0-nightly, will deprecate after 1.89.0 is stable
-vpclmulqdq = []
-
-# the features below aren't in use, are deprecated, and will be removed in the next MAJOR version
+# the features below are deprecated, aren't in use, and will be removed in the next MAJOR version (v2)
+vpclmulqdq = [] # deprecated, VPCLMULQDQ stabilized in Rust 1.89.0
 optimize_crc32_auto = [] # deprecated
 optimize_crc32_neon_eor3_v9s3x2e_s3 = [] # deprecated
 optimize_crc32_neon_v12e_v1 = [] # deprecated

Cargo.toml

@@ -5,22 +5,22 @@
 [![Latest Version](https://img.shields.io/crates/v/crc-fast.svg)](https://crates.io/crates/crc-fast)
 [![Documentation](https://img.shields.io/badge/api-rustdoc-blue.svg)](https://docs.rs/crc-fast)
 
-Fast, hardware-accelerated CRC calculation for
-[all known CRC-32 and CRC-64 variants](https://reveng.sourceforge.io/crc-catalogue/all.htm) using SIMD intrinsics,
+World's fastest generic CRC calculator for
+[all known CRC-32 and CRC-64 variants](https://reveng.sourceforge.io/crc-catalogue/all.htm), as well as bring-your-own
+custom parameters, using SIMD intrinsics,
 which can exceed [100GiB/s](#performance) on modern systems.
 
-Supports acceleration on `aarch64`, `x86_64`, and `x86` architectures, plus has a safe non-accelerated table-based 
+Supports acceleration on `aarch64`, `x86_64`, and `x86` architectures, plus has a safe non-accelerated table-based
 software fallback for others.
 
 The [crc crate](https://crates.io/crates/crc) is ~0.5GiB/s by default, so this is
-[up to >220X faster](#tldr-just-tell-me-how-to-turn-it-up-to-11-), and even the most conservative baseline settings
-are >27X.
+[up to >220X faster](#tldr-just-tell-me-how-to-turn-it-up-to-11-).
 
 This is unique, not just because of the performance, but also because I couldn't find a single generic SIMD-accelerated
 implementation (in any language) which worked for _all_ known variants, using the
 [Rocksoft model](http://www.ross.net/crc/download/crc_v3.txt), especially the "non-reflected" variants.
 
-So I wrote one.
+So I wrote one. :)
 
 ## Other languages
 
@@ -144,7 +144,8 @@ assert_eq!(checksum.unwrap(), 0xcbf43926);
 
 ## Custom CRC Parameters
 
-For cases where you need to use CRC variants not included in the predefined algorithms, you can define custom CRC parameters and use the `*_with_params` functions.
+For cases where you need to use CRC variants not included in the predefined algorithms, you can define custom CRC
+parameters and use the `*_with_params` functions.
 
 ### Digest with custom parameters
 

README.md

@@ -22,8 +22,8 @@ use aarch64::AArch64Ops;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 use x86::X86Ops;
 
-//#[rustversion::since(1.89)]
-#[cfg(all(target_arch = "x86_64", feature = "vpclmulqdq"))]
+#[rustversion::since(1.89)]
+#[cfg(target_arch = "x86_64")]
 use vpclmulqdq::Vpclmulqdq512Ops;
 
 mod aarch64;
@@ -49,28 +49,25 @@ pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64
     }
 }
 
-//#[rustversion::before(1.89)]
+#[rustversion::before(1.89)]
 #[inline]
-#[cfg(all(
-    not(feature = "vpclmulqdq"),
-    any(target_arch = "x86", target_arch = "x86_64")
-))]
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 #[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
 pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
     update_x86_sse(state, bytes, params)
 }
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[inline]
-#[cfg(all(feature = "vpclmulqdq", target_arch = "x86"))]
+#[cfg(target_arch = "x86")]
 #[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
 pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
     update_x86_sse(state, bytes, params)
 }
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[inline]
-#[cfg(all(feature = "vpclmulqdq", target_arch = "x86_64"))]
+#[cfg(target_arch = "x86_64")]
 #[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
 pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
     use std::arch::is_x86_feature_detected;
@@ -117,8 +114,7 @@ unsafe fn update_x86_sse(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
     }
 }
 
-//#[rustversion::before(1.89)]
-#[cfg(not(feature = "vpclmulqdq"))]
+#[rustversion::before(1.89)]
 pub fn get_target() -> String {
     #[cfg(target_arch = "aarch64")]
     {
@@ -137,8 +133,7 @@ pub fn get_target() -> String {
     return "software-fallback-tables".to_string();
 }
 
-//#[rustversion::since(1.89)]
-#[cfg(feature = "vpclmulqdq")]
+#[rustversion::since(1.89)]
 pub fn get_target() -> String {
     #[cfg(target_arch = "aarch64")]
     {

src/arch/mod.rs

@@ -4,33 +4,33 @@
 //!
 //! It performs folding using 4 x ZMM registers of 512-bits each.
 
-#![cfg(all(target_arch = "x86_64", feature = "vpclmulqdq"))]
+#![cfg(target_arch = "x86_64")]
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use crate::arch::x86::X86Ops;
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use crate::enums::Reflector;
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use crate::structs::CrcState;
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use crate::traits::{ArchOps, EnhancedCrcWidth};
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use std::arch::x86_64::*;
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 use std::ops::BitXor;
 
 /// Implements the ArchOps trait using 512-bit AVX-512 and VPCLMULQDQ instructions at 512 bits.
 /// Delegates to X86Ops for standard 128-bit operations
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[derive(Debug, Copy, Clone)]
 pub struct Vpclmulqdq512Ops(X86Ops);
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 impl Vpclmulqdq512Ops {
     #[inline(always)]
     pub fn new() -> Self {
@@ -39,11 +39,11 @@ impl Vpclmulqdq512Ops {
 }
 
 // Wrapper for __m512i to make it easier to work with
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[derive(Debug, Copy, Clone)]
 struct Simd512(__m512i);
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 impl Simd512 {
     #[inline]
     #[target_feature(enable = "avx512f")]
@@ -112,7 +112,7 @@ impl Simd512 {
     }
 }
 
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 impl Vpclmulqdq512Ops {
     /// Process aligned blocks using VPCLMULQDQ with 4 x 512-bit registers
     ///
@@ -339,15 +339,15 @@ impl Vpclmulqdq512Ops {
 }
 
 // 512-bit version of the Reflector
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[derive(Clone, Copy)]
 enum Reflector512 {
     NoReflector,
     ForwardReflector { smask: Simd512 },
 }
 
 // Function to create the appropriate reflector based on CRC parameters
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[inline(always)]
 unsafe fn create_reflector512(reflected: bool) -> Reflector512 {
     if reflected {
@@ -369,7 +369,7 @@ unsafe fn create_reflector512(reflected: bool) -> Reflector512 {
 }
 
 // Function to apply reflection to a 512-bit vector
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[inline(always)]
 unsafe fn reflect_bytes512(reflector: &Reflector512, data: Simd512) -> Simd512 {
     match reflector {
@@ -379,12 +379,12 @@ unsafe fn reflect_bytes512(reflector: &Reflector512, data: Simd512) -> Simd512 {
 }
 
 // pre-compute the reverse indices for 512-bit shuffling
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 static REVERSE_INDICES_512: __m512i =
     unsafe { std::mem::transmute([7u64, 6u64, 5u64, 4u64, 3u64, 2u64, 1u64, 0u64]) };
 
 // Implement a 512-bit byte shuffle function
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 #[inline]
 #[target_feature(enable = "avx512f,avx512bw")]
 unsafe fn shuffle_bytes512(data: Simd512, mask: Simd512) -> Simd512 {
@@ -396,7 +396,7 @@ unsafe fn shuffle_bytes512(data: Simd512, mask: Simd512) -> Simd512 {
 }
 
 // Delegate all ArchOps methods to the inner X86Ops instance
-//#[rustversion::since(1.89)]
+#[rustversion::since(1.89)]
 impl ArchOps for Vpclmulqdq512Ops {
     type Vector = __m128i;
 

src/arch/vpclmulqdq.rs

@@ -227,9 +227,8 @@ impl ArchOps for X86Ops {
         _mm_clmulepi64_si128(a, b, 0x11)
     }
 
-    //#[rustversion::since(1.89)]
+    #[rustversion::since(1.89)]
     #[inline]
-    #[cfg(feature = "vpclmulqdq")]
     #[target_feature(enable = "avx512f,avx512vl")]
     unsafe fn xor3_vectors(
         &self,
@@ -244,9 +243,8 @@ impl ArchOps for X86Ops {
         self.xor3_vectors_sse(a, b, c)
     }
 
-    //#[rustversion::before(1.89)]
+    #[rustversion::before(1.89)]
     #[inline]
-    #[cfg(not(feature = "vpclmulqdq"))]
     #[target_feature(enable = "sse4.1")]
     unsafe fn xor3_vectors(
         &self,
@@ -321,9 +319,8 @@ impl X86Ops {
         }
     }
 
-    //#[rustversion::since(1.89)]
+    #[rustversion::since(1.89)]
     #[inline]
-    #[cfg(feature = "vpclmulqdq")]
     #[target_feature(enable = "avx512f,avx512vl")]
     unsafe fn xor3_vectors_avx512(&self, a: __m128i, b: __m128i, c: __m128i) -> __m128i {
         _mm_ternarylogic_epi64(