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onethumbonethumb
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Simplify target_feature(enable)
Elminate redundant features that are already implictly enabled. https://doc.rust-lang.org/reference/attributes/codegen.html#r-attributes.codegen.target_feature.x86 https://doc.rust-lang.org/reference/attributes/codegen.html#r-attributes.codegen.target_feature.aarch64
1 parent 3f3c274 commit aa30cbc

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10 files changed

+118
-120
lines changed

10 files changed

+118
-120
lines changed

‎src/algorithm.rs‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,9 @@ use crate::{crc32, crc64};
2525
#[inline]
2626
#[cfg_attr(
2727
any(target_arch = "x86", target_arch = "x86_64"),
28-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
28+
target_feature(enable = "sse3,sse4.1,pclmulqdq")
2929
)]
30-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
30+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
3131
pub unsafe fn update<T: ArchOps, W: EnhancedCrcWidth>(
3232
state: W::Value,
3333
bytes: &[u8],
@@ -78,9 +78,9 @@ where
7878
#[inline]
7979
#[cfg_attr(
8080
any(target_arch = "x86", target_arch = "x86_64"),
81-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
81+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
8282
)]
83-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
83+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
8484
unsafe fn process_by_strategy<T: ArchOps, W: EnhancedCrcWidth>(
8585
strategy: DataChunkProcessor,
8686
data: &[u8],
@@ -114,9 +114,9 @@ where
114114
#[inline]
115115
#[cfg_attr(
116116
any(target_arch = "x86", target_arch = "x86_64"),
117-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
117+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
118118
)]
119-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
119+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
120120
unsafe fn process_large_aligned<T: ArchOps, W: EnhancedCrcWidth>(
121121
bytes: &[u8],
122122
state: &mut CrcState<T::Vector>,
@@ -167,9 +167,9 @@ where
167167
#[inline]
168168
#[cfg_attr(
169169
any(target_arch = "x86", target_arch = "x86_64"),
170-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
170+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
171171
)]
172-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
172+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
173173
unsafe fn process_simd_chunks<T: ArchOps, W: EnhancedCrcWidth>(
174174
state: &mut CrcState<T::Vector>,
175175
first: &[T::Vector; 8],
@@ -247,9 +247,9 @@ unsafe fn process_simd_chunks<T: ArchOps, W: EnhancedCrcWidth>(
247247
#[inline]
248248
#[cfg_attr(
249249
any(target_arch = "x86", target_arch = "x86_64"),
250-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
250+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
251251
)]
252-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
252+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
253253
unsafe fn process_exactly_16<T: ArchOps, W: EnhancedCrcWidth>(
254254
data: &[u8],
255255
state: &mut CrcState<T::Vector>,
@@ -273,9 +273,9 @@ where
273273
#[inline]
274274
#[cfg_attr(
275275
any(target_arch = "x86", target_arch = "x86_64"),
276-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
276+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
277277
)]
278-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
278+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
279279
unsafe fn process_16_byte_block<T: ArchOps>(
280280
data_ptr: *const u8,
281281
initial_crc: T::Vector,
@@ -296,9 +296,9 @@ where
296296
#[inline]
297297
#[cfg_attr(
298298
any(target_arch = "x86", target_arch = "x86_64"),
299-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
299+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
300300
)]
301-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
301+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
302302
pub(crate) unsafe fn reflect_bytes<T: ArchOps>(
303303
reflector: &Reflector<T::Vector>,
304304
data: T::Vector,
@@ -317,9 +317,9 @@ where
317317
#[inline]
318318
#[cfg_attr(
319319
any(target_arch = "x86", target_arch = "x86_64"),
320-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
320+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
321321
)]
322-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
322+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
323323
unsafe fn fold_and_xor<T: ArchOps, W: EnhancedCrcWidth>(
324324
current: T::Vector,
325325
coefficient: T::Vector,
@@ -347,9 +347,9 @@ where
347347
#[inline]
348348
#[cfg_attr(
349349
any(target_arch = "x86", target_arch = "x86_64"),
350-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
350+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
351351
)]
352-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
352+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
353353
unsafe fn process_17_to_31<T: ArchOps, W: EnhancedCrcWidth>(
354354
data: &[u8],
355355
state: &mut CrcState<T::Vector>,
@@ -386,9 +386,9 @@ where
386386
#[inline]
387387
#[cfg_attr(
388388
any(target_arch = "x86", target_arch = "x86_64"),
389-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
389+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
390390
)]
391-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
391+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
392392
unsafe fn process_32_to_255<T: ArchOps, W: EnhancedCrcWidth>(
393393
data: &[u8],
394394
state: &mut CrcState<T::Vector>,
@@ -448,9 +448,9 @@ where
448448
#[inline]
449449
#[cfg_attr(
450450
any(target_arch = "x86", target_arch = "x86_64"),
451-
target_feature(enable = "sse2,sse4.1,pclmulqdq")
451+
target_feature(enable = "ssse3,sse4.1,pclmulqdq")
452452
)]
453-
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "neon,aes"))]
453+
#[cfg_attr(target_arch = "aarch64", target_feature(enable = "aes"))]
454454
unsafe fn get_last_two_xmms<T: ArchOps, W: EnhancedCrcWidth>(
455455
data: &[u8],
456456
remaining_len: usize,

‎src/arch/aarch64.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ impl ArchOps for AArch64Ops {
221221
}
222222

223223
#[inline]
224-
#[target_feature(enable = "neon,aes")]
224+
#[target_feature(enable = "aes")]
225225
unsafe fn carryless_mul_00(&self, a: Self::Vector, b: Self::Vector) -> Self::Vector {
226226
vreinterpretq_u8_p128(vmull_p64(
227227
vgetq_lane_p64(vreinterpretq_p64_u8(a), 0),
@@ -230,7 +230,7 @@ impl ArchOps for AArch64Ops {
230230
}
231231

232232
#[inline]
233-
#[target_feature(enable = "neon,aes")]
233+
#[target_feature(enable = "aes")]
234234
unsafe fn carryless_mul_01(&self, a: Self::Vector, b: Self::Vector) -> Self::Vector {
235235
// Low 64 bits of a, high 64 bits of b
236236
let a_low = vgetq_lane_p64(vreinterpretq_p64_u8(a), 1);
@@ -239,7 +239,7 @@ impl ArchOps for AArch64Ops {
239239
}
240240

241241
#[inline]
242-
#[target_feature(enable = "neon,aes")]
242+
#[target_feature(enable = "aes")]
243243
unsafe fn carryless_mul_10(&self, a: Self::Vector, b: Self::Vector) -> Self::Vector {
244244
vreinterpretq_u8_p128(vmull_p64(
245245
vgetq_lane_p64(vreinterpretq_p64_u8(a), 0),
@@ -248,7 +248,7 @@ impl ArchOps for AArch64Ops {
248248
}
249249

250250
#[inline]
251-
#[target_feature(enable = "neon,aes")]
251+
#[target_feature(enable = "aes")]
252252
unsafe fn carryless_mul_11(&self, a: Self::Vector, b: Self::Vector) -> Self::Vector {
253253
vreinterpretq_u8_p128(vmull_p64(
254254
vgetq_lane_p64(vreinterpretq_p64_u8(a), 1),
@@ -258,7 +258,7 @@ impl ArchOps for AArch64Ops {
258258

259259
#[inline]
260260
#[cfg(target_feature = "sha3")]
261-
#[target_feature(enable = "neon,sha3")]
261+
#[target_feature(enable = "sha3")]
262262
unsafe fn xor3_vectors(
263263
&self,
264264
a: Self::Vector,

‎src/arch/mod.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ mod x86;
3838
/// May use native CPU features
3939
#[inline]
4040
#[cfg(target_arch = "aarch64")]
41-
#[target_feature(enable = "neon,aes")]
41+
#[target_feature(enable = "aes")]
4242
pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
4343
let ops = AArch64Ops;
4444

@@ -55,23 +55,23 @@ pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64
5555
not(feature = "vpclmulqdq"),
5656
any(target_arch = "x86", target_arch = "x86_64")
5757
))]
58-
#[target_feature(enable = "sse2,sse4.1,pclmulqdq")]
58+
#[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
5959
pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
6060
update_x86_sse(state, bytes, params)
6161
}
6262

6363
//#[rustversion::since(1.89)]
6464
#[inline]
6565
#[cfg(all(feature = "vpclmulqdq", target_arch = "x86"))]
66-
#[target_feature(enable = "sse2,sse4.1,pclmulqdq")]
66+
#[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
6767
pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
6868
update_x86_sse(state, bytes, params)
6969
}
7070

7171
//#[rustversion::since(1.89)]
7272
#[inline]
7373
#[cfg(all(feature = "vpclmulqdq", target_arch = "x86_64"))]
74-
#[target_feature(enable = "sse2,sse4.1,pclmulqdq")]
74+
#[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
7575
pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
7676
use std::arch::is_x86_feature_detected;
7777

@@ -106,7 +106,7 @@ pub(crate) unsafe fn update(state: u64, bytes: &[u8], params: CrcParams) -> u64
106106

107107
#[inline]
108108
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
109-
#[target_feature(enable = "sse2,sse4.1,pclmulqdq")]
109+
#[target_feature(enable = "ssse3,sse4.1,pclmulqdq")]
110110
unsafe fn update_x86_sse(state: u64, bytes: &[u8], params: CrcParams) -> u64 {
111111
let ops = X86Ops;
112112

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