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Improve docs (from GitHub Copilot’s suggestions)
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src/crc32/fusion/x86/iscsi/avx512_pclmulqdq.rs

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@@ -11,6 +11,8 @@
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/// ./generate -i avx512 -p crc32c -a v4s3x3
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///
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/// Modified as necessary for this Rust implementation.
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///
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/// Uses AVX-512 instructions so only available after Rust 1.89 (when AVX-512 stabilized)
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#[rustversion::since(1.89)]
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#[inline]
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#[target_feature(enable = "avx512vl,pclmulqdq")]

src/crc32/fusion/x86/iscsi/avx512_vpclmulqdq.rs

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/// ./generate -i avx512_vpclmulqdq -p crc32c -a v3x2
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///
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/// Modified as necessary for this Rust implementation.
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///
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/// Uses AVX-512 VPCLMULQDQ instructions, so only available after Rust 1.89 (when AVX-512
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/// stabilized)
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#[rustversion::since(1.89)]
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#[inline]
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#[target_feature(enable = "avx512vl,vpclmulqdq")]

src/crc32/fusion/x86/mod.rs

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@@ -28,8 +28,7 @@ use std::arch::x86::*;
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#[cfg(target_arch = "x86_64")]
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use std::arch::x86_64::*;
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/// Safe wrapper for CRC32 iSCSI calculation using AVX-512
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/// CRC32 iSCSI calculation for Rust versions before 1.89
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/// CRC32 iSCSI calculation for Rust versions before 1.89 (pre-AVX-512 support)
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///
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///
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/// This function is called by the wrapper layer after feature detection has been performed.
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unsafe { crc32_iscsi_sse_v4s3x3(crc, data.as_ptr(), data.len()) }
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}
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/// CRC32 iSCSI calculation using the highest available instruction set
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/// CRC32 iSCSI calculation using the highest available instruction set after Rust 1.89
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/// (post-AVX-512 support)
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///
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/// This function is called by the wrapper layer after feature detection has been performed.
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/// The wrapper layer ensures that only the appropriate implementation is called based on

src/feature_detection.rs

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@@ -100,7 +100,7 @@ unsafe fn detect_arch_capabilities() -> ArchCapabilities {
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unsafe fn detect_aarch64_features() -> ArchCapabilities {
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use std::arch::is_aarch64_feature_detected;
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// AES is available on essentially all Aarch64 CPUs and provides the PMULL instructions
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// AES is available on essentially all AArch64 CPUs and provides the PMULL instructions
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let has_aes = is_aarch64_feature_detected!("aes");
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// SHA3 is available on modern Aarch64 CPUs, and provides the EOR3 instruction for efficient

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