Release candidate for V1.4.4 (#437)

* Release candidate for V1.4.4

Fixes Simulations when using 3rd party simulators

* updating sh_ddr interface to shell V1.4 in cl_template file.

Author: AWSaalluri

Jenkinsfile

@@ -97,10 +97,7 @@ if(fdf_ddr_comb) {
 //=============================================================================
 
 // Map that contains stages of tests
-
-def initial_tests = [:]
-def secondary_tests = [:]
-def multi_stage_tests = [:]
+def all_tests = [:]
 
 // Task to Label map
 task_label = [
@@ -199,7 +196,7 @@ if (env.CHANGE_ID) {
 
 
 if (test_markdown_links || test_src_headers) {
-    initial_tests['Documentation Tests'] = {
+    all_tests['Documentation Tests'] = {
         node(get_task_label(task: 'md_links', xilinx_version: default_xilinx_version)) {
             checkout scm
             commitChangeset = sh(returnStdout: true, script: 'git diff-tree --no-commit-id --name-status -r HEAD').trim()
@@ -253,7 +250,7 @@ if (test_markdown_links || test_src_headers) {
 //=============================================================================
 
 if (test_hdk_scripts) {
-    initial_tests['Test HDK Scripts'] = {
+    all_tests['Test HDK Scripts'] = {
         stage('Test HDK Scripts') {
             String report_file = 'test_hdk_scripts.xml'
             node(get_task_label(task: 'source_scripts', xilinx_version: default_xilinx_version)) {
@@ -278,7 +275,7 @@ if (test_hdk_scripts) {
 }
 
 if (test_fpga_tools) {
-    secondary_tests['Test FPGA Tools 1 Slot'] = {
+    all_tests['Test FPGA Tools 1 Slot'] = {
         stage('Test FPGA Tools 1 Slot') {
             String report_file_tools = 'test_fpga_tools.xml'
             String report_file_sdk = 'test_fpga_sdk.xml'
@@ -310,7 +307,7 @@ if (test_fpga_tools) {
             }
         }
     }
-    secondary_tests['Test FPGA Tools All Slots'] = {
+    all_tests['Test FPGA Tools All Slots'] = {
         stage('Test FPGA Tools All Slots') {
             String report_file_tools = 'test_fpga_tools_all_slots.xml'
             String report_file_sdk = 'test_fpga_sdk_all_slots.xml'
@@ -345,7 +342,7 @@ if (test_fpga_tools) {
 }
 
 if (test_sims) {
-    multi_stage_tests['Run Sims'] = {
+    all_tests['Run Sims'] = {
         stage('Run Sims') {
             def cl_names = ['cl_uram_example', 'cl_dram_dma', 'cl_hello_world']
             def sim_nodes = [:]
@@ -387,7 +384,7 @@ if (test_sims) {
 }
 
 if (test_edma) {
-    secondary_tests['Test EDMA Driver'] = {
+    all_tests['Test EDMA Driver'] = {
         stage('Test EDMA Driver') {
             node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) {
 
@@ -424,7 +421,7 @@ if (test_edma) {
 }
 
 if (test_xdma) {
-    secondary_tests['Test XDMA Driver'] = {
+    all_tests['Test XDMA Driver'] = {
         stage('Test XDMA Driver') {
             node(get_task_label(task: 'runtime', xilinx_version: default_xilinx_version)) {
 
@@ -460,7 +457,7 @@ if(disable_runtime_tests) {
 }
 else {
     if (test_runtime_software) {
-        multi_stage_tests['Test Runtime Software'] = {
+        all_tests['Test Runtime Software'] = {
 
             stage('Test Runtime Software') {
                 def nodes = [:]
@@ -511,7 +508,7 @@ else {
 
 
 if (test_dcp_recipes) {
-    multi_stage_tests['Test DCP Recipes'] = {
+    all_tests['Test DCP Recipes'] = {
         stage('Test DCP Recipes') {
             def nodes = [:]
             for (version in xilinx_versions) {
@@ -560,7 +557,7 @@ if (test_dcp_recipes) {
 if (test_hdk_fdf) {
     // Top level stage for FDF
     // Each CL will have its own parallel FDF stage under this one.
-    multi_stage_tests['HDK_FDF'] = {
+    all_tests['HDK_FDF'] = {
         stage('HDK FDF') {
             def fdf_stages = [:]
             for (version in xilinx_versions) {
@@ -742,7 +739,7 @@ if (test_hdk_fdf) {
 //=============================================================================
 
 if (test_sdaccel_scripts) {
-    initial_tests['Test SDAccel Scripts'] = {
+    all_tests['Test SDAccel Scripts'] = {
         stage('Test SDAccel Scripts') {
             def nodes = [:]
 
@@ -777,7 +774,7 @@ if (test_sdaccel_scripts) {
 }
 
 if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
-    multi_stage_tests['Run SDAccel Tests'] = {
+    all_tests['Run SDAccel Tests'] = {
         String sdaccel_examples_list = 'sdaccel_examples_list.json'
 
         def sdaccel_all_version_stages = [:]
@@ -1083,6 +1080,4 @@ if (test_helloworld_sdaccel_example_fdf || test_all_sdaccel_examples_fdf) {
 
 
 // Run the tests here
-parallel initial_tests
-parallel secondary_tests
-parallel multi_stage_tests
+parallel all_tests

README.md

@@ -46,8 +46,8 @@ The AWS EC2 FPGA Development Kit is provided by AWS to support development and r
 
 | Tool     | Development/Runtime | Tool location | Description |
 | --------|---------|---------|---------|
-| SDx 2017.4 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Software Defined Accelerator Development](SDAccel/README.md) |
-| Vivado 2017.4 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Hardware Accelerator Development](hdk/README.md) |
+| SDx 2017.4 & 2018.2 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Software Defined Accelerator Development](SDAccel/README.md) |
+| Vivado 2017.4 & 2018.2 | Development | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Used for [Hardware Accelerator Development](hdk/README.md) |
 | FPGA AFI Management Tools | Runtime | [SDK - fpga\_mgmt\_tools](sdk/userspace/fpga_mgmt_tools) | Command-line tools used for FPGA management while running on the F1 instance |
 | Virtual JTAG | Development (Debug) | [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) | Runtime debug waveform |
 | wait\_for\_afi | Development | [wait\_for\_afi.py](shared/bin/scripts/wait_for_afi.py) | Helper script that notifies via email on AFI generation completion |

RELEASE_NOTES.md

@@ -25,7 +25,10 @@
          *    CL to SH 512-bit AXI4 interface
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
-         
+
+## Release 1.4.4 (See [ERRATA](./ERRATA.md) for unsupported features)        
+* Fixed compile issues in Simulation while using  3rd pary simulators (synopsys VCS, Cadence IES and Menor Questasim).
+
 ## Release 1.4.3 (See [ERRATA](./ERRATA.md) for unsupported features)
 * [DRAM Data Retention](hdk/docs/data_retention.md) - With DRAM data retention, developers can simply load a new AFI and continue using the data that is persistently kept in the DRAM attached to the FPGA, eliminating unnecessary data movements and greatly improving the overall application performance.
 * [Virtual Ethernet](./sdk/apps/virtual-ethernet/README.md) - Provides a low latency network interface for EC2 F1, that enables high performance hardware acceleration to ethernet based applications on AWS like firewalls, routers and advanced security virtual appliances. With Virtual Ethernet, developers are able to create F1 accelerators that process ethernet packets directly from user-space on the FPGA with high throughput and low-latency. 

SDAccel/docs/Debug_OpenCL_Kernel.md

@@ -0,0 +1,144 @@
+Hardware Debug of SDAccel OpenCL Kernel
+======================
+
+This file contains the following sections:
+
+1. Overview
+2. Enabling ChipScope Debug
+3. Host code changes to support debugging
+4. Building the executable, creating the AFI, and executing the host code
+5. Start debug servers
+
+
+## 1. Overview
+The sections below give you a brief explanation of the steps required to debug your SDAccel OpenCL kernel.  They include enabling ChipScope debug,  pausing the execution of the host code at the appropriate stage to ensure the setup of ILA triggers, building the running the host code and starting the debug servers to debug the design in hardware.  
+
+## 2. Enabling ChipScope Debug 
+
+Debug cores can be added to the AXI interfaces on the kernel itself to monitor AXI transaction level activity (part of the ChipScope Debug feature of SDAccel).
+
+
+
+Adding debug cores to the AXI interfaces on the kernel can be done in a couple of ways:
+
+- Using the SDAccel GUI and enabling "ChipScope Debug" on the hardware function in the Hardware Function Settings window.  
+
+  - Note: If you are building on AWS and need information on how to enable the SDAccel GUI on AWS F1, see​  [README_GUI.md](./README_GUI.md).  If you are building on premise, follow the directions in [On_Premises_Development_Steps.md](./On_Premises_Development_Steps.md).
+
+- Using the XOCC --dk chipscope option with the compute unit name and optional interface name. 
+
+
+
+
+To enable ChipScope debug using the GUI, perform the following steps:
+
+1. In the assistant window, under System build configuration, right-click on the compute unit that you want to enable ChipScope debug on and click settings.
+
+
+
+
+
+  ![](./figure/sda_chipscope_flow1.PNG)
+
+2. When the hardware function settings dialog appears, check the box for "ChipScope Debug" in the debug and profiling settings table.  By checking this box, the compute unit will now have a System ILA inserted onto it's AXI interface ports.
+  ![](./figure/sda_chipscope_flow2.PNG)
+
+
+
+Alternatively, ChipScope debug can be enabled by adding an XOCC option to the CLFLAGS in the makefile.  This method allows the ChipScope debug feature to be enabled without invoking the SDAccel GUI.  The --dk option shown below shows the general usage:
+
+```
+--dk chipscope:<compute_unit_name>:<interface_name>
+```
+
+For example, to add ChipScope debugging to the helloworld_ocl OpenCL example , enabling chipscope debug can be accomplished by adding the following XOCC option to the CLFLAGS in the makefile:
+
+```
+--dk chipscope:krnl_vadd_1
+```
+
+For detailed usage and more examples, refer to the SDAccel Debugging Guide (UG1281 v2018.2).
+
+
+
+## 3. Host code changes to support debugging
+
+The application host code needs to be modified to ensure you can set up the ILA trigger conditions **prior** to  running the kernel.   
+
+
+
+The host code shown below introduces the wait for the setup of ILA Trigger conditions and the arming of the ILA.
+
+src/host.cpp
+
+		void wait_for_enter(const std::string& msg)
+		{
+		    std::cout << msg << std::endl;
+		    std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
+		}
+	
+		...
+	
+		cl::Program::Binaries bins = xcl::import_binary_file(binaryFile);
+		devices.resize(1);
+		cl::Program program(context, devices, bins);
+		cl::Kernel krnl_vadd(program,"krnl_vadd_rtl");
+		
+		wait_for_enter("\nPress ENTER to continue after setting up ILA trigger...");
+		
+		//Allocate Buffer in Global Memory
+		
+		...
+	
+		//Launch the Kernel
+		q.enqueueTask(krnl_vadd);
+
+
+
+## 4. Building the executable, creating the AFI and executing the host code
+
+- **Build the executable** in your design directory (`your_design_directory`) by running the steps below:
+
+```
+	cd your_design_directory
+
+	make all DEVICES=$AWS_PLATFORM
+```
+
+- **Creating and registering the AFI**
+
+Please note, the angle bracket directories need to be replaced according to the user setup.
+
+```	
+	$SDACCEL_DIR/tools/create_sdaccel_afi.sh -xclbin=your_design.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.xclbin -o=your_design.hw.xilinx_aws-vu9p-f1-04261818_dynamic_5_0.awsxclbin -s3_bucket=<bucket-s3_dcp_key=<f1-dcp-folder-s3_logs_key=<f1-logs>
+```
+
+- **Setup and Execute**
+
+```
+		$ sudo sh
+		# source /opt/Xilinx/SDx/2017.4.rte.dyn/setup.sh
+		# ./host
+```
+This produces the following output: 
+```
+			Device/Slot[0] (/dev/xdma0, 0:0:1d.0)
+			xclProbe found 1 FPGA slots with XDMA driver running
+			platform Name: Xilinx
+			Vendor Name : Xilinx
+			Found Platform
+			XCLBIN File Name: vadd
+			INFO: Importing ./binary_container_1.awsxclbin
+			Loading: './binary_container_1.awsxclbin'
+			Successfully skipped reloading of local image.
+			
+			Press ENTER to continue after setting up ILA trigger...
+```
+
+
+## 5. Start Debug Servers
+
+#### Starting Debug Servers on Amazon F1 instance
+Instructions to start the debug servers on an Amazon F1 instance can be found [here](../../hdk/docs/Virtual_JTAG_XVC.md).
+Once you have setup your ILA triggers and armed the ILA core, you can now Press Enter on your host to continue execution of the application and RTL Kernel.
+