Merge pull request #341 from sbarillet/master

fixed encryption issue with verilog file extension (.v)

Author: kristopk

hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl

@@ -238,7 +238,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv [ glob $ENC_SRC_DIR/*.?v ]
+read_verilog -sv [ glob $ENC_SRC_DIR/*.{v,sv} ]
 
 #---- End of section replaced by User ----
 

hdk/cl/examples/cl_dram_dma/build/scripts/encrypt.tcl

@@ -63,7 +63,7 @@ file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
 exec chmod +w {*}[glob $TARGET_DIR/*]
 
 # encrypt .v/.sv/.vh/inc as verilog files
-encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.?v] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
+encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
 
 # encrypt *vhdl files
 encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]

hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl

@@ -180,7 +180,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----
 

hdk/cl/examples/cl_hello_world/build/scripts/encrypt.tcl

@@ -51,7 +51,7 @@ file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc        $TARGET_DI
 exec chmod +w {*}[glob $TARGET_DIR/*]
 
 # encrypt .v/.sv/.vh/inc as verilog files
-encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.?v] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
+encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog  [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
 
 # encrypt *vhdl files
 encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]

hdk/common/shell_v032117d7/new_cl_template/build/scripts/create_dcp_from_cl.tcl

@@ -112,7 +112,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----
 

hdk/common/shell_v04151701/new_cl_template/build/scripts/create_dcp_from_cl.tcl

@@ -173,7 +173,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer's
 # Reading the .sv and .v files, as proper designs would not require
 # reading .v, .vh, nor .inc files
 
-read_verilog -sv  [glob $ENC_SRC_DIR/*.?v] 
+read_verilog -sv  [glob $ENC_SRC_DIR/*.{v,sv}] 
 
 #---- End of section replaced by User ----