Release candidate for Release V1.4.2 (#426)

AWSaalluri · kristopk · commit 2ecf9b9c5435 · 2018-08-29T17:05:43.000-05:00
* Release candidate for Release V1.4.2

* V1.4.2 release notes &amp; delta updates
diff --git a/Jenkinsfile b/Jenkinsfile
@@ -21,7 +21,9 @@ properties([parameters([
     booleanParam(name: 'debug_dcp_gen',                       defaultValue: false, description: 'Only run FDF on cl_hello_world. Overrides test_*.'),
     booleanParam(name: 'debug_fdf_uram',                      defaultValue: false, description: 'Debug the FDF for cl_uram_example.'),
     booleanParam(name: 'fdf_ddr_comb',                        defaultValue: false, description: 'run FDF for cl_dram_dma ddr combinations.'),
-    booleanParam(name: 'disable_runtime_tests',               defaultValue: false,  description: 'Option to disable runtime tests.')
+    booleanParam(name: 'disable_runtime_tests',               defaultValue: false,  description: 'Option to disable runtime tests.'),
+    booleanParam(name: 'use_test_ami',                        defaultValue: false,  description: 'This option asks for the test AMI from Jenkins')
+
 ])])
 
 //=============================================================================
@@ -144,6 +146,13 @@ def is_public_repo() {
 
 def get_task_label(Map args=[ : ]) {
     String task_label = args.xilinx_version + '_' + task_label[args.task]
+    //boolean use_test_ami = params.get('use_test_ami')
+
+    if (params.use_test_ami) {
+        echo "Test AMI Requested"
+        task_label = task_label + '_test'
+    }
+
     echo "Label Requested: $task_label"
     return task_label
 }
diff --git a/README.md b/README.md
@@ -77,7 +77,8 @@ NOTE: For on-premises development, SDx/Vivado must have the correct license and
 # Getting Started
 
 ### New to AWS?
-If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI.  These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`).
+If you are new to AWS, we recommend you start with [AWS getting started training](https://aws.amazon.com/getting-started/), to learn how to use AWS EC2, S3 and the AWS CLI.  These services are required to start developing accelerations for AWS FPGAs. For example, creating an AFI requires [AWS CLI](http://docs.aws.amazon.com/cli/latest/userguide/cli-chap-getting-started.html) installed and the execution of `aws s3 <action>` (`aws ec2 create-fpga-image`).  AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US).
+
 
 ### New to AWS FPGAs and setting up a development environment?
 The developer kit is supported for Linux operating systems only.  You have the choice to develop on AWS EC2 using the [FPGA developer AMI](https://aws.amazon.com/marketplace/pp/B06VVYBLZZ) or on-premises. Within a linux environment, you should execute `git clone https://github.com/aws/aws-fpga.git` to download the latest release to your EC2 Instance or local server. Using a SSH connection, execute `git clone git@github.com:aws/aws-fpga.git`. [To get help with connecting to Github via SSH](https://help.github.com/articles/connecting-to-github-with-ssh/).
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
@@ -25,6 +25,9 @@
          *    CL to SH 512-bit AXI4 interface
          *    1 DDR controller implemented in the SH (always available)
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
+         
+## Release 1.4.2 (See [ERRATA](./ERRATA.md) for unsupported features)
+* Fixed SDAccel XOCL driver compile fails that occur on linux kernels greater than 3.10.0-862.3.3.el7.x86_64
 
 ## Release 1.4.1 (See [ERRATA](./ERRATA.md) for unsupported features)
 * Simulation performance Improvements
diff --git a/hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc b/hdk/cl/examples/cl_dram_dma/build/constraints/cl_pnr_user.xdc
@@ -61,8 +61,8 @@ resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X2Y
 set_property SNAPPING_MODE ON [get_pblocks pblock_CL_bot]
 set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]
 
-set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
-set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
-set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
+#set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
+#set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]
+#set_clock_groups -name TIG_SRAI_3 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins static_sh/pcie_inst/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_userclk/O]]
 
 
diff --git a/hdk/cl/examples/cl_dram_dma/build/constraints/cl_synth_user.xdc b/hdk/cl/examples/cl_dram_dma/build/constraints/cl_synth_user.xdc
@@ -1,5 +1,3 @@
 # This contains the CL specific constraints for synthesis at the CL level
-set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
-set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins WRAPPER_INST/CL/CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
-
-
+set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins SH_DDR/ddr_cores.DDR4_0/inst/div_clk_rst_r1_reg/Q]]
+set_property MAX_FANOUT 50 [get_nets -of_objects [get_pins CL_PCIM_MSTR/CL_TST_PCI/sync_rst_n_reg/Q]]
diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/create_dcp_from_cl.tcl
@@ -37,7 +37,7 @@ set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
 set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
-
+set VDEFINES            [lindex $argv 13]
 ##################################################
 ## Flow control variables 
 ##################################################
@@ -104,6 +104,11 @@ puts "All reports and intermediate results will be time stamped with $timestamp"
 
 set_msg_config -id {Chipscope 16-3} -suppress
 set_msg_config -string {AXI_QUAD_SPI} -suppress
+set_msg_config -string {PIPE_CL_SH_AURORA_STAT} -suppress
+set_msg_config -string {PIPE_CL_SH_HMC_STAT} -suppress
+set_msg_config -string {PIPE_AURORA_CHANNEL_UP} -suppress
+set_msg_config -string {PIPE_HMC_IIC} -suppress
+set_msg_config -string {PIPE_SH_CL_AURORA_STAT} -suppress
 
 # Suppress Warnings
 # These are to avoid warning messages that may not be real issues. A developer
@@ -123,7 +128,7 @@ set_msg_config -id {Vivado 12-4739}      -suppress
 set_msg_config -id {Vivado 12-5201}      -suppress
 set_msg_config -id {DRC CKLD-1}          -suppress
 set_msg_config -id {IP_Flow 19-2248}     -suppress
-set_msg_config -id {Opt 31-155}          -suppress
+#set_msg_config -id {Opt 31-155}          -suppress
 set_msg_config -id {Synth 8-115}         -suppress
 set_msg_config -id {Synth 8-3936}        -suppress
 set_msg_config -id {Vivado 12-1023}      -suppress
diff --git a/hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl b/hdk/cl/examples/cl_dram_dma/build/scripts/synth_cl_dram_dma.tcl
@@ -16,6 +16,7 @@
 #Param needed to avoid clock name collisions
 set_param sta.enableAutoGenClkNamePersistence 0
 set CL_MODULE $CL_MODULE
+set VDEFINES $VDEFINES
 
 create_project -in_memory -part [DEVICE_TYPE] -force
 
@@ -115,7 +116,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
 
 update_compile_order -fileset sources_1
 puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
-eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
 
 set failval [catch {exec grep "FAIL" failfast.csv}]
 if { $failval==0 } {
diff --git a/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv b/hdk/cl/examples/cl_dram_dma/design/cl_dma_pcis_slv.sv
@@ -150,7 +150,12 @@ lib_pipe #(.WIDTH(1), .STAGES(4)) SLR2_PIPE_RST_N (.clk(aclk), .rst_n(1'b1), .in
        .m_axi_rready  (sh_cl_dma_pcis_q.rready)
    );
 
-
+//-----------------------------------------------------
+//TIE-OFF unused signals to prevent critical warnings
+//-----------------------------------------------------
+   assign sh_cl_dma_pcis_q.rid[15:6] = 10'b0 ;
+   assign sh_cl_dma_pcis_q.bid[15:6] = 10'b0 ;
+   
 //---------------------------- 
 // axi interconnect for DDR address decodes 
 //---------------------------- 
diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/create_dcp_from_cl.tcl
@@ -37,7 +37,7 @@ set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
 set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
-
+set VDEFINES            [lindex $argv 13]
 ##################################################
 ## Flow control variables 
 ##################################################
@@ -132,6 +132,7 @@ set_msg_config -id {DRC REQP-1853}       -suppress
 set_msg_config -id {Synth 8-350}         -suppress
 set_msg_config -id {Synth 8-3848}        -suppress
 set_msg_config -id {Synth 8-3917}        -suppress
+set_msg_config -id {Opt 31-430}          -suppress
 
 puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
 
@@ -247,6 +248,7 @@ if {$implement} {
    ########################
    # CL Optimize
    ########################
+   set place_preHookTcl  ""
    if {$opt} {
       puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running optimization";
       impl_step opt_design $TOP $opt_options $opt_directive $opt_preHookTcl $opt_postHookTcl
diff --git a/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl b/hdk/cl/examples/cl_hello_world/build/scripts/synth_cl_hello_world.tcl
@@ -16,6 +16,7 @@
 #Param needed to avoid clock name collisions
 set_param sta.enableAutoGenClkNamePersistence 0
 set CL_MODULE $CL_MODULE
+set VDEFINES $VDEFINES
 
 create_project -in_memory -part [DEVICE_TYPE] -force
 
@@ -106,7 +107,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
 
 update_compile_order -fileset sources_1
 puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
-eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
 
 set failval [catch {exec grep "FAIL" failfast.csv}]
 if { $failval==0 } {
diff --git a/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/create_dcp_from_cl.tcl
@@ -37,7 +37,7 @@ set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
 set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
-
+set VDEFINES            [lindex $argv 13]
 ##################################################
 ## Flow control variables 
 ##################################################
diff --git a/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl b/hdk/cl/examples/cl_hello_world_vhdl/build/scripts/synth_cl_hello_world.tcl
@@ -16,6 +16,7 @@
 #Param needed to avoid clock name collisions
 set_param sta.enableAutoGenClkNamePersistence 0
 set CL_MODULE $CL_MODULE
+set VDEFINES $VDEFINES
 
 create_project -in_memory -part [DEVICE_TYPE] -force
 
@@ -120,7 +121,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
 
 update_compile_order -fileset sources_1
 puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
-eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
 
 set failval [catch {exec grep "FAIL" failfast.csv}]
 if { $failval==0 } {
diff --git a/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl b/hdk/cl/examples/cl_uram_example/build/scripts/create_dcp_from_cl.tcl
@@ -37,7 +37,7 @@ set clock_recipe_b      [lindex $argv  9]
 set clock_recipe_c      [lindex $argv 10]
 set uram_option         [lindex $argv 11]
 set notify_via_sns      [lindex $argv 12]
-
+set VDEFINES            [lindex $argv 13]
 ##################################################
 ## Flow control variables 
 ##################################################
diff --git a/hdk/cl/examples/cl_uram_example/build/scripts/synth_cl_uram_example.tcl b/hdk/cl/examples/cl_uram_example/build/scripts/synth_cl_uram_example.tcl
@@ -16,6 +16,7 @@
 #Param needed to avoid clock name collisions
 set_param sta.enableAutoGenClkNamePersistence 0
 set CL_MODULE $CL_MODULE
+set VDEFINES $VDEFINES
 
 create_project -in_memory -part [DEVICE_TYPE] -force
 
@@ -140,7 +141,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes
 
 update_compile_order -fileset sources_1
 puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
-eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
+eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]
 
 set failval [catch {exec grep "FAIL" failfast.csv}]
 if { $failval==0 } {
diff --git a/hdk/common/shell_v04261818/build/constraints/cl_debug_bridge.xdc b/hdk/common/shell_v04261818/build/constraints/cl_debug_bridge.xdc
@@ -1,14 +1,14 @@
-set bridge [get_debug_cores -filter {NAME=~ WRAPPER_INST/CL/*CL_DEBUG_BRIDGE*}]
+set bridge [get_debug_cores -filter {NAME=~WRAPPER_INST/CL/*CL_DEBUG_BRIDGE*}]
 current_instance $bridge/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst
 
-set wr_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
-set rd_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
+set wr_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance wr_clk]]
+set rd_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance rd_clk]]
 set wr_clk_period     [get_property PERIOD $wr_clock]
 set rd_clk_period     [get_property PERIOD $rd_clock]
 set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
 
 # Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
-set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
+set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
 
 # Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
 
@@ -22,14 +22,14 @@ current_instance
 
 current_instance $bridge/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst
 
-set wr_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance tck]]
-set rd_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance clk]]
+set wr_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance wr_clk]]
+set rd_clock          [get_clocks -of_objects [get_ports -scoped_to_current_instance rd_clk]]
 set wr_clk_period     [get_property PERIOD $wr_clock]
 set rd_clk_period     [get_property PERIOD $rd_clock]
 set skew_value [expr {(($wr_clk_period < $rd_clk_period) ? $wr_clk_period : $rd_clk_period)} ]
 
 # Ignore paths from the write clock to the read data registers for Asynchronous Distributed RAM based FIFO
-set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance tck] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
+set_false_path -from [filter [all_fanout -from [get_ports -scoped_to_current_instance wr_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~ *gdm.dm_gen.dm*/gpr1.dout_i_reg*}]
 
 # Set max delay on cross clock domain path for Block/Distributed RAM based FIFO
 
diff --git a/hdk/common/shell_v04261818/build/scripts/aws_build_dcp_from_cl.sh b/hdk/common/shell_v04261818/build/scripts/aws_build_dcp_from_cl.sh
@@ -18,7 +18,7 @@
 # Usage help
 function usage
 {
-    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-foreground] [-notify] | [-h] | [-H] | [-help] ]"
+    echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-vdefine macro1,macro2,macro3,.....,macrox] -foreground] [-notify] | [-h] | [-H] | [-help] ]"
     echo " "
     echo "By default the build is run in the background using nohup so that the"
     echo "process will not be terminated if the terminal window is closed."
@@ -44,6 +44,7 @@ notify=0
 ignore_memory_requirement=0
 expected_memory_usage=30000000
 uram_option=2
+vdefine=""
 
 function info_msg {
   echo -e "INFO: $1"
@@ -90,6 +91,9 @@ while [ "$1" != "" ]; do
         -uram_option )          shift
                                 uram_option=$1
                                 ;;
+        -vdefine )              shift
+                                vdefine=$1
+                                ;;
         -foreground )           foreground=1
                                 ;;
         -notify )               notify=1
@@ -145,7 +149,20 @@ if [[ $uram_option != @(2|3|4) ]]; then
   err_msg "$uram_option isn't a valid URAM option. Valid URAM options are 2 (50%), 3 (75%), and 4 (100%)."
   exit 1
 fi
+# process vdefines
+info_msg "VDEFINE is : $vdefine"
+shopt -s extglob
+IFS=',' read -r -a vdefine_array <<< "$vdefine"
 
+opt_vdefine=""
+
+for index in "${!vdefine_array[@]}"
+do 
+ echo "$index ${vdefine_array[index]}"
+ opt_vdefine+=" -verilog_define "
+ opt_vdefine+=${vdefine_array[index]}
+done
+echo "$opt_vdefine"
 if [ $expected_memory_usage -gt `get_instance_memory` ]; then
 
     output_message="YOUR INSTANCE has less memory than is necessary for certain builds. This means that your builds will take longer than expected. \nTo change to an instance type with more memory, please check our instance resize guide: http://docs.aws.amazon.com/AWSEC2/latest/UserGuide/ec2-instance-resize.html"
@@ -226,7 +243,7 @@ subsystem_id="0x${id1_version:0:4}";
 subsystem_vendor_id="0x${id1_version:4:4}";
 
 # Run vivado
-cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $uram_option $notify"
+cmd="vivado -mode batch -nojournal -log $logname -source $vivado_script -tclargs $timestamp $strategy $hdk_version $shell_version $device_id $vendor_id $subsystem_id $subsystem_vendor_id $clock_recipe_a $clock_recipe_b $clock_recipe_c $uram_option $notify $opt_vdefine"
 if [[ "$foreground" == "0" ]]; then
   nohup $cmd > $timestamp.nohup.out 2>&1 &
   
diff --git a/hdk/common/shell_v04261818/build/scripts/check_uram.tcl b/hdk/common/shell_v04261818/build/scripts/check_uram.tcl
@@ -14,9 +14,11 @@
 # limitations under the License.
 
 global uramHeight
+global CL_MODULE
 
 ###Check oreg_b usage for uramHeight==3 and uramHeight==4
 set clean 1
+if {[string compare $CL_MODULE "cl_uram_example"] == 0} {
 if {$uramHeight > 2} {
    foreach uram [get_cells -hier -filter {REF_NAME==URAM288 && NAME=~WRAPPER_INST/CL/*} ] {
       set oregB [get_property OREG_B $uram]
@@ -83,3 +85,4 @@ if {$uramHeight == 2} {
 } else {
    error "Error: Variable \'\$uramHeight\' set to unsupported value $uramHeight. Supported values are 2, 3, or 4"
 }  
+}
diff --git a/hdk/docs/HOWTO_detect_shell_timeout.md b/hdk/docs/HOWTO_detect_shell_timeout.md
diff --git a/sdk/linux_kernel_drivers/xocl/xocl_bo.c b/sdk/linux_kernel_drivers/xocl/xocl_bo.c
diff --git a/sdk/userspace/fpga_mgmt_tools/README.md b/sdk/userspace/fpga_mgmt_tools/README.md
diff --git a/supported_vivado_versions.txt b/supported_vivado_versions.txt
