From 457b97878928e62187801f8b105a89614599ef8e Mon Sep 17 00:00:00 2001
From: mijn naam <mijnmail.com>
Date: Mon, 8 Jun 2020 14:34:19 +0200
Subject: [PATCH 1/6] uart part 1

---
 controller.vhdl                 | 138 ++++++++++++++++
 vhdl_source/controller.vhdl     | 284 ++++++++++++++------------------
 vhdl_source/controller.vhdl.bak | 138 ++++++++++++++++
 vhdl_source/uart.vhdl           |  56 ++++++-
 vhdl_source/uart.vhdl.bak       |  64 +++++++
 5 files changed, 519 insertions(+), 161 deletions(-)
 create mode 100644 controller.vhdl
 create mode 100644 vhdl_source/controller.vhdl.bak
 create mode 100644 vhdl_source/uart.vhdl.bak

diff --git a/controller.vhdl b/controller.vhdl
new file mode 100644
index 0000000..54359a7
--- /dev/null
+++ b/controller.vhdl
@@ -0,0 +1,138 @@
+library IEEE;
+-- Hier komen de gebruikte libraries:
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+entity controller is
+port ( clk : in std_logic;
+reset : in std_logic;
+
+sensor_l : in std_logic;
+sensor_m : in std_logic;
+sensor_r : in std_logic;
+mine_detect: in std_logic;
+count_in : in std_logic_vector (19 downto 0);
+count_reset : out std_logic;
+
+motor_l_reset : out std_logic;
+motor_l_direction : out std_logic;
+
+motor_r_reset : out std_logic;
+motor_r_direction : out std_logic
+);
+end entity controller;
+
+architecture controller_behav of controller is
+type diff_states is (Startturn,Sensor_check,Wait_for_line);
+signal state, next_state: diff_states;
+signal sensor: std_logic_vector(2 downto 0); 
+signal mine : std_logic; -- using for being in state mine_detect.
+signal motorreset: std_logic;
+signal reset_l_motor, reset_r_motor: std_logic;
+begin
+sensor(2)<=sensor_l;
+sensor(1)<=sensor_m;
+sensor(0)<=sensor_r;
+ttl:process(sensor,state,mine_detect)
+  begin
+case state is
+when Startturn =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+if(sensor="111") then
+next_state <= Wait_for_line;
+else next_state<=Startturn;
+end if;
+when Wait_for_line =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+if(sensor="110") then
+next_state <= Sensor_check;
+else next_state <= Wait_for_line;
+end if;
+when Sensor_check=>
+if (sensor="000") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "001") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '1';
+reset_r_motor <= '0';
+
+elsif(sensor= "010") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "011") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "100") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_r_motor <= '1';
+reset_l_motor <= '0';
+
+elsif(sensor= "101") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "110") then
+motor_l_direction <= '1';
+        motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "111") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+else
+motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+        end if;
+if(mine_detect='1') then
+next_state<=Startturn;
+else
+next_state<=Sensor_check;
+end if;
+     end case;       
+end process;
+clk_sig: process(clk,reset)
+begin
+if (reset='1') then
+    count_reset <= '1';
+    motorreset <= '1';
+    state<=Sensor_check;
+    elsif (clk'event and clk='1') then
+state<=next_state;
+        if (unsigned(count_in) =1000000) then
+      count_reset <= '1';
+      motorreset <= '1';
+    else
+      count_reset <= '0';
+      motorreset <= '0';
+    end if;
+end if;
+end process;
+
+motor_l_reset <= reset_l_motor or motorreset;
+motor_r_reset <= reset_r_motor or motorreset;
+
+end controller_behav;
diff --git a/vhdl_source/controller.vhdl b/vhdl_source/controller.vhdl
index 8b19bb6..54359a7 100644
--- a/vhdl_source/controller.vhdl
+++ b/vhdl_source/controller.vhdl
@@ -1,172 +1,138 @@
 library IEEE;
+-- Hier komen de gebruikte libraries:
+use IEEE.numeric_std.all;
 use IEEE.std_logic_1164.all;
-use ieee.numeric_std.all;
 
 entity controller is
-	port (	clk			: in	std_logic;
-		reset			: in	std_logic;
+port ( clk : in std_logic;
+reset : in std_logic;
 
-		sensor_l		: in	std_logic;
-		sensor_m		: in	std_logic;
-		sensor_r		: in	std_logic;
-		mine_detect		: in	std_logic;
+sensor_l : in std_logic;
+sensor_m : in std_logic;
+sensor_r : in std_logic;
+mine_detect: in std_logic;
+count_in : in std_logic_vector (19 downto 0);
+count_reset : out std_logic;
 
-		count_in		: in	std_logic_vector (19 downto 0);
-		count_reset		: out	std_logic;
+motor_l_reset : out std_logic;
+motor_l_direction : out std_logic;
 
-		motor_l_reset		: out	std_logic;
-		motor_l_direction	: out	std_logic;
-
-		motor_r_reset		: out	std_logic;
-		motor_r_direction	: out	std_logic
-	);
+motor_r_reset : out std_logic;
+motor_r_direction : out std_logic
+);
 end entity controller;
 
-architecture behaviour of controller is
+architecture controller_behav of controller is
+type diff_states is (Startturn,Sensor_check,Wait_for_line);
+signal state, next_state: diff_states;
+signal sensor: std_logic_vector(2 downto 0); 
+signal mine : std_logic; -- using for being in state mine_detect.
+signal motorreset: std_logic;
+signal reset_l_motor, reset_r_motor: std_logic;
+begin
+sensor(2)<=sensor_l;
+sensor(1)<=sensor_m;
+sensor(0)<=sensor_r;
+ttl:process(sensor,state,mine_detect)
+  begin
+case state is
+when Startturn =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+if(sensor="111") then
+next_state <= Wait_for_line;
+else next_state<=Startturn;
+end if;
+when Wait_for_line =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+if(sensor="110") then
+next_state <= Sensor_check;
+else next_state <= Wait_for_line;
+end if;
+when Sensor_check=>
+if (sensor="000") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "001") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '1';
+reset_r_motor <= '0';
+
+elsif(sensor= "010") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "011") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
 
-	type controller_state is ( 	motor_uit ,
-					motor_both,
-					motor_gentleleft,
-					motor_gentleright,
-					motor_sharpleft,
-					motor_sharpright,
-					motor_white_mine,
-					motor_right_mine,
-					motor_reset_mine);
-	signal state, new_state : controller_state;
+elsif(sensor= "100") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_r_motor <= '1';
+reset_l_motor <= '0';
 
+elsif(sensor= "101") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "110") then
+motor_l_direction <= '1';
+        motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "111") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+else
+motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+        end if;
+if(mine_detect='1') then
+next_state<=Startturn;
+else
+next_state<=Sensor_check;
+end if;
+     end case;       
+end process;
+clk_sig: process(clk,reset)
 begin
-	process ( clk )
-	begin
-		if (clk'event and clk = '1') then
-			if (reset = '1') then
-				state <= motor_uit; 
-			else
-				state <= new_state;
-			end if ;
-		end if ;
-	end process ;
+if (reset='1') then
+    count_reset <= '1';
+    motorreset <= '1';
+    state<=Sensor_check;
+    elsif (clk'event and clk='1') then
+state<=next_state;
+        if (unsigned(count_in) =1000000) then
+      count_reset <= '1';
+      motorreset <= '1';
+    else
+      count_reset <= '0';
+      motorreset <= '0';
+    end if;
+end if;
+end process;
+
+motor_l_reset <= reset_l_motor or motorreset;
+motor_r_reset <= reset_r_motor or motorreset;
 
-	process (state, count_in, sensor_l, sensor_r, sensor_m, mine_detect)
-	begin
-		case state is
-			when motor_uit =>
-				count_reset <= '1';
-				motor_l_reset <= '1';
-				motor_r_reset <= '1';
-				if (mine_detect = '1') then
-					new_state <=	motor_reset_mine;
-				else
-					if (sensor_l = '0' and sensor_m = '0' and sensor_r = '0') then
-						new_state <= 	motor_both; 
-					elsif (sensor_l = '0' and sensor_m = '0' and sensor_r = '1') then
-						new_state <= 	motor_gentleleft;
-					elsif (sensor_l = '0' and sensor_m = '1' and sensor_r = '0') then
-						new_state <= 	motor_both;
-					elsif (sensor_l = '0' and sensor_m = '1' and sensor_r = '1') then
-						new_state <= 	motor_sharpleft;
-					elsif (sensor_l = '1' and sensor_m = '0' and sensor_r = '0') then
-						new_state <= 	motor_gentleright;
-					elsif (sensor_l = '1' and sensor_m = '0' and sensor_r = '1') then
-						new_state <= 	motor_both; 	
-					elsif (sensor_l = '1' and sensor_m = '1' and sensor_r = '0') then
-						new_state <= 	motor_sharpright;
-					elsif (sensor_l = '1' and sensor_m = '1' and sensor_r = '1') then
-						new_state <= 	motor_both; 	
-					else
-						new_state <= 	motor_uit; 
-					end if;
-				end if;
-			when motor_white_mine =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '0';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '1';
-				if (unsigned(count_in) = 1000000 and sensor_l = '1' and sensor_m = '1' and sensor_r = '0') then
-					new_state <= 	motor_uit; 
-				elsif (unsigned(count_in) = 1000000) then
-					new_state <=	motor_reset_mine;
-				else
-					new_state <= 	motor_white_mine;
-				end if;
-			when motor_right_mine =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '0';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '1';
-				if (unsigned(count_in) = 1000000) then
-					new_state <=	motor_reset_mine;
-				else
-					new_state <= 	motor_right_mine;
-				end if;
-			when motor_reset_mine =>
-				count_reset <= '1';
-				motor_l_reset <= '1';
-				motor_r_reset <= '1';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '1';
-				if (sensor_l = '1' and sensor_m = '1' and sensor_r = '1') then
-					new_state <=	motor_white_mine;
-				else
-					new_state <=	motor_right_mine;
-				end if;
-			when motor_both =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '0';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '0';	
-				if (unsigned(count_in) = 1000000) then
-					new_state <= motor_uit;
-				else
-					new_state <= motor_both;
-				end if;
-			when motor_gentleleft =>
-				count_reset <= '0';
-				motor_l_reset <= '1';
-				motor_r_reset <= '0';
-				motor_l_direction <= '0';		
-				motor_r_direction <= '0';	
-				if (unsigned(count_in) = 1000000) then
-					new_state <= motor_uit;
-				else
-					new_state <= motor_gentleleft;
-				end if;		
-			when motor_sharpleft =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '0';
-				motor_l_direction <= '0';		
-				motor_r_direction <= '0';	
-				if (unsigned(count_in) = 1000000) then
-					new_state <= motor_uit;
-				else
-					new_state <= motor_sharpleft;
-				end if;
-			when motor_gentleright =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '1';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '0';	
-				if (unsigned(count_in) = 1000000) then
-					new_state <= motor_uit;
-				else
-					new_state <= motor_gentleright;
-				end if;	
-			when motor_sharpright =>
-				count_reset <= '0';
-				motor_l_reset <= '0';
-				motor_r_reset <= '0';
-				motor_l_direction <= '1';		
-				motor_r_direction <= '1';	
-				if (unsigned(count_in) = 1000000) then
-					new_state <= motor_uit;
-				else
-					new_state <= motor_sharpright;
-				end if;
-		end case;
-	end process;
-end architecture behaviour;
+end controller_behav;
diff --git a/vhdl_source/controller.vhdl.bak b/vhdl_source/controller.vhdl.bak
new file mode 100644
index 0000000..54359a7
--- /dev/null
+++ b/vhdl_source/controller.vhdl.bak
@@ -0,0 +1,138 @@
+library IEEE;
+-- Hier komen de gebruikte libraries:
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+entity controller is
+port ( clk : in std_logic;
+reset : in std_logic;
+
+sensor_l : in std_logic;
+sensor_m : in std_logic;
+sensor_r : in std_logic;
+mine_detect: in std_logic;
+count_in : in std_logic_vector (19 downto 0);
+count_reset : out std_logic;
+
+motor_l_reset : out std_logic;
+motor_l_direction : out std_logic;
+
+motor_r_reset : out std_logic;
+motor_r_direction : out std_logic
+);
+end entity controller;
+
+architecture controller_behav of controller is
+type diff_states is (Startturn,Sensor_check,Wait_for_line);
+signal state, next_state: diff_states;
+signal sensor: std_logic_vector(2 downto 0); 
+signal mine : std_logic; -- using for being in state mine_detect.
+signal motorreset: std_logic;
+signal reset_l_motor, reset_r_motor: std_logic;
+begin
+sensor(2)<=sensor_l;
+sensor(1)<=sensor_m;
+sensor(0)<=sensor_r;
+ttl:process(sensor,state,mine_detect)
+  begin
+case state is
+when Startturn =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+if(sensor="111") then
+next_state <= Wait_for_line;
+else next_state<=Startturn;
+end if;
+when Wait_for_line =>
+motor_l_direction <= '1';
+motor_r_direction <= '1';
+if(sensor="110") then
+next_state <= Sensor_check;
+else next_state <= Wait_for_line;
+end if;
+when Sensor_check=>
+if (sensor="000") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "001") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '1';
+reset_r_motor <= '0';
+
+elsif(sensor= "010") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "011") then
+        motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "100") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_r_motor <= '1';
+reset_l_motor <= '0';
+
+elsif(sensor= "101") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "110") then
+motor_l_direction <= '1';
+        motor_r_direction <= '1';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+elsif(sensor= "111") then
+motor_l_direction <= '1';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+
+else
+motor_l_direction <= '0';
+        motor_r_direction <= '0';
+reset_l_motor <= '0';
+reset_r_motor <= '0';
+        end if;
+if(mine_detect='1') then
+next_state<=Startturn;
+else
+next_state<=Sensor_check;
+end if;
+     end case;       
+end process;
+clk_sig: process(clk,reset)
+begin
+if (reset='1') then
+    count_reset <= '1';
+    motorreset <= '1';
+    state<=Sensor_check;
+    elsif (clk'event and clk='1') then
+state<=next_state;
+        if (unsigned(count_in) =1000000) then
+      count_reset <= '1';
+      motorreset <= '1';
+    else
+      count_reset <= '0';
+      motorreset <= '0';
+    end if;
+end if;
+end process;
+
+motor_l_reset <= reset_l_motor or motorreset;
+motor_r_reset <= reset_r_motor or motorreset;
+
+end controller_behav;
diff --git a/vhdl_source/uart.vhdl b/vhdl_source/uart.vhdl
index 666cc52..736b92e 100644
--- a/vhdl_source/uart.vhdl
+++ b/vhdl_source/uart.vhdl
@@ -1,3 +1,7 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
 entity uart is
 	port (
 		clk, reset: in std_logic;
@@ -7,6 +11,54 @@ entity uart is
 		data_out: out std_logic_vector(7 downto 0); -- received byte
 		write_data: in std_logic; -- write to transmitter buffer 
 		read_data: in std_logic; -- read from receiver buffer 
-		new_data: out std_logic; -- new data available
+		new_data: out std_logic -- new data available
 	);
-end uart;
\ No newline at end of file
+end uart;
+
+architecture structural of uart is 
+component uart_rx is
+   port(
+      clk, reset: in std_logic;
+      rx: in std_logic; -- icoming serial bit stream
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      rx_done_tick: out std_logic; -- data frame completion tick
+      dout: out std_logic_vector(7 downto 0) -- data byte
+   );
+end component;
+component uart_tx is
+   port(
+      clk, reset: in std_logic;
+      tx_start: in std_logic; -- if '1' transmission starts
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      din: in std_logic_vector(7 downto 0); -- incoming data byte
+      tx_done_tick: out std_logic; -- data frame completion tick 
+      tx: out std_logic -- outcoming bit stream
+   );
+end component;
+component buf_reg is
+   port(
+      clk, reset: in std_logic;
+      clr_flag, set_flag: in std_logic; 
+      din: in std_logic_vector(7 downto 0);
+      dout: out std_logic_vector(7 downto 0);
+      flag: out std_logic
+   );
+end component;
+component baud_gen is
+   generic(
+      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
+  );
+   port(
+      clk, reset: in std_logic;
+      s_tick: out std_logic -- sampling tick
+   );
+end component;
+signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
+signal dout_rx, din_tx : std_logic_vector(7 downto 0);
+begin
+U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
+U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
+U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
+U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
+end structural;
\ No newline at end of file
diff --git a/vhdl_source/uart.vhdl.bak b/vhdl_source/uart.vhdl.bak
new file mode 100644
index 0000000..eb48554
--- /dev/null
+++ b/vhdl_source/uart.vhdl.bak
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart is
+	port (
+		clk, reset: in std_logic;
+		rx: in std_logic; -- input bit stream
+		tx: out std_logic; -- output bit stream
+		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
+		data_out: out std_logic_vector(7 downto 0); -- received byte
+		write_data: in std_logic; -- write to transmitter buffer 
+		read_data: in std_logic; -- read from receiver buffer 
+		new_data: out std_logic -- new data available
+	);
+end uart;
+
+architecture structural of uart is 
+component uart_rx is
+   port(
+      clk, reset: in std_logic;
+      rx: in std_logic; -- icoming serial bit stream
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      rx_done_tick: out std_logic; -- data frame completion tick
+      dout: out std_logic_vector(7 downto 0) -- data byte
+   );
+end component;
+component uart_tx is
+   port(
+      clk, reset: in std_logic;
+      tx_start: in std_logic; -- if '1' transmission starts
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      din: in std_logic_vector(7 downto 0); -- incoming data byte
+      tx_done_tick: out std_logic; -- data frame completion tick 
+      tx: out std_logic -- outcoming bit stream
+   );
+end component;
+component buf_reg is
+   port(
+      clk, reset: in std_logic;
+      clr_flag, set_flag: in std_logic; 
+      din: in std_logic_vector(7 downto 0);
+      dout: out std_logic_vector(7 downto 0);
+      flag: out std_logic
+   );
+end component;
+component baud_gen is
+   generic(
+      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
+  );
+   port(
+      clk, reset: in std_logic;
+      s_tick: out std_logic -- sampling tick
+   );
+end component;
+signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
+signal dout_rx, din_tx : std_logic_vector(7 downto 0);
+begin
+U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
+U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
+U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
+U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
+end structural;
\ No newline at end of file

From 6e3f0d101f7cce123ee95cc69cd3e8f79ba0750f Mon Sep 17 00:00:00 2001
From: EveliendeWolff <E.I.deWolff@student.tudelft.nl>
Date: Mon, 8 Jun 2020 14:53:07 +0200
Subject: [PATCH 2/6] uart part 1

---
 vhdl_source/uart.vhdl | 64 -------------------------------------------
 1 file changed, 64 deletions(-)
 delete mode 100644 vhdl_source/uart.vhdl

diff --git a/vhdl_source/uart.vhdl b/vhdl_source/uart.vhdl
deleted file mode 100644
index 736b92e..0000000
--- a/vhdl_source/uart.vhdl
+++ /dev/null
@@ -1,64 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity uart is
-	port (
-		clk, reset: in std_logic;
-		rx: in std_logic; -- input bit stream
-		tx: out std_logic; -- output bit stream
-		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
-		data_out: out std_logic_vector(7 downto 0); -- received byte
-		write_data: in std_logic; -- write to transmitter buffer 
-		read_data: in std_logic; -- read from receiver buffer 
-		new_data: out std_logic -- new data available
-	);
-end uart;
-
-architecture structural of uart is 
-component uart_rx is
-   port(
-      clk, reset: in std_logic;
-      rx: in std_logic; -- icoming serial bit stream
-      s_tick: in std_logic; -- sampling tick from baud rate generator
-      rx_done_tick: out std_logic; -- data frame completion tick
-      dout: out std_logic_vector(7 downto 0) -- data byte
-   );
-end component;
-component uart_tx is
-   port(
-      clk, reset: in std_logic;
-      tx_start: in std_logic; -- if '1' transmission starts
-      s_tick: in std_logic; -- sampling tick from baud rate generator
-      din: in std_logic_vector(7 downto 0); -- incoming data byte
-      tx_done_tick: out std_logic; -- data frame completion tick 
-      tx: out std_logic -- outcoming bit stream
-   );
-end component;
-component buf_reg is
-   port(
-      clk, reset: in std_logic;
-      clr_flag, set_flag: in std_logic; 
-      din: in std_logic_vector(7 downto 0);
-      dout: out std_logic_vector(7 downto 0);
-      flag: out std_logic
-   );
-end component;
-component baud_gen is
-   generic(
-      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
-  );
-   port(
-      clk, reset: in std_logic;
-      s_tick: out std_logic -- sampling tick
-   );
-end component;
-signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
-signal dout_rx, din_tx : std_logic_vector(7 downto 0);
-begin
-U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
-U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
-U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
-U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
-U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
-end structural;
\ No newline at end of file

From 6083e0ea22f7767e4b23f2407246f0774bbd2909 Mon Sep 17 00:00:00 2001
From: EveliendeWolff <E.I.deWolff@student.tudelft.nl>
Date: Mon, 8 Jun 2020 14:57:14 +0200
Subject: [PATCH 3/6] uart poging 2

---
 vhdl_source/uart.vhdl | 64 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 vhdl_source/uart.vhdl

diff --git a/vhdl_source/uart.vhdl b/vhdl_source/uart.vhdl
new file mode 100644
index 0000000..736b92e
--- /dev/null
+++ b/vhdl_source/uart.vhdl
@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity uart is
+	port (
+		clk, reset: in std_logic;
+		rx: in std_logic; -- input bit stream
+		tx: out std_logic; -- output bit stream
+		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
+		data_out: out std_logic_vector(7 downto 0); -- received byte
+		write_data: in std_logic; -- write to transmitter buffer 
+		read_data: in std_logic; -- read from receiver buffer 
+		new_data: out std_logic -- new data available
+	);
+end uart;
+
+architecture structural of uart is 
+component uart_rx is
+   port(
+      clk, reset: in std_logic;
+      rx: in std_logic; -- icoming serial bit stream
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      rx_done_tick: out std_logic; -- data frame completion tick
+      dout: out std_logic_vector(7 downto 0) -- data byte
+   );
+end component;
+component uart_tx is
+   port(
+      clk, reset: in std_logic;
+      tx_start: in std_logic; -- if '1' transmission starts
+      s_tick: in std_logic; -- sampling tick from baud rate generator
+      din: in std_logic_vector(7 downto 0); -- incoming data byte
+      tx_done_tick: out std_logic; -- data frame completion tick 
+      tx: out std_logic -- outcoming bit stream
+   );
+end component;
+component buf_reg is
+   port(
+      clk, reset: in std_logic;
+      clr_flag, set_flag: in std_logic; 
+      din: in std_logic_vector(7 downto 0);
+      dout: out std_logic_vector(7 downto 0);
+      flag: out std_logic
+   );
+end component;
+component baud_gen is
+   generic(
+      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
+  );
+   port(
+      clk, reset: in std_logic;
+      s_tick: out std_logic -- sampling tick
+   );
+end component;
+signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
+signal dout_rx, din_tx : std_logic_vector(7 downto 0);
+begin
+U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
+U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
+U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
+U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
+end structural;
\ No newline at end of file

From 43f5dc2a8cec94c4a9c0d99cc0ddb5f42d9e507b Mon Sep 17 00:00:00 2001
From: Your Name <stevenzhou200@hotmail.com>
Date: Mon, 8 Jun 2020 15:44:08 +0200
Subject: [PATCH 4/6] tbv2

---
 vhdl_source/Top.vhdl            |   8 +-
 vhdl_source/controller.vhdl     |   2 +-
 vhdl_source/controller.vhdl.bak | 280 ++++++++++++++++++--------------
 vhdl_source/robot.vhdl          |  10 +-
 vhdl_source/uart.vhdl           |   8 +-
 vhdl_source/uart.vhdl.bak       |  10 +-
 6 files changed, 175 insertions(+), 143 deletions(-)

diff --git a/vhdl_source/Top.vhdl b/vhdl_source/Top.vhdl
index bf55f0b..196029b 100644
--- a/vhdl_source/Top.vhdl
+++ b/vhdl_source/Top.vhdl
@@ -46,8 +46,8 @@ architecture structural of top is
 			write_data	: out std_logic; 
 			read_data	: out std_logic;  
 			new_data	: in std_logic;
-			data_out	: in std_logic_vector(7 downto 0);
-			data_in		: out std_logic_vector(7 downto 0);
+			data_received	: in std_logic_vector(7 downto 0);
+			data_send	: out std_logic_vector(7 downto 0);
 
 			motor_l_pwm     : out   std_logic;
 			motor_r_pwm     : out   std_logic
@@ -75,8 +75,8 @@ L2: robot port map(	clk=>clk,
 			mine_sensor =>mine_sensor,
 			motor_r_pwm=>motor_r_pwm,
 			motor_l_pwm=>motor_l_pwm,
-			data_in=>data_in_sig,
-			data_out=>data_out_sig,
+			data_send=>data_in_sig,
+			data_received=>data_out_sig,
 			write_data=>write_data_sig,
 			read_data=>read_data_sig,
 			new_data=>new_data_sig
diff --git a/vhdl_source/controller.vhdl b/vhdl_source/controller.vhdl
index 9d48efc..855182b 100644
--- a/vhdl_source/controller.vhdl
+++ b/vhdl_source/controller.vhdl
@@ -75,8 +75,8 @@ begin
 					reset_l_motor <= '1';
 					reset_r_motor <= '1';
 					read_data <= '0';
-					data_send <= "01101101";
 					write_data <= '1';
+					data_send <= "01101101";
 					next_state <= Sensor_check;
 				when Sensor_check=>
 					if (sensor="000") then
diff --git a/vhdl_source/controller.vhdl.bak b/vhdl_source/controller.vhdl.bak
index 54359a7..4ecf436 100644
--- a/vhdl_source/controller.vhdl.bak
+++ b/vhdl_source/controller.vhdl.bak
@@ -4,135 +4,163 @@ use IEEE.numeric_std.all;
 use IEEE.std_logic_1164.all;
 
 entity controller is
-port ( clk : in std_logic;
-reset : in std_logic;
-
-sensor_l : in std_logic;
-sensor_m : in std_logic;
-sensor_r : in std_logic;
-mine_detect: in std_logic;
-count_in : in std_logic_vector (19 downto 0);
-count_reset : out std_logic;
-
-motor_l_reset : out std_logic;
-motor_l_direction : out std_logic;
-
-motor_r_reset : out std_logic;
-motor_r_direction : out std_logic
-);
+
+	port ( clk : in std_logic;
+		reset : in std_logic;
+
+		sensor_l : in std_logic;
+		sensor_m : in std_logic;
+		sensor_r : in std_logic;
+
+		mine_detect: in std_logic;
+
+		write_data: out std_logic; 
+		read_data: out std_logic;  
+		new_data: in std_logic;
+		data_received: in std_logic_vector(7 downto 0);
+		data_send: out std_logic_vector(7 downto 0);
+
+		count_in : in std_logic_vector (19 downto 0);
+		count_reset : out std_logic;
+
+		motor_l_reset : out std_logic;
+		motor_l_direction : out std_logic;
+
+		motor_r_reset : out std_logic;
+		motor_r_direction : out std_logic
+		);
 end entity controller;
 
 architecture controller_behav of controller is
-type diff_states is (Startturn,Sensor_check,Wait_for_line);
-signal state, next_state: diff_states;
-signal sensor: std_logic_vector(2 downto 0); 
-signal mine : std_logic; -- using for being in state mine_detect.
-signal motorreset: std_logic;
-signal reset_l_motor, reset_r_motor: std_logic;
-begin
-sensor(2)<=sensor_l;
-sensor(1)<=sensor_m;
-sensor(0)<=sensor_r;
-ttl:process(sensor,state,mine_detect)
-  begin
-case state is
-when Startturn =>
-motor_l_direction <= '1';
-motor_r_direction <= '1';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-if(sensor="111") then
-next_state <= Wait_for_line;
-else next_state<=Startturn;
-end if;
-when Wait_for_line =>
-motor_l_direction <= '1';
-motor_r_direction <= '1';
-if(sensor="110") then
-next_state <= Sensor_check;
-else next_state <= Wait_for_line;
-end if;
-when Sensor_check=>
-if (sensor="000") then
-motor_l_direction <= '1';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-elsif(sensor= "001") then
-        motor_l_direction <= '0';
-        motor_r_direction <= '0';
-reset_l_motor <= '1';
-reset_r_motor <= '0';
-
-elsif(sensor= "010") then
-motor_l_direction <= '1';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-elsif(sensor= "011") then
-        motor_l_direction <= '0';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-elsif(sensor= "100") then
-motor_l_direction <= '1';
-        motor_r_direction <= '0';
-reset_r_motor <= '1';
-reset_l_motor <= '0';
-
-elsif(sensor= "101") then
-motor_l_direction <= '1';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-elsif(sensor= "110") then
-motor_l_direction <= '1';
-        motor_r_direction <= '1';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-elsif(sensor= "111") then
-motor_l_direction <= '1';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-
-else
-motor_l_direction <= '0';
-        motor_r_direction <= '0';
-reset_l_motor <= '0';
-reset_r_motor <= '0';
-        end if;
-if(mine_detect='1') then
-next_state<=Startturn;
-else
-next_state<=Sensor_check;
-end if;
-     end case;       
-end process;
-clk_sig: process(clk,reset)
+	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_signal);
+	signal state, next_state: diff_states;
+	signal sensor: std_logic_vector(2 downto 0); 
+	signal mine : std_logic; -- using for being in state mine_detect.
+	signal motorreset: std_logic;
+	signal reset_l_motor, reset_r_motor: std_logic;
 begin
-if (reset='1') then
-    count_reset <= '1';
-    motorreset <= '1';
-    state<=Sensor_check;
-    elsif (clk'event and clk='1') then
-state<=next_state;
-        if (unsigned(count_in) =1000000) then
-      count_reset <= '1';
-      motorreset <= '1';
-    else
-      count_reset <= '0';
-      motorreset <= '0';
-    end if;
-end if;
-end process;
-
-motor_l_reset <= reset_l_motor or motorreset;
-motor_r_reset <= reset_r_motor or motorreset;
+	sensor(2)<=sensor_l;
+	sensor(1)<=sensor_m;
+	sensor(0)<=sensor_r;
+	data_send <= "11100111";
+	read_data <= '1';
+	write_data <= '0';
+
+	ttl:process(sensor,state,mine_detect)
+  	begin
+			case state is
+				when Startturn =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+					if(sensor="111") then
+						next_state <= Wait_for_line;
+					else 
+						next_state <= Startturn;
+					end if;
+				when Wait_for_line =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+					if(sensor="110") then
+						next_state <= Mine_signal;
+					else 
+						next_state <= Wait_for_line;
+					end if;
+				when Mine_signal =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '1';
+					reset_r_motor <= '1';
+					read_data <= '0';
+					write_data <= '1';
+					data_send <= "01101101";
+					next_state <= Sensor_check;
+				when Sensor_check=>
+					if (sensor="000") then
+						motor_l_direction <= '1';
+        					motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "001") then
+        					motor_l_direction <= '0';
+       						motor_r_direction <= '0';
+						reset_l_motor <= '1';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "010") then
+						motor_l_direction <= '1';
+        					motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "011") then
+        					motor_l_direction <= '0';
+        					motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "100") then
+						motor_l_direction <= '1';
+        					motor_r_direction <= '0';
+						reset_r_motor <= '1';
+						reset_l_motor <= '0';
+
+					elsif(sensor= "101") then
+						motor_l_direction <= '1';
+        					motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "110") then
+						motor_l_direction <= '1';
+    						motor_r_direction <= '1';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					elsif(sensor= "111") then
+						motor_l_direction <= '1';
+   						motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+
+					else
+						motor_l_direction <= '0';
+        					motor_r_direction <= '0';
+						reset_l_motor <= '0';
+						reset_r_motor <= '0';
+        				end if;
+					if(mine_detect='1') then
+						next_state<=Startturn;
+					else
+						next_state<=Sensor_check;
+					end if;
+     			end case;       
+	end process;
+
+	clk_sig: process(clk,reset)
+	begin
+		if (reset='1') then
+    			count_reset <= '1';
+    			motorreset <= '1';
+    			state<=Sensor_check;
+    		elsif (clk'event and clk = '1') then
+			state<=next_state;
+        		if (unsigned(count_in) = 1000000) then
+      				count_reset <= '1';
+      				motorreset <= '1';
+    			else
+      				count_reset <= '0';
+      				motorreset <= '0';
+    			end if;
+		end if;
+	end process;
+
+	motor_l_reset <= reset_l_motor or motorreset;
+	motor_r_reset <= reset_r_motor or motorreset;
+
 
 end controller_behav;
diff --git a/vhdl_source/robot.vhdl b/vhdl_source/robot.vhdl
index 2fc18c7..8a5fd40 100644
--- a/vhdl_source/robot.vhdl
+++ b/vhdl_source/robot.vhdl
@@ -14,8 +14,8 @@ entity robot is
 		write_data	: out std_logic; 
 		read_data	: out std_logic;  
 		new_data	: in std_logic;
-		data_out	: in std_logic_vector(7 downto 0);
-		data_in		: out std_logic_vector(7 downto 0);
+		data_received	: in std_logic_vector(7 downto 0);
+		data_send	: out std_logic_vector(7 downto 0);
 
 		motor_l_pwm     : out   std_logic;
 		motor_r_pwm     : out   std_logic
@@ -36,7 +36,7 @@ architecture structural of robot is
 			read_data		: out std_logic;  
 			new_data		: in std_logic;
 			data_received		: in std_logic_vector(7 downto 0);
-			data_send			: out std_logic_vector(7 downto 0);
+			data_send		: out std_logic_vector(7 downto 0);
 
 			count_in		: in	std_logic_vector (19 downto 0);
 			count_reset		: out	std_logic;
@@ -129,8 +129,8 @@ L4: controller port map (	clk=>clk,
 				motor_r_reset=>motor_r_resets,
 				motor_l_direction=>motor_l_directions,
 				motor_r_direction=>motor_r_directions,
-				data_received=>data_out,
-				data_send=>data_in,
+				data_received=>data_received,
+				data_send=>data_send,
 				write_data=>write_data,
 				read_data=>read_data,
 				new_data=>new_data			
diff --git a/vhdl_source/uart.vhdl b/vhdl_source/uart.vhdl
index 736b92e..efa11be 100644
--- a/vhdl_source/uart.vhdl
+++ b/vhdl_source/uart.vhdl
@@ -5,7 +5,7 @@ use ieee.numeric_std.all;
 entity uart is
 	port (
 		clk, reset: in std_logic;
-		rx: in std_logic; -- input bit stream
+--		rx: in std_logic; -- input bit stream
 		tx: out std_logic; -- output bit stream
 		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
 		data_out: out std_logic_vector(7 downto 0); -- received byte
@@ -19,7 +19,7 @@ architecture structural of uart is
 component uart_rx is
    port(
       clk, reset: in std_logic;
-      rx: in std_logic; -- icoming serial bit stream
+--      rx: in std_logic; -- icoming serial bit stream
       s_tick: in std_logic; -- sampling tick from baud rate generator
       rx_done_tick: out std_logic; -- data frame completion tick
       dout: out std_logic_vector(7 downto 0) -- data byte
@@ -56,7 +56,9 @@ end component;
 signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
 signal dout_rx, din_tx : std_logic_vector(7 downto 0);
 begin
-U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+--U1: uart_rx port map (clk => clk, reset=> reset, 
+--rx=>rx,
+--s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
 U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
 U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
 U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
diff --git a/vhdl_source/uart.vhdl.bak b/vhdl_source/uart.vhdl.bak
index eb48554..e5189db 100644
--- a/vhdl_source/uart.vhdl.bak
+++ b/vhdl_source/uart.vhdl.bak
@@ -5,7 +5,7 @@ use ieee.numeric_std.all;
 entity uart is
 	port (
 		clk, reset: in std_logic;
-		rx: in std_logic; -- input bit stream
+--		rx: in std_logic; -- input bit stream
 		tx: out std_logic; -- output bit stream
 		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
 		data_out: out std_logic_vector(7 downto 0); -- received byte
@@ -19,7 +19,7 @@ architecture structural of uart is
 component uart_rx is
    port(
       clk, reset: in std_logic;
-      rx: in std_logic; -- icoming serial bit stream
+--      rx: in std_logic; -- icoming serial bit stream
       s_tick: in std_logic; -- sampling tick from baud rate generator
       rx_done_tick: out std_logic; -- data frame completion tick
       dout: out std_logic_vector(7 downto 0) -- data byte
@@ -56,9 +56,11 @@ end component;
 signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
 signal dout_rx, din_tx : std_logic_vector(7 downto 0);
 begin
-U1: uart_rx port map (clk => clk, reset=> reset, rx => rx, s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+U1: uart_rx port map (clk => clk, reset=> reset, 
+--rx=>rx,
+s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
 U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
 U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
-U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
+U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
 U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
 end structural;
\ No newline at end of file

From a3703fd5959a605133d6f185b5e8d8b908f38981 Mon Sep 17 00:00:00 2001
From: Your Name <stevenzhou200@hotmail.com>
Date: Mon, 8 Jun 2020 16:52:53 +0200
Subject: [PATCH 5/6] final_version_part_1

---
 vhdl_source/controller.vhdl     | 36 ++++++++++++++++++++++++---------
 vhdl_source/controller.vhdl.bak | 30 ++++++++++++++++++---------
 vhdl_source/uart.vhdl           |  4 +---
 vhdl_source/uart.vhdl.bak       |  4 ++--
 4 files changed, 49 insertions(+), 25 deletions(-)

diff --git a/vhdl_source/controller.vhdl b/vhdl_source/controller.vhdl
index 855182b..b728b80 100644
--- a/vhdl_source/controller.vhdl
+++ b/vhdl_source/controller.vhdl
@@ -32,7 +32,7 @@ entity controller is
 end entity controller;
 
 architecture controller_behav of controller is
-	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_signal);
+	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_revert,Mine_send);
 	signal state, next_state: diff_states;
 	signal sensor: std_logic_vector(2 downto 0); 
 	signal mine : std_logic; -- using for being in state mine_detect.
@@ -42,11 +42,8 @@ begin
 	sensor(2)<=sensor_l;
 	sensor(1)<=sensor_m;
 	sensor(0)<=sensor_r;
-	data_send <= "11111111";
-	read_data <= '1';
-	write_data <= '0';
 
-	ttl:process(sensor,state,mine_detect)
+	ttl:process(sensor,state,mine_detect, count_in)
   	begin
 			case state is
 				when Startturn =>
@@ -54,6 +51,9 @@ begin
 					motor_r_direction <= '1';
 					reset_l_motor <= '0';
 					reset_r_motor <= '0';
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if(sensor="111") then
 						next_state <= Wait_for_line;
 					else 
@@ -64,21 +64,37 @@ begin
 					motor_r_direction <= '1';
 					reset_l_motor <= '0';
 					reset_r_motor <= '0';
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if(sensor="110") then
-						next_state <= Mine_signal;
+						next_state <= Mine_revert;
 					else 
 						next_state <= Wait_for_line;
 					end if;
-				when Mine_signal =>
+				when Mine_revert =>
 					motor_l_direction <= '1';
 					motor_r_direction <= '1';
-					reset_l_motor <= '1';
-					reset_r_motor <= '1';
-					read_data <= '0';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+					if (unsigned(count_in) = 0) then
+						next_state <= Mine_send;
+					else
+						next_state <= Mine_revert;
+    					end if;
+				when Mine_send =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+      					read_data <= '0';
 					write_data <= '1';
 					data_send <= "01101101";
 					next_state <= Sensor_check;
 				when Sensor_check=>
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if (sensor="000") then
 						motor_l_direction <= '1';
         					motor_r_direction <= '0';
diff --git a/vhdl_source/controller.vhdl.bak b/vhdl_source/controller.vhdl.bak
index 4ecf436..92d6404 100644
--- a/vhdl_source/controller.vhdl.bak
+++ b/vhdl_source/controller.vhdl.bak
@@ -32,7 +32,7 @@ entity controller is
 end entity controller;
 
 architecture controller_behav of controller is
-	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_signal);
+	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_revert,Mine_send);
 	signal state, next_state: diff_states;
 	signal sensor: std_logic_vector(2 downto 0); 
 	signal mine : std_logic; -- using for being in state mine_detect.
@@ -42,11 +42,8 @@ begin
 	sensor(2)<=sensor_l;
 	sensor(1)<=sensor_m;
 	sensor(0)<=sensor_r;
-	data_send <= "11100111";
-	read_data <= '1';
-	write_data <= '0';
 
-	ttl:process(sensor,state,mine_detect)
+	ttl:process(sensor,state,mine_detect, count_in)
   	begin
 			case state is
 				when Startturn =>
@@ -65,20 +62,33 @@ begin
 					reset_l_motor <= '0';
 					reset_r_motor <= '0';
 					if(sensor="110") then
-						next_state <= Mine_signal;
+						next_state <= Mine_revert;
 					else 
 						next_state <= Wait_for_line;
 					end if;
-				when Mine_signal =>
+				when Mine_revert =>
 					motor_l_direction <= '1';
 					motor_r_direction <= '1';
-					reset_l_motor <= '1';
-					reset_r_motor <= '1';
-					read_data <= '0';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+					if (unsigned(count_in) = 0) then
+						next_state <= Mine_send;
+					else
+						next_state <= Mine_revert;
+    					end if;
+				when Mine_send =>
+					motor_l_direction <= '1';
+					motor_r_direction <= '1';
+					reset_l_motor <= '0';
+					reset_r_motor <= '0';
+      					read_data <= '0';
 					write_data <= '1';
 					data_send <= "01101101";
 					next_state <= Sensor_check;
 				when Sensor_check=>
+					read_data <= '1';
+					write_data <= '0';
+					data_send <= "11111111";
 					if (sensor="000") then
 						motor_l_direction <= '1';
         					motor_r_direction <= '0';
diff --git a/vhdl_source/uart.vhdl b/vhdl_source/uart.vhdl
index efa11be..1ee24ee 100644
--- a/vhdl_source/uart.vhdl
+++ b/vhdl_source/uart.vhdl
@@ -56,9 +56,7 @@ end component;
 signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
 signal dout_rx, din_tx : std_logic_vector(7 downto 0);
 begin
---U1: uart_rx port map (clk => clk, reset=> reset, 
---rx=>rx,
---s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+--U1: uart_rx port map (clk => clk, reset=> reset, rx=>rx,s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
 U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
 U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
 U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
diff --git a/vhdl_source/uart.vhdl.bak b/vhdl_source/uart.vhdl.bak
index e5189db..efa11be 100644
--- a/vhdl_source/uart.vhdl.bak
+++ b/vhdl_source/uart.vhdl.bak
@@ -56,9 +56,9 @@ end component;
 signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
 signal dout_rx, din_tx : std_logic_vector(7 downto 0);
 begin
-U1: uart_rx port map (clk => clk, reset=> reset, 
+--U1: uart_rx port map (clk => clk, reset=> reset, 
 --rx=>rx,
-s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
+--s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
 U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
 U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
 U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);

From 7c6faa34f232ae92cc7c4d5e7fb7b63f56c78f3b Mon Sep 17 00:00:00 2001
From: Your Name <stevenzhou200@hotmail.com>
Date: Mon, 8 Jun 2020 17:02:49 +0200
Subject: [PATCH 6/6] remove_bak

---
 vhdl_source/controller.vhdl.bak | 176 --------------------------------
 vhdl_source/uart.vhdl.bak       |  66 ------------
 2 files changed, 242 deletions(-)
 delete mode 100644 vhdl_source/controller.vhdl.bak
 delete mode 100644 vhdl_source/uart.vhdl.bak

diff --git a/vhdl_source/controller.vhdl.bak b/vhdl_source/controller.vhdl.bak
deleted file mode 100644
index 92d6404..0000000
--- a/vhdl_source/controller.vhdl.bak
+++ /dev/null
@@ -1,176 +0,0 @@
-library IEEE;
--- Hier komen de gebruikte libraries:
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity controller is
-
-	port ( clk : in std_logic;
-		reset : in std_logic;
-
-		sensor_l : in std_logic;
-		sensor_m : in std_logic;
-		sensor_r : in std_logic;
-
-		mine_detect: in std_logic;
-
-		write_data: out std_logic; 
-		read_data: out std_logic;  
-		new_data: in std_logic;
-		data_received: in std_logic_vector(7 downto 0);
-		data_send: out std_logic_vector(7 downto 0);
-
-		count_in : in std_logic_vector (19 downto 0);
-		count_reset : out std_logic;
-
-		motor_l_reset : out std_logic;
-		motor_l_direction : out std_logic;
-
-		motor_r_reset : out std_logic;
-		motor_r_direction : out std_logic
-		);
-end entity controller;
-
-architecture controller_behav of controller is
-	type diff_states is (Startturn,Sensor_check,Wait_for_line,Mine_revert,Mine_send);
-	signal state, next_state: diff_states;
-	signal sensor: std_logic_vector(2 downto 0); 
-	signal mine : std_logic; -- using for being in state mine_detect.
-	signal motorreset: std_logic;
-	signal reset_l_motor, reset_r_motor: std_logic;
-begin
-	sensor(2)<=sensor_l;
-	sensor(1)<=sensor_m;
-	sensor(0)<=sensor_r;
-
-	ttl:process(sensor,state,mine_detect, count_in)
-  	begin
-			case state is
-				when Startturn =>
-					motor_l_direction <= '1';
-					motor_r_direction <= '1';
-					reset_l_motor <= '0';
-					reset_r_motor <= '0';
-					if(sensor="111") then
-						next_state <= Wait_for_line;
-					else 
-						next_state <= Startturn;
-					end if;
-				when Wait_for_line =>
-					motor_l_direction <= '1';
-					motor_r_direction <= '1';
-					reset_l_motor <= '0';
-					reset_r_motor <= '0';
-					if(sensor="110") then
-						next_state <= Mine_revert;
-					else 
-						next_state <= Wait_for_line;
-					end if;
-				when Mine_revert =>
-					motor_l_direction <= '1';
-					motor_r_direction <= '1';
-					reset_l_motor <= '0';
-					reset_r_motor <= '0';
-					if (unsigned(count_in) = 0) then
-						next_state <= Mine_send;
-					else
-						next_state <= Mine_revert;
-    					end if;
-				when Mine_send =>
-					motor_l_direction <= '1';
-					motor_r_direction <= '1';
-					reset_l_motor <= '0';
-					reset_r_motor <= '0';
-      					read_data <= '0';
-					write_data <= '1';
-					data_send <= "01101101";
-					next_state <= Sensor_check;
-				when Sensor_check=>
-					read_data <= '1';
-					write_data <= '0';
-					data_send <= "11111111";
-					if (sensor="000") then
-						motor_l_direction <= '1';
-        					motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "001") then
-        					motor_l_direction <= '0';
-       						motor_r_direction <= '0';
-						reset_l_motor <= '1';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "010") then
-						motor_l_direction <= '1';
-        					motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "011") then
-        					motor_l_direction <= '0';
-        					motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "100") then
-						motor_l_direction <= '1';
-        					motor_r_direction <= '0';
-						reset_r_motor <= '1';
-						reset_l_motor <= '0';
-
-					elsif(sensor= "101") then
-						motor_l_direction <= '1';
-        					motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "110") then
-						motor_l_direction <= '1';
-    						motor_r_direction <= '1';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					elsif(sensor= "111") then
-						motor_l_direction <= '1';
-   						motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-
-					else
-						motor_l_direction <= '0';
-        					motor_r_direction <= '0';
-						reset_l_motor <= '0';
-						reset_r_motor <= '0';
-        				end if;
-					if(mine_detect='1') then
-						next_state<=Startturn;
-					else
-						next_state<=Sensor_check;
-					end if;
-     			end case;       
-	end process;
-
-	clk_sig: process(clk,reset)
-	begin
-		if (reset='1') then
-    			count_reset <= '1';
-    			motorreset <= '1';
-    			state<=Sensor_check;
-    		elsif (clk'event and clk = '1') then
-			state<=next_state;
-        		if (unsigned(count_in) = 1000000) then
-      				count_reset <= '1';
-      				motorreset <= '1';
-    			else
-      				count_reset <= '0';
-      				motorreset <= '0';
-    			end if;
-		end if;
-	end process;
-
-	motor_l_reset <= reset_l_motor or motorreset;
-	motor_r_reset <= reset_r_motor or motorreset;
-
-
-end controller_behav;
diff --git a/vhdl_source/uart.vhdl.bak b/vhdl_source/uart.vhdl.bak
deleted file mode 100644
index efa11be..0000000
--- a/vhdl_source/uart.vhdl.bak
+++ /dev/null
@@ -1,66 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity uart is
-	port (
-		clk, reset: in std_logic;
---		rx: in std_logic; -- input bit stream
-		tx: out std_logic; -- output bit stream
-		data_in: in std_logic_vector(7 downto 0); -- byte to be sent
-		data_out: out std_logic_vector(7 downto 0); -- received byte
-		write_data: in std_logic; -- write to transmitter buffer 
-		read_data: in std_logic; -- read from receiver buffer 
-		new_data: out std_logic -- new data available
-	);
-end uart;
-
-architecture structural of uart is 
-component uart_rx is
-   port(
-      clk, reset: in std_logic;
---      rx: in std_logic; -- icoming serial bit stream
-      s_tick: in std_logic; -- sampling tick from baud rate generator
-      rx_done_tick: out std_logic; -- data frame completion tick
-      dout: out std_logic_vector(7 downto 0) -- data byte
-   );
-end component;
-component uart_tx is
-   port(
-      clk, reset: in std_logic;
-      tx_start: in std_logic; -- if '1' transmission starts
-      s_tick: in std_logic; -- sampling tick from baud rate generator
-      din: in std_logic_vector(7 downto 0); -- incoming data byte
-      tx_done_tick: out std_logic; -- data frame completion tick 
-      tx: out std_logic -- outcoming bit stream
-   );
-end component;
-component buf_reg is
-   port(
-      clk, reset: in std_logic;
-      clr_flag, set_flag: in std_logic; 
-      din: in std_logic_vector(7 downto 0);
-      dout: out std_logic_vector(7 downto 0);
-      flag: out std_logic
-   );
-end component;
-component baud_gen is
-   generic(
-      M: integer := 326 -- baud rate divisor M = 50M/(16*9600)
-  );
-   port(
-      clk, reset: in std_logic;
-      s_tick: out std_logic -- sampling tick
-   );
-end component;
-signal s_tick_buf, rx_done_tick_buf, tx_done_tick, flag_buf_tx, tx_done_tick_buf: std_logic;
-signal dout_rx, din_tx : std_logic_vector(7 downto 0);
-begin
---U1: uart_rx port map (clk => clk, reset=> reset, 
---rx=>rx,
---s_tick=> s_tick_buf, rx_done_tick=> rx_done_tick_buf, dout=> dout_rx);
-U2: uart_tx port map (clk=> clk, reset=> reset, tx_start=> flag_buf_tx, s_tick => s_tick_buf, din => din_tx, tx_done_tick=> tx_done_tick_buf, tx=> tx);
-U3rx: buf_reg port map(clk=>clk, reset=> reset, clr_flag=> read_data, set_flag=>rx_done_tick_buf, din=> dout_rx, dout=>data_out, flag =>new_data);
-U4tx: buf_reg port map (clk=> clk, reset=> reset, clr_flag=> tx_done_tick_buf, set_flag => write_data, din=> data_in, dout=> din_tx, flag=> flag_buf_tx);
-U5: baud_gen port map (clk=>clk, reset => reset, s_tick =>s_tick_buf);
-end structural;
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