From a13864b835041353eb18c7a2d421c7a86e6d9309 Mon Sep 17 00:00:00 2001 From: Olasoji Date: Mon, 8 Jun 2020 23:07:20 +0200 Subject: [PATCH 1/3] Updated the minesensor there were a little to many states for the mine sensor, and some of them were redundant. So it has less states now. The counter is set such that the threshold for the mine is 10 khz and a asynchronous reset was added insted of synchronous. --- vhdl_source/mine_freq.vhdl | 96 ++++++++++++-------------------------- 1 file changed, 31 insertions(+), 65 deletions(-) diff --git a/vhdl_source/mine_freq.vhdl b/vhdl_source/mine_freq.vhdl index 1a8e984..94a4a48 100644 --- a/vhdl_source/mine_freq.vhdl +++ b/vhdl_source/mine_freq.vhdl @@ -13,85 +13,51 @@ end entity mine_freq; architecture behaviour of mine_freq is - type mine_state is ( mine, - no_mine, - reset_mine, - count_mine, - count_no_mine, - count_reset_mine, - count_reset_no_mine + type mine_state is ( + reset_state, + wait_for_high, + count_high ); signal state, new_state : mine_state; signal mine_count, new_mine_count : unsigned(19 downto 0); begin - process (clk) + process (reset,clk) begin - if (clk'event and clk = '1') then - if (reset = '1') then - state <= reset_mine; - else - state <= new_state; - end if ; - end if ; + if reset = '1' then + + state <= reset_state; + + elsif rising_edge(clk) then + state <= new_state; + new_mine_count <= mine_count + 1; + end if; end process ; - process (state, mine_sensor, clk) + process (state, mine_sensor,new_mine_count) begin case state is - when reset_mine => + when reset_state => mine_count <= (others => '0'); mine_detect <= '0'; - new_state <= count_no_mine; - when count_no_mine => - mine_count <= new_mine_count; - mine_detect <= '0'; - if (mine_sensor = '1' and unsigned(mine_count) > 5000) then - new_state <= mine; - elsif (mine_sensor = '1' and unsigned(mine_count) <= 5000) then - new_state <= no_mine; - else - new_state <= count_no_mine; - end if; - when count_mine => - mine_count <= new_mine_count; - mine_detect <= '1'; - if (mine_sensor = '1' and unsigned(mine_count) > 5000) then - new_state <= mine; - elsif (mine_sensor = '1' and unsigned(mine_count) <= 5000) then - new_state <= no_mine; - else - new_state <= count_mine; - end if; - when no_mine => - mine_detect <= '0'; - if (mine_sensor ='0') then + new_state <= wait_for_high; + when wait_for_high => + if mine_sensor = '1' then mine_count <= (others => '0'); - new_state <= count_reset_no_mine; - else - new_state <= no_mine; - end if; - when count_reset_no_mine => - mine_detect <= '0'; - mine_count <= (others => '0'); - new_state <= count_no_mine; - when mine => - mine_detect <= '1'; - if (mine_sensor ='0') then - mine_count <= (others => '0'); - new_state <= count_reset_mine; - else - new_state <= mine; - end if; - when count_reset_mine => - mine_detect <= '1'; - mine_count <= (others => '0'); - new_state <= count_mine; + new_state <= count_high; + end if; + when count_high => + mine_count <= new_mine_count; + if mine_sensor = '0' then + if (unsigned(mine_count) < 2500) then + mine_detect <= '0'; + else + mine_detect <= '1'; + end if; + new_state <= wait_for_high; + end if; end case; end process; - process(mine_count) - begin - new_mine_count <= mine_count + 1; - end process; + end architecture behaviour; \ No newline at end of file From 7e0b343102dfa298075858dcb9702ea1769c0058 Mon Sep 17 00:00:00 2001 From: Olasoji Date: Tue, 9 Jun 2020 11:41:01 +0200 Subject: [PATCH 2/3] refactor --- vhdl_source/mine_freq.vhdl | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/vhdl_source/mine_freq.vhdl b/vhdl_source/mine_freq.vhdl index 94a4a48..1837730 100644 --- a/vhdl_source/mine_freq.vhdl +++ b/vhdl_source/mine_freq.vhdl @@ -14,9 +14,9 @@ end entity mine_freq; architecture behaviour of mine_freq is type mine_state is ( - reset_state, - wait_for_high, - count_high + S0, + S1, + S2 ); signal state, new_state : mine_state; signal mine_count, new_mine_count : unsigned(19 downto 0); @@ -26,7 +26,7 @@ begin begin if reset = '1' then - state <= reset_state; + state <= S0; elsif rising_edge(clk) then state <= new_state; @@ -37,24 +37,24 @@ begin process (state, mine_sensor,new_mine_count) begin case state is - when reset_state => + when S0 => mine_count <= (others => '0'); mine_detect <= '0'; - new_state <= wait_for_high; - when wait_for_high => + new_state <= S1; + when S1 => if mine_sensor = '1' then mine_count <= (others => '0'); - new_state <= count_high; + new_state <= S2; end if; - when count_high => + when S2 => mine_count <= new_mine_count; if mine_sensor = '0' then - if (unsigned(mine_count) < 2500) then + if (unsigned(mine_count) < 2777) then mine_detect <= '0'; else mine_detect <= '1'; end if; - new_state <= wait_for_high; + new_state <= S1; end if; end case; end process; From 310e1ed4d8a7e045808acc98377a89c76c58e117 Mon Sep 17 00:00:00 2001 From: Olasoji Date: Tue, 9 Jun 2020 17:44:39 +0200 Subject: [PATCH 3/3] added testbench for mine sensor --- vhdl_source/mine_freq_tb.vhdl | 64 +++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 vhdl_source/mine_freq_tb.vhdl diff --git a/vhdl_source/mine_freq_tb.vhdl b/vhdl_source/mine_freq_tb.vhdl new file mode 100644 index 0000000..21f444e --- /dev/null +++ b/vhdl_source/mine_freq_tb.vhdl @@ -0,0 +1,64 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +entity mine_freq_tb is +end entity mine_freq_tb; + +architecture test of mine_freq_tb is + +component mine_freq is + port ( clk : in std_logic; + reset : in std_logic; + mine_sensor : in std_logic; + mine_detect : out std_logic + ); +end component mine_freq; + + signal clk, reset, mine_sensor, mine_detect : std_logic; +begin + DUT: mine_freq port map(clk,reset,mine_sensor,mine_detect); + process + begin + clk <= '0'; + wait for 10 ns; + clk <= '1'; + wait for 10 ns; + end process; + + + process begin + reset <= '1' ; + wait for 10 us ; + reset <= '0'; + wait for 600 us; + reset <= '1'; + wait ; + end process; + + process begin + mine_sensor <= '1'; + wait for 50 us; + mine_sensor <= '0'; + wait for 50 us; + + + mine_sensor <= '1'; + wait for 57us; + mine_sensor <= '0'; + wait for 57 us; + + mine_sensor <= '1'; + wait for 50 us; + mine_sensor <= '0'; + wait for 50 us; + + mine_sensor <= '1'; + wait for 57 us ; + mine_sensor <= '0'; + wait for 57 us; + end process; + + + + +end architecture test; \ No newline at end of file