From 99ed6b1fc5c0bd5f771fe73d62209a6fcea159fd Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Thu, 21 Nov 2024 13:16:56 +0300 Subject: [PATCH 01/12] cortexm: Allow toggling non-halting option via a runtime command --- src/target/cortexm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/target/cortexm.c b/src/target/cortexm.c index a6445de5561..0553d51f7bc 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -51,9 +51,11 @@ #define CORTEXM_MAX_REG_COUNT (CORTEXM_GENERAL_REG_COUNT + CORTEX_FLOAT_REG_COUNT + CORTEXM_TRUSTZONE_REG_COUNT) static bool cortexm_vector_catch(target_s *target, int argc, const char **argv); +static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv); const command_s cortexm_cmd_list[] = { {"vector_catch", cortexm_vector_catch, "Catch exception vectors"}, + {"mem_nohalt", cortexm_mem_nohalt, "Toggle halting during memory accesses (affects RTT)"}, {NULL, NULL, NULL}, }; @@ -1272,6 +1274,25 @@ static bool cortexm_vector_catch(target_s *target, int argc, const char **argv) return true; } +static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv) +{ + bool enable = false; + if (argc > 2) { + tc_printf(target, "Usage: monitor mem_nohalt "); + return false; + } + if ((argc == 2) && parse_enable_or_disable(argv[1], &enable)) { + if (enable) + target->target_options |= TOPT_NON_HALTING_MEM_IO; + else + target->target_options &= ~TOPT_NON_HALTING_MEM_IO; + return true; + } + tc_printf(target, "Target allows non-halting memory IO: %s\n", + target->target_options & TOPT_NON_HALTING_MEM_IO ? "yes" : "no"); + return true; +} + static bool cortexm_hostio_request(target_s *const target) { /* Read out the information from the target needed to complete the request */ From 738dd0ae2255c96fb8a5c50fbbb2284e0adb3816 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Mon, 30 Dec 2024 14:42:11 +0300 Subject: [PATCH 02/12] fixup! cortexm: Allow toggling non-halting option via a runtime command --- src/target/cortexm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/target/cortexm.c b/src/target/cortexm.c index 0553d51f7bc..ee8be6d9b6e 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -51,11 +51,16 @@ #define CORTEXM_MAX_REG_COUNT (CORTEXM_GENERAL_REG_COUNT + CORTEX_FLOAT_REG_COUNT + CORTEXM_TRUSTZONE_REG_COUNT) static bool cortexm_vector_catch(target_s *target, int argc, const char **argv); +#ifdef ENABLE_RTT static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv); +#include "rtt.h" +#endif const command_s cortexm_cmd_list[] = { {"vector_catch", cortexm_vector_catch, "Catch exception vectors"}, +#ifdef ENABLE_RTT {"mem_nohalt", cortexm_mem_nohalt, "Toggle halting during memory accesses (affects RTT)"}, +#endif {NULL, NULL, NULL}, }; @@ -1274,6 +1279,7 @@ static bool cortexm_vector_catch(target_s *target, int argc, const char **argv) return true; } +#ifdef ENABLE_RTT static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv) { bool enable = false; @@ -1286,6 +1292,9 @@ static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv) target->target_options |= TOPT_NON_HALTING_MEM_IO; else target->target_options &= ~TOPT_NON_HALTING_MEM_IO; + /* Force reapplying halt settings in rtt.c */ + rtt_found = false; + return true; } tc_printf(target, "Target allows non-halting memory IO: %s\n", @@ -1293,6 +1302,8 @@ static bool cortexm_mem_nohalt(target_s *target, int argc, const char **argv) return true; } +#endif + static bool cortexm_hostio_request(target_s *const target) { /* Read out the information from the target needed to complete the request */ From 87fb5b31ec68e0492b99bf93d6b003f93905725b Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 26 Oct 2024 11:12:46 +0300 Subject: [PATCH 03/12] stm32g0: Enable non-halting SRAM access for RTT on G0/C0 series * Tested on STM32G071RB --- src/target/stm32g0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/stm32g0.c b/src/target/stm32g0.c index 671b1b9d6d8..79df1127476 100644 --- a/src/target/stm32g0.c +++ b/src/target/stm32g0.c @@ -299,6 +299,9 @@ bool stm32g0_probe(target_s *target) return false; target_add_ram32(target, RAM_START, ram_size); + /* On this SoC, Cortex-M0+ allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; + /* Even dual Flash bank devices have a contiguous Flash memory space */ stm32g0_add_flash(target, FLASH_START, flash_size, FLASH_PAGE_SIZE); From 565c0e584f1916ada2a30c0abb283d31c1cf6589 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 16 Nov 2024 21:07:14 +0300 Subject: [PATCH 04/12] stm32f1: Enable non-halting SRAM access for RTT on AT32F403A/F407 --- src/target/stm32f1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index 318812783ee..af6a05ed401 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -494,6 +494,8 @@ static bool at32f403a_407_detect(target_s *target, const uint16_t part_id) } // All parts have 96 KiB SRAM target_add_ram32(target, STM32F1_SRAM_BASE, 96U * 1024U); + /* On AT32F403A/F407 SoC, Cortex-M4F allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; target->driver = "AT32F403A/407"; target->part_id = part_id; target->target_options |= STM32F1_TOPT_32BIT_WRITES; From dad91baec50bbc4aed5390fa45aae888f5f08f71 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 23 Nov 2024 15:03:05 +0300 Subject: [PATCH 05/12] stm32f1: Enable non-halting SRAM access for RTT on some GD32 series * Tested chips include GD32F103CB, GD32F303CC, GD32E508ZE --- src/target/stm32f1.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index af6a05ed401..fdc4e3b565d 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -286,8 +286,10 @@ bool gd32f1_probe(target_s *target) switch (device_id) { case 0x414U: /* GD32F30x_HD, High density */ case 0x430U: /* GD32F30x_XD, XL-density */ - target->driver = "GD32F3"; + target->driver = "GD32F3 HD/XD"; block_size = 0x800; + /* On this SoC, Cortex-M4F allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; break; case 0x418U: /* Connectivity Line */ target->driver = "GD32F2"; @@ -297,14 +299,19 @@ bool gd32f1_probe(target_s *target) if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M23) target->driver = "GD32E230"; /* GD32E230, 64 KiB max in 1 KiB pages */ else if ((target->cpuid & CORTEX_CPUID_PARTNO_MASK) == CORTEX_M4) { - target->driver = "GD32F3"; + target->driver = "GD32F3 MD"; block_size = 0x800; - } else + } else { target->driver = "GD32F1"; /* GD32F103, 1 KiB pages */ + /* On this SoC, Cortex-M3 allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; + } break; case 0x444U: /* GD32E50x_CL, 512 KiB max in 8 KiB pages */ target->driver = "GD32E5"; block_size = 0x2000; + /* On this SoC, Cortex-M33 allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; break; default: return false; From 7948f1b0c33d87661af6f763a370e0d1221d7796 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Mon, 6 Jan 2025 06:40:35 +0300 Subject: [PATCH 06/12] stm32l4: Enable non-halting SRAM access for RTT on STM32G47x --- src/target/stm32l4.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/target/stm32l4.c b/src/target/stm32l4.c index efc35627edf..feda4e6bbdd 100644 --- a/src/target/stm32l4.c +++ b/src/target/stm32l4.c @@ -847,6 +847,10 @@ static bool stm32l4_attach(target_s *const target) } else stm32l4_add_flash(target, STM32L4_FLASH_BANK_1_BASE, flash_len * 1024U, 0x800, UINT32_MAX); + /* On STM32G47x SoC, Cortex-M4F allows SRAM access without halting */ + if (device->device_id == ID_STM32G47) + target->target_options |= TOPT_NON_HALTING_MEM_IO; + /* Clear all errors in the status register. */ stm32l4_flash_write32(target, FLASH_SR, stm32l4_flash_read32(target, FLASH_SR)); return true; From 527b78b1f9b482b60549934987be9710d064487a Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sat, 11 Jan 2025 17:48:09 +0300 Subject: [PATCH 07/12] stm32f1: Enable non-halting SRAM access for RTT on STM32F1/F3/F0 (blanket) * Tested on STM32F103 and STM32F072 --- src/target/stm32f1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index fdc4e3b565d..744f897b0b6 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -1017,6 +1017,9 @@ bool stm32f1_probe(target_s *target) stm32f1_add_flash(target, STM32F1_FLASH_BANK1_BASE, flash_size, block_size); target_add_commands(target, stm32f1_cmd_list, target->driver); + /* On STM32F1 (F3, F0) SoC, Cortex-M3 (M4F, M0) allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; + /* Now we have a stable debug environment, make sure the WDTs + WFI and WFE instructions can't cause problems */ return stm32f1_configure_dbgmcu(target, dbgmcu_config_taddr); } From 43db4656389e72e7cdee9bf914ee05919d8f9f8d Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 19 Jan 2025 20:10:18 +0300 Subject: [PATCH 08/12] stm32f4: Enable non-halting SRAM access for RTT on STM32F4 series --- src/target/stm32f4.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/target/stm32f4.c b/src/target/stm32f4.c index c2aef553f10..d45210d7786 100644 --- a/src/target/stm32f4.c +++ b/src/target/stm32f4.c @@ -486,6 +486,10 @@ static bool stm32f4_attach(target_s *const target) } } + /* On STM32F4 SoC, Cortex-M4F allows SRAM access without halting */ + if (!is_f7 && target->part_id != ID_STM32F20X) + target->target_options |= TOPT_NON_HALTING_MEM_IO; + /* Now we have a base RAM map, rebuild the Flash map */ uint8_t split = 0; uint32_t bank_length; From 66fecf2be011a124e08a624f1146ba246b955513 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 19 Jan 2025 20:30:40 +0300 Subject: [PATCH 09/12] nrf51: Enable non-halting SRAM access for RTT on nRF52 series --- src/target/nrf51.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/target/nrf51.c b/src/target/nrf51.c index 7400254f57f..b95e0f08721 100644 --- a/src/target/nrf51.c +++ b/src/target/nrf51.c @@ -144,6 +144,8 @@ bool nrf51_probe(target_s *t) uint32_t ram_size = target_mem32_read32(t, NRF52_INFO_RAM); t->driver = "nRF52"; t->target_options |= TOPT_INHIBIT_NRST; + /* On nRF52 SoC, Cortex-M4F allows SRAM access without halting */ + t->target_options |= TOPT_NON_HALTING_MEM_IO; target_add_ram32(t, 0x20000000U, ram_size * 1024U); nrf51_add_flash(t, 0, page_size * code_size, page_size); nrf51_add_flash(t, NRF51_UICR, page_size, page_size); From 44827a170588234b650932062b7fb2fb3f32e7d9 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Wed, 17 Dec 2025 21:30:24 +0300 Subject: [PATCH 10/12] nrf54l: Enable non-halting SRAM access for RTT on nRF54L series --- src/target/nrf54l.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/target/nrf54l.c b/src/target/nrf54l.c index 3d411d0a6b5..0659794051e 100644 --- a/src/target/nrf54l.c +++ b/src/target/nrf54l.c @@ -118,6 +118,8 @@ bool nrf54l_probe(target_s *target) case NRF54L_PARTNO: target->driver = "nRF54L"; target->target_options |= TOPT_INHIBIT_NRST; + /* On nRF54L SoC, Cortex-M33 allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; break; default: return false; From 3f5a51b880f4558c76a0be4df59b97d2c0097eb9 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Wed, 17 Dec 2025 21:45:36 +0300 Subject: [PATCH 11/12] stm32f1: Enable non-halting SRAM access for RTT on AT32F425 --- src/target/stm32f1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index 744f897b0b6..45da0931f73 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -686,6 +686,8 @@ static bool at32f425_detect(target_s *target, const uint16_t part_id) #endif // All parts have 20 KiB SRAM target_add_ram32(target, 0x20000000, 20U * 1024U); + /* On AT32F425 SoC, Cortex-M4 allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; target->driver = "AT32F425"; target->part_id = part_id; target->target_options |= STM32F1_TOPT_32BIT_WRITES; From a39ae13847a4718f42da54e4746aebce461bf43d Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Wed, 17 Dec 2025 22:00:24 +0300 Subject: [PATCH 12/12] at32f43x: Enable non-halting SRAM access for RTT on AT32F435/F437 --- src/target/at32f43x.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/target/at32f43x.c b/src/target/at32f43x.c index 29d4ba21ced..8a6a47d0804 100644 --- a/src/target/at32f43x.c +++ b/src/target/at32f43x.c @@ -299,6 +299,9 @@ static bool at32f43_detect(target_s *target, const uint16_t part_id) target->attach = at32f43_attach; target->detach = at32f43_detach; + /* On AT32F435/F437 SoC, Cortex-M4F allows SRAM access without halting */ + target->target_options |= TOPT_NON_HALTING_MEM_IO; + at32f43_configure_dbgmcu(target); return true; }