diff --git a/src/target/jep106.h b/src/target/jep106.h
index 1dd626b7669..e37c83b79b4 100644
--- a/src/target/jep106.h
+++ b/src/target/jep106.h
@@ -69,10 +69,11 @@
 #define JEP106_MANUFACTURER_RENESAS      0x423U /* Renesas */
 #define JEP106_MANUFACTURER_XILINX       0x309U /* Xilinx - Technically 0x049, but they use Ikanos Communications' code */
 /*
- * This JEP code should belong to "Andes Technology Corporation", but is used on RISC-V by GigaDevice,
- * so in the unlikely event we need to support chips by them, here be dragons.
+ * This JEP code is used on RISC-V by GigaDevice, because
+ * "Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology and Andes Technology."
  */
-#define JEP106_MANUFACTURER_RV_GIGADEVICE 0x61eU
+#define JEP106_MANUFACTURER_ANDES  0x61eU /* Andes Technology Corporation */
+#define JEP106_MANUFACTURER_NUCLEI 0xa36U /* Nuclei System Technology */
 
 /*
  * Used by WCH (WinChipHead) aka Nanjing Qinheng Microelectronics
diff --git a/src/target/jtag_devs.c b/src/target/jtag_devs.c
index d388f043a8a..1830de43e86 100644
--- a/src/target/jtag_devs.c
+++ b/src/target/jtag_devs.c
@@ -410,11 +410,19 @@ const jtag_dev_descr_s dev_descr[] = {
 		.idcode = 0x0000563dU,
 		.idmask = 0x0fffffffU,
 #if ENABLE_DEBUG == 1
-		.descr = "RISC-V debug v0.13.",
+		.descr = "Andes Tech RISC-V DTM.",
 #endif
 		.handler = riscv_jtag_dtm_handler,
 	},
+	{
+		.idcode = 0x00307a6dU,
+		.idmask = 0x0fffffffU,
+#if ENABLE_DEBUG == 1
+		.descr = "Nuclei Systems RISC-V DTM.",
 #endif
+		.handler = riscv_jtag_dtm_handler,
+	},
+#endif // CONFIG_RISCV
 #if defined(CONFIG_CORTEXAR) && defined(CONFIG_TI_ICEPICK)
 	{
 		.idcode = 0x0b90002fU,
diff --git a/src/target/riscv32.c b/src/target/riscv32.c
index aee1d676974..f77cf410a43 100644
--- a/src/target/riscv32.c
+++ b/src/target/riscv32.c
@@ -89,18 +89,21 @@ bool riscv32_probe(target_s *const target)
 	target->breakwatch_clear = riscv32_breakwatch_clear;
 
 	switch (target->designer_code) {
-	case JEP106_MANUFACTURER_RV_GIGADEVICE:
+	case JEP106_MANUFACTURER_ANDES:
 		PROBE(gd32vf1_probe);
 		break;
+	case JEP106_MANUFACTURER_NUCLEI:
+		PROBE(gd32vw5_probe);
+		break;
 	case JEP106_MANUFACTURER_RASPBERRY:
 		PROBE(rp2350_probe);
 		break;
-	default:
-		break;
 	case JEP106_MANUFACTURER_WCH:
 		PROBE(ch32v003x_probe);
 		PROBE(ch32vx_probe);
 		break;
+	default:
+		break;
 	}
 
 #if CONFIG_BMDA == 0
diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
index 4367545178f..b51f910ce2b 100644
--- a/src/target/stm32f1.c
+++ b/src/target/stm32f1.c
@@ -393,6 +393,21 @@ static void gd32vf1_detach(target_s *const target)
 	/* Now defer to the normal Cortex-M detach routine to complete the detach */
 	riscv_detach(target);
 }
+
+/* Identify RISC-V GD32VW5 chips */
+bool gd32vw5_probe(target_s *const target)
+{
+	const uint16_t device_id = target_mem32_read32(target, GD32E5_DBGMCU_BASE) & 0xfffU;
+	const uint32_t signature = target_mem32_read32(target, GD32Fx_FLASHSIZE);
+	const uint16_t flash_size = signature & 0xffffU;
+	const uint16_t ram_size = signature >> 16U;
+	DEBUG_WARN("Stub for detection of GD32VW553. DBG_ID=0x%x, RAM=%u, flash=%u\n", device_id, ram_size, flash_size);
+	target->driver = "GD32VW5";
+	target->part_id = device_id;
+	target_add_ram32(target, STM32F1_SRAM_BASE, ram_size * 1024U);
+	target_add_ram32(target, STM32F1_FLASH_BANK1_BASE, flash_size * 1024U);
+	return true;
+}
 #endif
 #endif
 
@@ -1139,7 +1154,7 @@ static bool stm32f1_flash_write(
 
 		target_mem32_write32(target, STM32F1_FPEC_CTRL, STM32F1_FPEC_PG);
 		/* Use the target API instead of a direct Cortex-M call for GD32VF103 parts */
-		if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U)
+		if (target->designer_code == JEP106_MANUFACTURER_ANDES && target->cpuid == 0x80000022U)
 			target_mem32_write(target, dest, src, offset);
 		else
 			cortexm_mem_write_aligned(target, dest, src, offset, psize);
@@ -1157,7 +1172,7 @@ static bool stm32f1_flash_write(
 
 		target_mem32_write32(target, STM32F1_FPEC_CTRL + STM32F1_FPEC_BANK2_OFFSET, STM32F1_FPEC_PG);
 		/* Use the target API instead of a direct Cortex-M call for GD32VF103 parts */
-		if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U)
+		if (target->designer_code == JEP106_MANUFACTURER_ANDES && target->cpuid == 0x80000022U)
 			target_mem32_write(target, dest + offset, data + offset, remainder);
 		else
 			cortexm_mem_write_aligned(target, dest + offset, data + offset, remainder, psize);
diff --git a/src/target/target_probe.c b/src/target/target_probe.c
index 0171dccb644..49bc3fc0845 100644
--- a/src/target/target_probe.c
+++ b/src/target/target_probe.c
@@ -114,6 +114,7 @@ TARGET_PROBE_WEAK_NOP(efm32_probe)
 TARGET_PROBE_WEAK_NOP(gd32f1_probe)
 TARGET_PROBE_WEAK_NOP(gd32f4_probe)
 TARGET_PROBE_WEAK_NOP(gd32vf1_probe)
+TARGET_PROBE_WEAK_NOP(gd32vw5_probe)
 TARGET_PROBE_WEAK_NOP(hc32l110_probe)
 TARGET_PROBE_WEAK_NOP(imxrt_probe)
 TARGET_PROBE_WEAK_NOP(ke04_probe)
diff --git a/src/target/target_probe.h b/src/target/target_probe.h
index 9c906cb3ef0..932fe8f0632 100644
--- a/src/target/target_probe.h
+++ b/src/target/target_probe.h
@@ -65,6 +65,7 @@ bool ch32vx_probe(target_s *target);
 bool gd32f1_probe(target_s *target);
 bool gd32f4_probe(target_s *target);
 bool gd32vf1_probe(target_s *target);
+bool gd32vw5_probe(target_s *target);
 bool hc32l110_probe(target_s *target);
 bool imxrt_probe(target_s *target);
 bool ke04_probe(target_s *target);