From d32915373dc2a87a93136777764371bb12f947b7 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 1 Feb 2026 16:04:07 +0300 Subject: [PATCH 1/3] riscv32: move the `default` case down in riscv32_probe --- src/target/riscv32.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/target/riscv32.c b/src/target/riscv32.c index aee1d676974..22153486940 100644 --- a/src/target/riscv32.c +++ b/src/target/riscv32.c @@ -95,12 +95,12 @@ bool riscv32_probe(target_s *const target) case JEP106_MANUFACTURER_RASPBERRY: PROBE(rp2350_probe); break; - default: - break; case JEP106_MANUFACTURER_WCH: PROBE(ch32v003x_probe); PROBE(ch32vx_probe); break; + default: + break; } #if CONFIG_BMDA == 0 From fcce49ca6b0ebf5d45125c80e8c84002686d35c2 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 1 Feb 2026 15:59:25 +0300 Subject: [PATCH 2/3] misc: Attribute JEP-106 code 0x61e to Andes Technology Corporation * The value was used internally by BMD as RV_GIGADEVICE, but it does not belong to Gigadevice (SoC vendor) or to Nucleisys (processor vendor). This is visible on JTAG TAP IDCODE of DTM and RISC-V mvendorid CSR of GD32VF103 SoC. --- src/target/jep106.h | 6 +++--- src/target/jtag_devs.c | 2 +- src/target/riscv32.c | 2 +- src/target/stm32f1.c | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/target/jep106.h b/src/target/jep106.h index 1dd626b7669..e4a100fb2fb 100644 --- a/src/target/jep106.h +++ b/src/target/jep106.h @@ -69,10 +69,10 @@ #define JEP106_MANUFACTURER_RENESAS 0x423U /* Renesas */ #define JEP106_MANUFACTURER_XILINX 0x309U /* Xilinx - Technically 0x049, but they use Ikanos Communications' code */ /* - * This JEP code should belong to "Andes Technology Corporation", but is used on RISC-V by GigaDevice, - * so in the unlikely event we need to support chips by them, here be dragons. + * This JEP code is used on RISC-V by GigaDevice, because + * "Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology and Andes Technology." */ -#define JEP106_MANUFACTURER_RV_GIGADEVICE 0x61eU +#define JEP106_MANUFACTURER_ANDES 0x61eU /* Andes Technology Corporation */ /* * Used by WCH (WinChipHead) aka Nanjing Qinheng Microelectronics diff --git a/src/target/jtag_devs.c b/src/target/jtag_devs.c index d388f043a8a..13f303bd557 100644 --- a/src/target/jtag_devs.c +++ b/src/target/jtag_devs.c @@ -410,7 +410,7 @@ const jtag_dev_descr_s dev_descr[] = { .idcode = 0x0000563dU, .idmask = 0x0fffffffU, #if ENABLE_DEBUG == 1 - .descr = "RISC-V debug v0.13.", + .descr = "Andes Tech RISC-V DTM.", #endif .handler = riscv_jtag_dtm_handler, }, diff --git a/src/target/riscv32.c b/src/target/riscv32.c index 22153486940..995e84004a9 100644 --- a/src/target/riscv32.c +++ b/src/target/riscv32.c @@ -89,7 +89,7 @@ bool riscv32_probe(target_s *const target) target->breakwatch_clear = riscv32_breakwatch_clear; switch (target->designer_code) { - case JEP106_MANUFACTURER_RV_GIGADEVICE: + case JEP106_MANUFACTURER_ANDES: PROBE(gd32vf1_probe); break; case JEP106_MANUFACTURER_RASPBERRY: diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index 4367545178f..621bf5d2c5e 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -1139,7 +1139,7 @@ static bool stm32f1_flash_write( target_mem32_write32(target, STM32F1_FPEC_CTRL, STM32F1_FPEC_PG); /* Use the target API instead of a direct Cortex-M call for GD32VF103 parts */ - if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U) + if (target->designer_code == JEP106_MANUFACTURER_ANDES && target->cpuid == 0x80000022U) target_mem32_write(target, dest, src, offset); else cortexm_mem_write_aligned(target, dest, src, offset, psize); @@ -1157,7 +1157,7 @@ static bool stm32f1_flash_write( target_mem32_write32(target, STM32F1_FPEC_CTRL + STM32F1_FPEC_BANK2_OFFSET, STM32F1_FPEC_PG); /* Use the target API instead of a direct Cortex-M call for GD32VF103 parts */ - if (target->designer_code == JEP106_MANUFACTURER_RV_GIGADEVICE && target->cpuid == 0x80000022U) + if (target->designer_code == JEP106_MANUFACTURER_ANDES && target->cpuid == 0x80000022U) target_mem32_write(target, dest + offset, data + offset, remainder); else cortexm_mem_write_aligned(target, dest + offset, data + offset, remainder, psize); From a56c1740b89ebf990f8a0de4f92cff45c1f3fe22 Mon Sep 17 00:00:00 2001 From: ALTracer <11005378+ALTracer@users.noreply.github.com> Date: Sun, 1 Feb 2026 16:10:52 +0300 Subject: [PATCH 3/3] riscv32, jtag: Detect Nucleisys DTM of GD32VW553 * Proper JEP-106 value of 0xa36 belonging to Nuclei Systems Technology * 307 is related to Nuclei N307 processor core --- src/target/jep106.h | 3 ++- src/target/jtag_devs.c | 8 ++++++++ src/target/riscv32.c | 3 +++ src/target/stm32f1.c | 15 +++++++++++++++ src/target/target_probe.c | 1 + src/target/target_probe.h | 1 + 6 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/target/jep106.h b/src/target/jep106.h index e4a100fb2fb..e37c83b79b4 100644 --- a/src/target/jep106.h +++ b/src/target/jep106.h @@ -72,7 +72,8 @@ * This JEP code is used on RISC-V by GigaDevice, because * "Note: The Bumblebee core used for this MCU is jointly developed by Nuclei System Technology and Andes Technology." */ -#define JEP106_MANUFACTURER_ANDES 0x61eU /* Andes Technology Corporation */ +#define JEP106_MANUFACTURER_ANDES 0x61eU /* Andes Technology Corporation */ +#define JEP106_MANUFACTURER_NUCLEI 0xa36U /* Nuclei System Technology */ /* * Used by WCH (WinChipHead) aka Nanjing Qinheng Microelectronics diff --git a/src/target/jtag_devs.c b/src/target/jtag_devs.c index 13f303bd557..1830de43e86 100644 --- a/src/target/jtag_devs.c +++ b/src/target/jtag_devs.c @@ -414,7 +414,15 @@ const jtag_dev_descr_s dev_descr[] = { #endif .handler = riscv_jtag_dtm_handler, }, + { + .idcode = 0x00307a6dU, + .idmask = 0x0fffffffU, +#if ENABLE_DEBUG == 1 + .descr = "Nuclei Systems RISC-V DTM.", #endif + .handler = riscv_jtag_dtm_handler, + }, +#endif // CONFIG_RISCV #if defined(CONFIG_CORTEXAR) && defined(CONFIG_TI_ICEPICK) { .idcode = 0x0b90002fU, diff --git a/src/target/riscv32.c b/src/target/riscv32.c index 995e84004a9..f77cf410a43 100644 --- a/src/target/riscv32.c +++ b/src/target/riscv32.c @@ -92,6 +92,9 @@ bool riscv32_probe(target_s *const target) case JEP106_MANUFACTURER_ANDES: PROBE(gd32vf1_probe); break; + case JEP106_MANUFACTURER_NUCLEI: + PROBE(gd32vw5_probe); + break; case JEP106_MANUFACTURER_RASPBERRY: PROBE(rp2350_probe); break; diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c index 621bf5d2c5e..b51f910ce2b 100644 --- a/src/target/stm32f1.c +++ b/src/target/stm32f1.c @@ -393,6 +393,21 @@ static void gd32vf1_detach(target_s *const target) /* Now defer to the normal Cortex-M detach routine to complete the detach */ riscv_detach(target); } + +/* Identify RISC-V GD32VW5 chips */ +bool gd32vw5_probe(target_s *const target) +{ + const uint16_t device_id = target_mem32_read32(target, GD32E5_DBGMCU_BASE) & 0xfffU; + const uint32_t signature = target_mem32_read32(target, GD32Fx_FLASHSIZE); + const uint16_t flash_size = signature & 0xffffU; + const uint16_t ram_size = signature >> 16U; + DEBUG_WARN("Stub for detection of GD32VW553. DBG_ID=0x%x, RAM=%u, flash=%u\n", device_id, ram_size, flash_size); + target->driver = "GD32VW5"; + target->part_id = device_id; + target_add_ram32(target, STM32F1_SRAM_BASE, ram_size * 1024U); + target_add_ram32(target, STM32F1_FLASH_BANK1_BASE, flash_size * 1024U); + return true; +} #endif #endif diff --git a/src/target/target_probe.c b/src/target/target_probe.c index 0171dccb644..49bc3fc0845 100644 --- a/src/target/target_probe.c +++ b/src/target/target_probe.c @@ -114,6 +114,7 @@ TARGET_PROBE_WEAK_NOP(efm32_probe) TARGET_PROBE_WEAK_NOP(gd32f1_probe) TARGET_PROBE_WEAK_NOP(gd32f4_probe) TARGET_PROBE_WEAK_NOP(gd32vf1_probe) +TARGET_PROBE_WEAK_NOP(gd32vw5_probe) TARGET_PROBE_WEAK_NOP(hc32l110_probe) TARGET_PROBE_WEAK_NOP(imxrt_probe) TARGET_PROBE_WEAK_NOP(ke04_probe) diff --git a/src/target/target_probe.h b/src/target/target_probe.h index 9c906cb3ef0..932fe8f0632 100644 --- a/src/target/target_probe.h +++ b/src/target/target_probe.h @@ -65,6 +65,7 @@ bool ch32vx_probe(target_s *target); bool gd32f1_probe(target_s *target); bool gd32f4_probe(target_s *target); bool gd32vf1_probe(target_s *target); +bool gd32vw5_probe(target_s *target); bool hc32l110_probe(target_s *target); bool imxrt_probe(target_s *target); bool ke04_probe(target_s *target);