diff --git a/dependencies/diplomacy b/dependencies/diplomacy
index edf375300d9..fe5e131d4fc 160000
--- a/dependencies/diplomacy
+++ b/dependencies/diplomacy
@@ -1 +1 @@
-Subproject commit edf375300d99a4c260a214d7c1553de0040771d7
+Subproject commit fe5e131d4fc8adec14a3ce4a4935bb5c0a269871
diff --git a/src/main/scala/amba/axi4/Fragmenter.scala b/src/main/scala/amba/axi4/Fragmenter.scala
index 85505374088..e5473801751 100644
--- a/src/main/scala/amba/axi4/Fragmenter.scala
+++ b/src/main/scala/amba/axi4/Fragmenter.scala
@@ -78,7 +78,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
 
         // We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
         // !!! think about this more -- what if illegal?
-        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
+        val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).view.mapValues(_.flatMap(_._2)).toMap
         val reductionMask = AddressDecoder(sizes1.values.toList)
         val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address
           (AddressSet.unify(a.map(_.widen(~reductionMask)).distinct).map(_.contains(addr)).reduce(_||_), v.U)
diff --git a/src/main/scala/amba/axi4/IdIndexer.scala b/src/main/scala/amba/axi4/IdIndexer.scala
index 4687d5dc0f8..9bf48f297e2 100644
--- a/src/main/scala/amba/axi4/IdIndexer.scala
+++ b/src/main/scala/amba/axi4/IdIndexer.scala
@@ -54,7 +54,7 @@ class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
       val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil
       mp.copy(
         echoFields = field ++ mp.echoFields,
-        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) })
+        masters    = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) }.toIndexedSeq)
     },
     slaveFn = { sp => sp
     })
diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala
index 0824b9c1b61..18e06704d7d 100755
--- a/src/main/scala/devices/debug/Debug.scala
+++ b/src/main/scala/devices/debug/Debug.scala
@@ -1703,7 +1703,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
           flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt, RegFieldDesc(s"debug_flags_$i", "", volatile=true))}
         }),
       ROMBASE       -> RegFieldGroup("debug_rom", Some("Debug ROM"),
-        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).zipWithIndex.map{case (x, i) =>
+        (if (cfg.atzero) DebugRomContents() else DebugRomNonzeroContents()).toIndexedSeq.zipWithIndex.map{case (x, i) =>
           RegField.r(8, (x & 0xFF).U(8.W), RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})
     )
 
diff --git a/src/main/scala/devices/tilelink/BootROM.scala b/src/main/scala/devices/tilelink/BootROM.scala
index d4fcda2b136..1e2793d2f17 100644
--- a/src/main/scala/devices/tilelink/BootROM.scala
+++ b/src/main/scala/devices/tilelink/BootROM.scala
@@ -99,7 +99,7 @@ object BootROM {
     }
 
     val bootrom = bootROMDomainWrapper {
-      LazyModule(new TLROM(params.address, params.size, contents, true, tlbus.beatBytes))
+      LazyModule(new TLROM(params.address, params.size, contents.toIndexedSeq, true, tlbus.beatBytes))
     }
 
     bootrom.node := tlbus.coupleTo(params.name){ TLFragmenter(tlbus, Some(params.name)) := _ }
diff --git a/src/main/scala/devices/tilelink/BusBypass.scala b/src/main/scala/devices/tilelink/BusBypass.scala
index 39ccbb0c117..a2731c78f3d 100644
--- a/src/main/scala/devices/tilelink/BusBypass.scala
+++ b/src/main/scala/devices/tilelink/BusBypass.scala
@@ -4,7 +4,10 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.ValName
+import org.chipsalliance.diplomacy.lazymodule._
+import org.chipsalliance.diplomacy.nodes.NodeHandle
+import freechips.rocketchip.diplomacy.{AddressSet, RegionType}
 import freechips.rocketchip.tilelink._
 
 abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096)
diff --git a/src/main/scala/devices/tilelink/Deadlock.scala b/src/main/scala/devices/tilelink/Deadlock.scala
index 0d5e970b216..905fb35201d 100644
--- a/src/main/scala/devices/tilelink/Deadlock.scala
+++ b/src/main/scala/devices/tilelink/Deadlock.scala
@@ -4,7 +4,7 @@ package freechips.rocketchip.devices.tilelink
 
 import chisel3._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.resources.{SimpleDevice}
 
 /** Adds a /dev/null slave that does not raise ready for any incoming traffic.
diff --git a/src/main/scala/diplomacy/AddressDecoder.scala b/src/main/scala/diplomacy/AddressDecoder.scala
index 1a5d7f7a44f..182e0108124 100644
--- a/src/main/scala/diplomacy/AddressDecoder.scala
+++ b/src/main/scala/diplomacy/AddressDecoder.scala
@@ -12,8 +12,9 @@ object AddressDecoder
   type Partitions = Seq[Partition]
 
   val addressOrder = Ordering.ordered[AddressSet]
-  val portOrder = Ordering.Iterable(addressOrder)
-  val partitionOrder = Ordering.Iterable(portOrder)
+  import Ordering.Implicits._
+  val portOrder = Ordering[Seq[AddressSet]]
+  val partitionOrder = Ordering[Seq[Seq[AddressSet]]]
 
   // Find the minimum subset of bits needed to disambiguate port addresses.
   // ie: inspecting only the bits in the output, you can look at an address
@@ -126,7 +127,7 @@ object AddressDecoder
           println("  For bit %x, %s".format(bit, score.toString))
         (score, bit, result)
       }
-      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Iterable[Int]](_._1.toIterable))
+      val (bestScore, bestBit, bestPartitions) = candidates.min(Ordering.by[(Seq[Int], BigInt, Partitions), Seq[Int]](_._1))
       if (debug) println("=> Selected bit 0x%x".format(bestBit))
       bestBit +: recurse(bestPartitions, bits.filter(_ != bestBit))
     }
diff --git a/src/main/scala/diplomacy/Main.scala b/src/main/scala/diplomacy/Main.scala
index d14a542ea4c..d641e790f26 100644
--- a/src/main/scala/diplomacy/Main.scala
+++ b/src/main/scala/diplomacy/Main.scala
@@ -5,7 +5,7 @@ import chisel3.stage.ChiselGeneratorAnnotation
 import chisel3.stage.phases.{Elaborate, Convert}
 import firrtl.AnnotationSeq
 import firrtl.options.TargetDirAnnotation
-import freechips.rocketchip.diplomacy.LazyModule
+import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import org.chipsalliance.cde.config.{Config, Parameters}
 import mainargs._
 
@@ -22,7 +22,7 @@ object Main {
         .getConstructor(classOf[Parameters])
         .newInstance(new Config(config.foldRight(Parameters.empty) {
           case (currentName, config) =>
-            val currentConfig = Class.forName(currentName).newInstance.asInstanceOf[Config]
+            val currentConfig = Class.forName(currentName).getDeclaredConstructor().newInstance().asInstanceOf[Config]
             currentConfig ++ config
         })) match {
           case m: RawModule => m
@@ -51,6 +51,6 @@ object Main {
     freechips.rocketchip.util.ElaborationArtefacts.files.foreach{ case (ext, contents) => os.write.over(os.Path(dir) / s"${config.mkString("_")}.${ext}", contents()) }
   }
 
-  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
+  def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args.toIndexedSeq)
 }
 
diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala
index ef28b918aa5..78d6f615afc 100644
--- a/src/main/scala/diplomacy/Parameters.scala
+++ b/src/main/scala/diplomacy/Parameters.scala
@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.diplomacy
 
+import scala.language.implicitConversions
+
 import chisel3._
 import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
 import freechips.rocketchip.util.ShiftQueue
@@ -30,8 +32,8 @@ case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
   require (start <= end, "Id ranges cannot be negative.")
 
   def compare(x: IdRange) = {
-    val primary   = (this.start - x.start).signum
-    val secondary = (x.end - this.end).signum
+    val primary   = (this.start - x.start).sign
+    val secondary = (x.end - this.end).sign
     if (primary != 0) primary else secondary
   }
 
@@ -119,7 +121,7 @@ object TransferSizes {
   def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
   def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
 
-  implicit def asBool(x: TransferSizes) = !x.none
+  implicit def asBool(x: TransferSizes): Boolean = !x.none
 }
 
 // AddressSets specify the address space managed by the manager
diff --git a/src/main/scala/diplomacy/package.scala b/src/main/scala/diplomacy/package.scala
index f6f0ed668a8..af287e2cc0e 100644
--- a/src/main/scala/diplomacy/package.scala
+++ b/src/main/scala/diplomacy/package.scala
@@ -59,7 +59,7 @@ package object diplomacy {
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")
   def ValName(value:                String)          = _root_.org.chipsalliance.diplomacy.ValName(value)
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")
-  implicit def SourcecodeNameExt(x: sourcecode.Name) = _root_.org.chipsalliance.diplomacy.SourcecodeNameExt(x)
+  implicit def SourcecodeNameExt(x: sourcecode.Name): _root_.org.chipsalliance.diplomacy.SourcecodeNameExt = _root_.org.chipsalliance.diplomacy.SourcecodeNameExt(x)
 
 // LazyModule.scala
   @deprecated("Diplomacy has been split to a standalone library", "rocketchip 2.0.0")
diff --git a/src/main/scala/groundtest/Configs.scala b/src/main/scala/groundtest/Configs.scala
index e9b00689aa9..03bf40bf511 100644
--- a/src/main/scala/groundtest/Configs.scala
+++ b/src/main/scala/groundtest/Configs.scala
@@ -42,7 +42,7 @@ class WithTraceGen(
   wordBits: Int = 32
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
+    val prev = up(TilesLocated(InSubsystem))
     val idOffset = up(NumTiles)
     val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
     params.zipWithIndex.map { case (dcp, i) =>
diff --git a/src/main/scala/interrupts/Parameters.scala b/src/main/scala/interrupts/Parameters.scala
index e9d90a56e7d..2d4472ca08a 100644
--- a/src/main/scala/interrupts/Parameters.scala
+++ b/src/main/scala/interrupts/Parameters.scala
@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.interrupts
 
+import scala.language.implicitConversions
+
 import chisel3.experimental.SourceInfo
 
 import org.chipsalliance.cde.config._
diff --git a/src/main/scala/interrupts/package.scala b/src/main/scala/interrupts/package.scala
index aaa73bf4b3a..d96080a32e3 100644
--- a/src/main/scala/interrupts/package.scala
+++ b/src/main/scala/interrupts/package.scala
@@ -20,15 +20,15 @@ package object interrupts
   type IntSyncNode = SimpleNodeHandle[IntSourcePortParameters, IntSinkPortParameters, IntEdge, SyncInterrupts]
 
   implicit class IntClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal {
-    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardClockCrossingHelper(valName.name, x, n)
-    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardClockCrossingHelper(valName.name, x, n)
+    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardClockCrossingHelper(valName.value, x, n)
+    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardClockCrossingHelper(valName.value, x, n)
     def cross(n: IntInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: IntOutwardNode)(implicit valName: ValName) = crossOut(n)
   }
 
   implicit class IntResetDomainCrossing(private val x: HasResetDomainCrossing) extends AnyVal {
-    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardResetCrossingHelper(valName.name, x, n)
-    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardResetCrossingHelper(valName.name, x, n)
+    def crossIn (n: IntInwardNode) (implicit valName: ValName) = IntInwardResetCrossingHelper(valName.value, x, n)
+    def crossOut(n: IntOutwardNode)(implicit valName: ValName) = IntOutwardResetCrossingHelper(valName.value, x, n)
     def cross(n: IntInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: IntOutwardNode)(implicit valName: ValName) = crossOut(n)
   }
diff --git a/src/main/scala/jtag/JtagStateMachine.scala b/src/main/scala/jtag/JtagStateMachine.scala
index 755b7cb66c2..07fb817d34e 100644
--- a/src/main/scala/jtag/JtagStateMachine.scala
+++ b/src/main/scala/jtag/JtagStateMachine.scala
@@ -15,7 +15,7 @@ object JtagState {
   object State {
     import scala.language.implicitConversions
 
-    implicit def toInt(x: State) = x.id
+    implicit def toInt(x: State): Int = x.id
     implicit def toBigInt(x: State):BigInt = x.id
 
     // TODO: this could be automatically generated with macros and stuff
diff --git a/src/main/scala/jtag/package.scala b/src/main/scala/jtag/package.scala
index 8ceceae50fe..963fdfcb9a8 100644
--- a/src/main/scala/jtag/package.scala
+++ b/src/main/scala/jtag/package.scala
@@ -11,5 +11,5 @@ package object jtag {
     *
     * This is limited to value types of Chain to limit application scope.
     */
-  implicit def instructionIntKeyToBigInt[V <: Chain](x: (Int, V)) = (BigInt(x._1), x._2)
+  implicit def instructionIntKeyToBigInt[V <: Chain](x: (Int, V)): (BigInt, V) = (BigInt(x._1), x._2)
 }
diff --git a/src/main/scala/prci/ClockGroup.scala b/src/main/scala/prci/ClockGroup.scala
index afd113d4e49..2c92fa2345b 100644
--- a/src/main/scala/prci/ClockGroup.scala
+++ b/src/main/scala/prci/ClockGroup.scala
@@ -34,7 +34,7 @@ class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
 
 object ClockGroup
 {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
+  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.value)).node
 }
 
 case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
@@ -63,7 +63,7 @@ class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends La
 
 object ClockGroupAggregator
 {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
+  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.value)).node
 }
 
 class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
diff --git a/src/main/scala/prci/package.scala b/src/main/scala/prci/package.scala
index 872a05d05d3..39d4747ca45 100644
--- a/src/main/scala/prci/package.scala
+++ b/src/main/scala/prci/package.scala
@@ -2,6 +2,8 @@
 
 package freechips.rocketchip
 
+import scala.language.implicitConversions
+
 import org.chipsalliance.diplomacy.nodes._
 import freechips.rocketchip.diplomacy.{BufferParams}
 
diff --git a/src/main/scala/regmapper/RegField.scala b/src/main/scala/regmapper/RegField.scala
index 1b7abfec234..0de9f416ed4 100644
--- a/src/main/scala/regmapper/RegField.scala
+++ b/src/main/scala/regmapper/RegField.scala
@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.regmapper
 
+import scala.language.implicitConversions
+
 import chisel3._
 import chisel3.util.{DecoupledIO, ReadyValidIO}
 
@@ -18,7 +20,7 @@ object RegReadFn
   // all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
   // effects must become visible on the cycle after ovalid && oready
   // data is only inspected when ovalid && oready
-  implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)) =
+  implicit def apply(x: (Bool, Bool) => (Bool, Bool, UInt)): RegReadFn =
     new RegReadFn(false, x)
   implicit def apply(x: RegisterReadIO[UInt]): RegReadFn =
     RegReadFn((ivalid, oready) => {
@@ -29,7 +31,7 @@ object RegReadFn
   // (ready: Bool) => (valid: Bool, data: UInt)
   // valid must not combinationally depend on ready
   // effects must become visible on the cycle after valid && ready
-  implicit def apply(x: Bool => (Bool, UInt)) =
+  implicit def apply(x: Bool => (Bool, UInt)): RegReadFn =
     new RegReadFn(true, { case (_, oready) =>
       val (ovalid, data) = x(oready)
       (true.B, ovalid, data)
@@ -50,7 +52,7 @@ object RegWriteFn
   // all other combinational dependencies forbidden (e.g. ovalid <= ivalid)
   // effects must become visible on the cycle after ovalid && oready
   // data should only be used for an effect when ivalid && iready
-  implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)) =
+  implicit def apply(x: (Bool, Bool, UInt) => (Bool, Bool)): RegWriteFn =
     new RegWriteFn(false, x)
   implicit def apply(x: RegisterWriteIO[UInt]): RegWriteFn =
     RegWriteFn((ivalid, oready, data) => {
@@ -62,7 +64,7 @@ object RegWriteFn
   // (valid: Bool, data: UInt) => (ready: Bool)
   // ready may combinationally depend on data (but not valid)
   // effects must become visible on the cycle after valid && ready
-  implicit def apply(x: (Bool, UInt) => Bool) =
+  implicit def apply(x: (Bool, UInt) => Bool): RegWriteFn =
     // combinational => data valid on oready
     new RegWriteFn(true, { case (_, oready, data) =>
       (true.B, x(oready, data))
diff --git a/src/main/scala/regmapper/RegMapper.scala b/src/main/scala/regmapper/RegMapper.scala
index 2e00c77005a..9b11ea33a4a 100644
--- a/src/main/scala/regmapper/RegMapper.scala
+++ b/src/main/scala/regmapper/RegMapper.scala
@@ -195,10 +195,10 @@ object RegMapper
       })
 
     // Include the per-register one-hot selected criteria
-    val rifireMux = mux(iindex, in.valid && front.ready &&  front.bits.read, frontSel, iRightReg, rifire)
-    val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg, wifire)
-    val rofireMux = mux(oindex, back.valid && out.ready &&  back .bits.read, backSel,  oRightReg, rofire)
-    val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel,  oRightReg, wofire)
+    val rifireMux = mux(iindex, in.valid && front.ready &&  front.bits.read, frontSel, iRightReg.toIndexedSeq, rifire.toIndexedSeq)
+    val wifireMux = mux(iindex, in.valid && front.ready && !front.bits.read, frontSel, iRightReg.toIndexedSeq, wifire.toIndexedSeq)
+    val rofireMux = mux(oindex, back.valid && out.ready &&  back .bits.read, backSel,  oRightReg.toIndexedSeq, rofire.toIndexedSeq)
+    val wofireMux = mux(oindex, back.valid && out.ready && !back .bits.read, backSel,  oRightReg.toIndexedSeq, wofire.toIndexedSeq)
 
     val iready = Mux(front.bits.read, rifireMux, wifireMux)
     val oready = Mux(back .bits.read, rofireMux, wofireMux)
@@ -210,8 +210,8 @@ object RegMapper
     out.valid   := back.valid  && oready
 
     out.bits.read  := back.bits.read
-    out.bits.data  := Mux(MuxSeq(oindex, true.B, oRightReg),
-                          MuxSeq(oindex, 0.U, dataOut),
+    out.bits.data  := Mux(MuxSeq(oindex, true.B, oRightReg.toIndexedSeq),
+                          MuxSeq(oindex, 0.U, dataOut.toIndexedSeq),
                           0.U)
     out.bits.extra := back.bits.extra
 
diff --git a/src/main/scala/resources/AddressMapEntry.scala b/src/main/scala/resources/AddressMapEntry.scala
index 27ba067ad56..c30e7a39ad9 100644
--- a/src/main/scala/resources/AddressMapEntry.scala
+++ b/src/main/scala/resources/AddressMapEntry.scala
@@ -17,5 +17,5 @@ case class AddressMapEntry(range: AddressRange, permissions: ResourcePermissions
 
   def toJSON = s"""{"base":[${range.base}],"size":[${range.size}],""" +
     s""""r":[$r],"w":[$w],"x":[$x],"c":[$c],"a":[$a],""" +
-    s""""names":[${names.map('"'+_+'"').mkString(",")}]}"""
+    s""""names":[${names.map(n => s""""$n"""").mkString(",")}]}"""
 }
diff --git a/src/main/scala/resources/DeviceTree.scala b/src/main/scala/resources/DeviceTree.scala
index 3c9e04384fc..993cf707239 100644
--- a/src/main/scala/resources/DeviceTree.scala
+++ b/src/main/scala/resources/DeviceTree.scala
@@ -137,6 +137,6 @@ object DTB
     require (proc.! == 0, "Failed to run dtc; is it in your path?")
     instream.close
     outstream.close
-    DTB(outstream.toByteArray)
+    DTB(outstream.toByteArray.toIndexedSeq)
   }
 }
diff --git a/src/main/scala/resources/Resources.scala b/src/main/scala/resources/Resources.scala
index 41d042f4907..e10c1fa65f7 100644
--- a/src/main/scala/resources/Resources.scala
+++ b/src/main/scala/resources/Resources.scala
@@ -145,7 +145,7 @@ trait DeviceRegName
 {
   this: Device =>
   def describeName(devname: String, resources: ResourceBindings): String = {
-    val reg = resources.map.filterKeys(DiplomacyUtils.regFilter)
+    val reg = resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap
     if (reg.isEmpty) {
       devname
     } else {
@@ -195,7 +195,7 @@ class SimpleDevice(val devname: String, devcompat: Seq[String]) extends Device
     def optDef(x: String, seq: Seq[ResourceValue]) = if (seq.isEmpty) None else Some(x -> seq)
     val compat = optDef("compatible", devcompat.map(ResourceString(_))) // describe the list of compatiable devices
 
-    val reg = resources.map.filterKeys(DiplomacyUtils.regFilter)
+    val reg = resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap
     val (named, bulk) = reg.partition { case (k, v) => DiplomacyUtils.regName(k).isDefined }
     // We need to be sure that each named reg has exactly one AddressRange associated to it
     named.foreach {
@@ -252,7 +252,7 @@ class MemoryDevice extends Device with DeviceRegName
 {
   def describe(resources: ResourceBindings): Description = {
     Description(describeName("memory", resources), ListMap(
-      "reg"         -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList,
+      "reg"         -> resources.map.view.filterKeys(DiplomacyUtils.regFilter).toMap.flatMap(_._2).map(_.value).toList,
       "device_type" -> Seq(ResourceString("memory"))))
   }
 }
@@ -379,8 +379,8 @@ trait BindingScope
     */
   def getResourceBindingsMap: ResourceBindingsMap = {
     eval
-    ResourceBindingsMap(map = resourceBindings.reverse.groupBy(_._1.owner).mapValues(seq => ResourceBindings(
-        seq.groupBy(_._1.key).mapValues(_.map(z => Binding(z._2, z._3)).distinct).toMap)).toMap)
+    ResourceBindingsMap(map = resourceBindings.reverse.groupBy(_._1.owner).view.mapValues(seq => ResourceBindings(
+        seq.groupBy(_._1.key).view.mapValues(_.map(z => Binding(z._2, z._3)).distinct).toMap)).toMap)
   }
 
   /** Collect resource addresses from tree. */
diff --git a/src/main/scala/resources/SRAM.scala b/src/main/scala/resources/SRAM.scala
index 8fc3c16e0d8..e18ab53f2fb 100644
--- a/src/main/scala/resources/SRAM.scala
+++ b/src/main/scala/resources/SRAM.scala
@@ -5,8 +5,9 @@ package freechips.rocketchip.resources
 import chisel3._
 import chisel3.util.log2Ceil
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.util.{DescribedSRAM, Code}
-import freechips.rocketchip.diplomacy.{AddressSet, LazyModule}
+import freechips.rocketchip.diplomacy.AddressSet
 
 abstract class DiplomaticSRAM(
     val address: AddressSet,
diff --git a/src/main/scala/rocket/BTB.scala b/src/main/scala/rocket/BTB.scala
index cb8392a7c29..55594d8035b 100644
--- a/src/main/scala/rocket/BTB.scala
+++ b/src/main/scala/rocket/BTB.scala
@@ -24,7 +24,7 @@ case class BTBParams(
   bhtParams: Option[BHTParams] = Some(BHTParams()),
   updatesOutOfOrder: Boolean = false)
 
-trait HasBtbParameters extends HasCoreParameters { this: InstanceId =>
+trait HasBtbParameters extends HasCoreParameters {
   val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
   val matchBits = btbParams.nMatchBits max log2Ceil(p(CacheBlockBytes) * tileParams.icache.get.nSets)
   val entries = btbParams.nEntries
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 0e931388065..ad883182af5 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -133,7 +133,7 @@ class Envcfg extends Bundle {
   val cbie = UInt(2.W)
   val zero3 = UInt(3.W)
   val fiom = Bool()
-  def write(wdata: UInt) {
+  def write(wdata: UInt): Unit = {
     val new_envcfg = wdata.asTypeOf(new Envcfg)
     fiom := new_envcfg.fiom // only FIOM is writable currently
   }
@@ -897,7 +897,7 @@ class CSRFile(
     val addr = io_dec.inst(31, 20)
 
     def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)
-    def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))
+    def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping.toMap -- s).keys.toList.map(_.U))
 
     val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =
       DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)
@@ -1508,10 +1508,10 @@ class CSRFile(
         io.wen := true.B
       }
     }
-    for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
+    for ((io, csr, reg) <- io.customCSRs.lazyZip(customCSRs).lazyZip(reg_custom)) {
       writeCustomCSR(io, csr, reg)
     }
-    for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
+    for ((io, csr, reg) <- io.roccCSRs.lazyZip(roccCSRs).lazyZip(reg_rocc)) {
       writeCustomCSR(io, csr, reg)
     }
     if (usingVector) {
@@ -1532,10 +1532,10 @@ class CSRFile(
       reg := (io.sdata & mask) | (reg & ~mask)
     }
   }
-  for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
+  for ((io, csr, reg) <- io.customCSRs.lazyZip(customCSRs).lazyZip(reg_custom)) {
     setCustomCSR(io, csr, reg)
   }
-  for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
+  for ((io, csr, reg) <- io.roccCSRs.lazyZip(roccCSRs).lazyZip(reg_rocc)) {
     setCustomCSR(io, csr, reg)
   }
 
diff --git a/src/main/scala/rocket/Configs.scala b/src/main/scala/rocket/Configs.scala
index a653e361ee9..82642de931a 100644
--- a/src/main/scala/rocket/Configs.scala
+++ b/src/main/scala/rocket/Configs.scala
@@ -18,7 +18,7 @@ class WithNHugeCores(
   crossing: RocketCrossingParams,
 ) extends Config((site, here, up) => {
   case TilesLocated(`location`) => {
-    val prev = up(TilesLocated(`location`), site)
+    val prev = up(TilesLocated(`location`))
     val idOffset = up(NumTiles)
     val big = RocketTileParams(
       core   = RocketCoreParams(
@@ -65,7 +65,7 @@ class WithNBigCores(
   crossing: RocketCrossingParams,
 ) extends Config((site, here, up) => {
   case TilesLocated(`location`) => {
-    val prev = up(TilesLocated(`location`), site)
+    val prev = up(TilesLocated(`location`))
     val idOffset = up(NumTiles)
     val big = RocketTileParams(
       core   = RocketCoreParams(mulDiv = Some(MulDivParams(
@@ -101,7 +101,7 @@ class WithNMedCores(
   crossing: RocketCrossingParams = RocketCrossingParams(),
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
+    val prev = up(TilesLocated(InSubsystem))
     val idOffset = up(NumTiles)
     val med = RocketTileParams(
       core = RocketCoreParams(fpu = None),
@@ -134,7 +134,7 @@ class WithNSmallCores(
   crossing: RocketCrossingParams = RocketCrossingParams()
 ) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
-    val prev = up(TilesLocated(InSubsystem), site)
+    val prev = up(TilesLocated(InSubsystem))
     val idOffset = up(NumTiles)
     val small = RocketTileParams(
       core = RocketCoreParams(useVM = false, fpu = None),
@@ -320,7 +320,7 @@ class WithCloneRocketTiles(
   cloneLocation: HierarchicalLocation = InSubsystem
 ) extends Config((site, here, up) => {
   case TilesLocated(`location`) => {
-    val prev = up(TilesLocated(location), site)
+    val prev = up(TilesLocated(location))
     val idOffset = up(NumTiles)
     val tileAttachParams = up(TilesLocated(cloneLocation)).find(_.tileParams.tileId == cloneTileId)
       .get.asInstanceOf[RocketTileAttachParams]
diff --git a/src/main/scala/rocket/CustomInstructions.scala b/src/main/scala/rocket/CustomInstructions.scala
index b4cada00bee..0427fb401f6 100644
--- a/src/main/scala/rocket/CustomInstructions.scala
+++ b/src/main/scala/rocket/CustomInstructions.scala
@@ -50,7 +50,7 @@ object CustomCSRs {
     res.toArray
   }
   val all32 = {
-    val res = collection.mutable.ArrayBuffer(all:_*)
+    val res = collection.mutable.ArrayBuffer.from(all)
     res.toArray
   }
 }
diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala
index 4e456d785c4..b06a80e2dfd 100644
--- a/src/main/scala/rocket/DCache.scala
+++ b/src/main/scala/rocket/DCache.scala
@@ -582,7 +582,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val put     = edge.Put(a_source, access_address, a_size, a_data)._2
   val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2
   val atomics = if (edge.manager.anySupportLogical) {
-    MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array(
+    MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Seq(
       M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2,
       M_XA_XOR  -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2,
       M_XA_OR   -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR)  ._2,
diff --git a/src/main/scala/rocket/DebugROB.scala b/src/main/scala/rocket/DebugROB.scala
index 39dec03a78c..b79efbeb767 100644
--- a/src/main/scala/rocket/DebugROB.scala
+++ b/src/main/scala/rocket/DebugROB.scala
@@ -5,7 +5,6 @@ package freechips.rocketchip.rocket
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{IntParam}
 import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tile.{HasCoreParameters}
 import freechips.rocketchip.util.DecoupledHelper
@@ -91,7 +90,7 @@ object DebugROB {
     trace
   }
   def pushWb(clock: Clock, reset: Reset,
-    hartid: UInt, valid: Bool, tag: UInt, data: UInt)(implicit p: Parameters) {
+    hartid: UInt, valid: Bool, tag: UInt, data: UInt)(implicit p: Parameters): Unit = {
     val debug_rob_push_wb = Module(new DebugROBPushWb)
     debug_rob_push_wb.io.clock := clock
     debug_rob_push_wb.io.reset := reset
diff --git a/src/main/scala/rocket/Instructions.scala b/src/main/scala/rocket/Instructions.scala
index dabf5365691..0477d34c4f5 100644
--- a/src/main/scala/rocket/Instructions.scala
+++ b/src/main/scala/rocket/Instructions.scala
@@ -1601,7 +1601,7 @@ object CSRs {
     res.toArray
   }
   val all32 = {
-    val res = collection.mutable.ArrayBuffer(all:_*)
+    val res = collection.mutable.ArrayBuffer.from(all)
     res += sieh
     res += siph
     res += stimecmph
diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala
index a0f9f72b91b..bc6e41a7e76 100644
--- a/src/main/scala/rocket/NBDcache.scala
+++ b/src/main/scala/rocket/NBDcache.scala
@@ -83,7 +83,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa
   val get     = edge.Get(a_source, a_address, a_size)._2
   val put     = edge.Put(a_source, a_address, a_size, a_data)._2
   val atomics = if (edge.manager.anySupportLogical) {
-    MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array(
+    MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Seq(
       M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2,
       M_XA_XOR  -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2,
       M_XA_OR   -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR)  ._2,
diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala
index 8b613aa09de..79eb7a76276 100644
--- a/src/main/scala/rocket/ScratchpadSlavePort.scala
+++ b/src/main/scala/rocket/ScratchpadSlavePort.scala
@@ -64,16 +64,16 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
 
     def formCacheReq(a: TLBundleA) = {
       val req = Wire(new HellaCacheReq)
-      req.cmd := MuxLookup(a.opcode, M_XRD)(Array(
+      req.cmd := MuxLookup(a.opcode, M_XRD)(Seq(
         TLMessages.PutFullData    -> M_XWR,
         TLMessages.PutPartialData -> M_PWR,
-        TLMessages.ArithmeticData -> MuxLookup(a.param, M_XRD)(Array(
+        TLMessages.ArithmeticData -> MuxLookup(a.param, M_XRD)(Seq(
           TLAtomics.MIN           -> M_XA_MIN,
           TLAtomics.MAX           -> M_XA_MAX,
           TLAtomics.MINU          -> M_XA_MINU,
           TLAtomics.MAXU          -> M_XA_MAXU,
           TLAtomics.ADD           -> M_XA_ADD)),
-        TLMessages.LogicalData    -> MuxLookup(a.param, M_XRD)(Array(
+        TLMessages.LogicalData    -> MuxLookup(a.param, M_XRD)(Seq(
           TLAtomics.XOR           -> M_XA_XOR,
           TLAtomics.OR            -> M_XA_OR,
           TLAtomics.AND           -> M_XA_AND,
diff --git a/src/main/scala/rocket/TLBPermissions.scala b/src/main/scala/rocket/TLBPermissions.scala
index 899bc7c33ca..dbde7674804 100644
--- a/src/main/scala/rocket/TLBPermissions.scala
+++ b/src/main/scala/rocket/TLBPermissions.scala
@@ -45,7 +45,7 @@ object TLBPageLookup
     permissions
       .filter(_._2.useful) // get rid of no-permission devices
       .groupBy(_._2) // group by permission type
-      .mapValues(seq =>
+      .view.mapValues(seq =>
         AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions
       .toMap
   }
@@ -72,7 +72,7 @@ object TLBPageLookup
     }
 
     val grouped = groupRegions(managers)
-      .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough
+      .view.mapValues(_.filter(_.alignment >= pageSize)).toMap // discard any region that's not big enough
 
     def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = {
       val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) }
diff --git a/src/main/scala/rocket/VectorUnit.scala b/src/main/scala/rocket/VectorUnit.scala
index f0a75106168..9797d37fcca 100644
--- a/src/main/scala/rocket/VectorUnit.scala
+++ b/src/main/scala/rocket/VectorUnit.scala
@@ -3,8 +3,8 @@ package freechips.rocketchip.rocket
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config._
+import org.chipsalliance.diplomacy.lazymodule._
 import freechips.rocketchip.tile._
-import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
 case class RocketCoreVectorParams(
diff --git a/src/main/scala/subsystem/Cluster.scala b/src/main/scala/subsystem/Cluster.scala
index a1dc1cef3da..71b11d4b6ea 100644
--- a/src/main/scala/subsystem/Cluster.scala
+++ b/src/main/scala/subsystem/Cluster.scala
@@ -8,7 +8,7 @@ import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.{TLDebugModule}
-import freechips.rocketchip.diplomacy.{FlipRendering}
+import org.chipsalliance.diplomacy.FlipRendering
 import freechips.rocketchip.interrupts.{IntIdentityNode, IntSyncIdentityNode, NullIntSource}
 import freechips.rocketchip.prci.{ClockCrossingType, NoCrossing, ClockSinkParameters, ClockGroupIdentityNode, BundleBridgeBlockDuringReset}
 import freechips.rocketchip.tile.{RocketTile, NMI, TraceBundle}
@@ -79,7 +79,7 @@ class Cluster(
   lazy val tileToPlicNodes = totalTileIdList.map { i => (i, IntIdentityNode()) }.to(SortedMap)
   lazy val debugNodes = totalTileIdList.map { i => (i, IntSyncIdentityNode()) }.to(SortedMap)
   lazy val nmiNodes = totalTiles.filter { case (i,t) => t.tileParams.core.useNMI }
-    .mapValues(_ => BundleBridgeIdentityNode[NMI]()).to(SortedMap)
+    .view.mapValues(_ => BundleBridgeIdentityNode[NMI]()).to(SortedMap)
   lazy val tileHartIdNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(SortedMap)
   lazy val tileResetVectorNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[UInt]()) }.to(SortedMap)
   lazy val traceCoreNodes = totalTileIdList.map { i => (i, BundleBridgeIdentityNode[TraceCoreInterface]()) }.to(SortedMap)
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
index 6d269192351..ee54e2ed48c 100644
--- a/src/main/scala/subsystem/Configs.scala
+++ b/src/main/scala/subsystem/Configs.scala
@@ -14,9 +14,8 @@ import freechips.rocketchip.devices.tilelink.{
   BuiltInErrorDeviceParams, BootROMLocated, BootROMParams, CLINTKey, DevNullDevice, CLINTParams, PLICKey, PLICParams, DevNullParams
 }
 import freechips.rocketchip.prci.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing, ClockCrossingType}
-import freechips.rocketchip.diplomacy.{
-  AddressSet, MonitorsEnabled,
-}
+import freechips.rocketchip.diplomacy.AddressSet
+import org.chipsalliance.diplomacy.nodes.MonitorsEnabled
 import freechips.rocketchip.resources.{
   DTSModel, DTSCompat, DTSTimebase, BigIntHexContext
 }
@@ -129,11 +128,11 @@ class WithClusterBanks(clusterId: Int, nBanks: Int = 1) extends Config((site, he
 })
 
 class WithNBanks(n: Int) extends Config((site, here, up) => {
-  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(nBanks = n)
+  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = n)
 })
 
 class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
-  case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n)
+  case BroadcastKey => up(BroadcastKey).copy(nTrackers = n)
 })
 
 class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
@@ -141,7 +140,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
 })
 
 class WithBufferlessBroadcastHub extends Config((site, here, up) => {
-  case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true)
+  case BroadcastKey => up(BroadcastKey).copy(bufferless = true)
 })
 
 class TileAttachConfig[T <: CanAttachTile](f: T => T, locationOpt: Option[HierarchicalLocation], tileIdOpt: Seq[Int])(implicit tag: ClassTag[T])
@@ -194,7 +193,7 @@ class WithRoccExample extends Config((site, here, up) => {
  * DO NOT use this configuration.
  */
 class WithIncoherentTiles extends Config((site, here, up) => {
-  case TilesLocated(location) => up(TilesLocated(location), site) map {
+  case TilesLocated(location) => up(TilesLocated(location)) map {
     case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
       master = tp.crossingParams.master match {
         case x: HierarchicalElementMasterPortParams => x.copy(cork = Some(true))
@@ -202,13 +201,13 @@ class WithIncoherentTiles extends Config((site, here, up) => {
       }))
     case t => t
   }
-  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(
+  case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(
     coherenceManager = CoherenceManagerWrapper.incoherentManager
   )
 })
 
 class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName=SystemFileName(bootROMFile)))
+  case BootROMLocated(x) => up(BootROMLocated(x)).map(_.copy(contentFileName=SystemFileName(bootROMFile)))
 })
 
 class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => {
@@ -216,25 +215,25 @@ class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((
 })
 
 class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
-  case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
-  case ExtIn => up(ExtIn, site).map(_.copy(beatBytes = dataBits/8))
+  case MemoryBusKey => up(MemoryBusKey).copy(beatBytes = dataBits/8)
+  case ExtIn => up(ExtIn).map(_.copy(beatBytes = dataBits/8))
 })
 
 class WithJtagDTM extends Config ((site, here, up) => {
-  case ExportDebug => up(ExportDebug, site).copy(protocols = Set(JTAG))
+  case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG))
 })
 
 class WithDebugAPB extends Config ((site, here, up) => {
-  case ExportDebug => up(ExportDebug, site).copy(protocols = Set(APB))
+  case ExportDebug => up(ExportDebug).copy(protocols = Set(APB))
 })
 
 
 class WithDebugSBA extends Config ((site, here, up) => {
-  case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(hasBusMaster = true))
+  case DebugModuleKey => up(DebugModuleKey).map(_.copy(hasBusMaster = true))
 })
 
 class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey, site).copy(beatBytes = nBits/8)
+  case PeripheryBusKey => up(PeripheryBusKey).copy(beatBytes = nBits/8)
 })
 
 class WithoutTLMonitors extends Config ((site, here, up) => {
@@ -246,15 +245,15 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
 })
 
 class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
-  case ExtMem => up(ExtMem, site).map(_.copy(nMemoryChannels = n))
+  case ExtMem => up(ExtMem).map(_.copy(nMemoryChannels = n))
 })
 
 class WithExtMemSize(n: BigInt) extends Config((site, here, up) => {
-  case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = n)))
+  case ExtMem => up(ExtMem).map(x => x.copy(master = x.master.copy(size = n)))
 })
 
 class WithExtMemSbusBypass(base: BigInt = x"10_0000_0000") extends Config((site, here, up) => {
-  case ExtMem => up(ExtMem, site).map(x => x.copy(incohBase = Some(base)))
+  case ExtMem => up(ExtMem).map(x => x.copy(incohBase = Some(base)))
 })
 
 class WithDTS(model: String, compat: Seq[String]) extends Config((site, here, up) => {
@@ -348,19 +347,19 @@ class WithFbusToSbusCrossingType(xType: ClockCrossingType) extends Config((site,
   * up the diplomatic graph to the clock sources.
   */
 class WithPeripheryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
+  case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
 })
 class WithMemoryBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case MemoryBusKey => up(MemoryBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
+  case MemoryBusKey => up(MemoryBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
 })
 class WithSystemBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case SystemBusKey => up(SystemBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
+  case SystemBusKey => up(SystemBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
 })
 class WithFrontBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case FrontBusKey => up(FrontBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
+  case FrontBusKey => up(FrontBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
 })
 class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) => {
-  case ControlBusKey => up(ControlBusKey, site).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
+  case ControlBusKey => up(ControlBusKey).copy(dtsFrequency = Some(BigInt((freqMHz * 1e6).round)))
 })
 
 /** Under the default multi-bus topologies, this leaves bus ClockSinks undriven by the topology itself */
diff --git a/src/main/scala/subsystem/HasHierarchicalElements.scala b/src/main/scala/subsystem/HasHierarchicalElements.scala
index c7078f53975..b0e90019266 100644
--- a/src/main/scala/subsystem/HasHierarchicalElements.scala
+++ b/src/main/scala/subsystem/HasHierarchicalElements.scala
@@ -100,7 +100,7 @@ trait InstantiatesHierarchicalElements { this: LazyModule with Attachable =>
 
   val element_prci_domains: Seq[HierarchicalElementPRCIDomain[_]] = tile_prci_domains.values.toSeq ++ cluster_prci_domains.values.toSeq
 
-  val leafTiles: SortedMap[Int, BaseTile] = SortedMap(tile_prci_domains.mapValues(_.element.asInstanceOf[BaseTile]).toSeq.sortBy(_._1):_*)
+  val leafTiles: SortedMap[Int, BaseTile] = SortedMap(tile_prci_domains.view.mapValues(_.element.asInstanceOf[BaseTile]).toSeq.sortBy(_._1):_*)
   val totalTiles: SortedMap[Int, BaseTile] = (leafTiles ++ cluster_prci_domains.values.map(_.element.asInstanceOf[Cluster].totalTiles).flatten)
 
   // Helper functions for accessing certain parameters that are popular to refer to in subsystem code
@@ -108,7 +108,7 @@ trait InstantiatesHierarchicalElements { this: LazyModule with Attachable =>
   def nTotalTiles: Int = totalTiles.size
   def leafTileIdList: Seq[Int] = leafTiles.keys.toSeq.sorted
   def totalTileIdList: Seq[Int] = totalTiles.keys.toSeq.sorted
-  def localIntCounts: SortedMap[Int, Int] = totalTiles.mapValues(_.tileParams.core.nLocalInterrupts).to(SortedMap)
+  def localIntCounts: SortedMap[Int, Int] = totalTiles.view.mapValues(_.tileParams.core.nLocalInterrupts).to(SortedMap)
 
   require(totalTileIdList.distinct.size == totalTiles.size, s"Every tile must be statically assigned a unique id, but got:\n${totalTileIdList}")
 }
@@ -217,7 +217,7 @@ trait HasHierarchicalElementsRootContext
     outputRequiresInput = false,
     inputRequiresOutput = false))
   val seipNodes: SortedMap[Int, IntNode] = totalTiles.filter { case (_, t) => t.tileParams.core.hasSupervisorMode }
-    .mapValues( _ => IntEphemeralNode()).to(SortedMap)
+    .view.mapValues( _ => IntEphemeralNode()).to(SortedMap)
 
   // meip/seip nodes must be connected in MSMSMS order
   // TODO: This is ultra fragile... the plic should just expose two intnodes
diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala
index 5a0f0b856c6..856debcc4e5 100644
--- a/src/main/scala/subsystem/HasTiles.scala
+++ b/src/main/scala/subsystem/HasTiles.scala
@@ -9,7 +9,7 @@ import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.TLDebugModule
-import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
+import org.chipsalliance.diplomacy.{DisableMonitors, FlipRendering}
 import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
 import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
 import freechips.rocketchip.tilelink.TLWidthWidget
diff --git a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala
index 8c234cd4e75..95a65f2d697 100644
--- a/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala
+++ b/src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala
@@ -7,7 +7,7 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.debug.TLDebugModule
-import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
+import org.chipsalliance.diplomacy.{DisableMonitors, FlipRendering}
 import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
 import freechips.rocketchip.prci.{ClockCrossingType, ResetCrossingType, ResetDomain, ClockSinkNode, ClockSinkParameters, ClockIdentityNode, FixedClockBroadcast, ClockDomain}
 import freechips.rocketchip.tile.{RocketTile, TraceBundle}
diff --git a/src/main/scala/subsystem/Litex.scala b/src/main/scala/subsystem/Litex.scala
index 7e8e1888d94..7c8b868e989 100644
--- a/src/main/scala/subsystem/Litex.scala
+++ b/src/main/scala/subsystem/Litex.scala
@@ -49,5 +49,5 @@ class WithLitexSlavePort extends Config((site, here, up) => {
 })
 
 class WithNBitMemoryBus(dataBits: Int) extends Config((site, here, up) => {
-  case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
+  case MemoryBusKey => up(MemoryBusKey).copy(beatBytes = dataBits/8)
 })
diff --git a/src/main/scala/system/RocketTestSuite.scala b/src/main/scala/system/RocketTestSuite.scala
index f188d3cd7b3..b9b4a54df03 100644
--- a/src/main/scala/system/RocketTestSuite.scala
+++ b/src/main/scala/system/RocketTestSuite.scala
@@ -55,7 +55,7 @@ class RegressionTestSuite(val names: LinkedHashSet[String]) extends RocketTestSu
 }
 
 object TestGeneration {
-  private val suites = collection.mutable.ListMap[String, RocketTestSuite]()
+  private var suites = collection.immutable.ListMap[String, RocketTestSuite]()
 
   def addSuite(s: RocketTestSuite): Unit = { suites += (s.makeTargetName -> s) }
   
@@ -66,7 +66,7 @@ object TestGeneration {
       val envs = s.groupBy(_.envName)
       val targets = s.map(t => s"$$(${t.makeTargetName})").mkString(" ")
       s.map(_.toString).mkString("\n") +
-      envs.filterKeys(_ != "").map( {
+      envs.view.filterKeys(_ != "").toMap.map( {
                                      case (env,envsuites) => {
                                        val suites = envsuites.map(t => s"$$(${t.makeTargetName})").mkString(" ")
                                        s"""
@@ -113,7 +113,7 @@ object DefaultTestSuites {
   val rv32uaSansLRSCNames = LinkedHashSet("amoadd_w", "amoand_w", "amoor_w", "amoxor_w", "amoswap_w", "amomax_w", "amomaxu_w", "amomin_w", "amominu_w")
   val rv32uaSansLRSC = new AssemblyTestSuite("rv32ua", rv32uaSansLRSCNames)(_)
 
-  val rv32uaNames = rv32uaSansLRSCNames + "lrsc"
+  val rv32uaNames = rv32uaSansLRSCNames.union(LinkedHashSet("lrsc"))
   val rv32ua = new AssemblyTestSuite("rv32ua", rv32uaNames)(_)
 
   val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi", "dirty")
@@ -138,7 +138,7 @@ object DefaultTestSuites {
   val rv64uaSansLRSCNames = rv32uaSansLRSCNames.map(_.replaceAll("_w","_d"))
   val rv64uaSansLRSC = new AssemblyTestSuite("rv64ua", rv32uaSansLRSCNames ++ rv64uaSansLRSCNames)(_)
 
-  val rv64uaNames = rv64uaSansLRSCNames + "lrsc"
+  val rv64uaNames = rv64uaSansLRSCNames.union(LinkedHashSet("lrsc"))
   val rv64ua = new AssemblyTestSuite("rv64ua", rv32uaNames ++ rv64uaNames)(_)
 
   val rv64ucNames = rv32ucNames
@@ -148,9 +148,9 @@ object DefaultTestSuites {
   val rv64uf = new AssemblyTestSuite("rv64uf", rv64ufNames)(_)
 
   val rv32uf = new AssemblyTestSuite("rv32uf", rv64ufNames)(_)
-  val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames - "move")(_)
+  val rv32ud = new AssemblyTestSuite("rv32ud", rv64ufNames.diff(LinkedHashSet("move")))(_)
 
-  val rv64udNames = rv64ufNames + "structural"
+  val rv64udNames = rv64ufNames.union(LinkedHashSet("structural"))
   val rv64ud = new AssemblyTestSuite("rv64ud", rv64udNames)(_)
 
   val rv32uzfhNames = rv64ufNames
@@ -162,13 +162,13 @@ object DefaultTestSuites {
   val rv32uzbaNames = LinkedHashSet("sh1add", "sh2add", "sh3add")
   val rv32uzba = new AssemblyTestSuite("rv32uzba", rv32uzbaNames)(_)
 
-  val rv64uzbaNames = rv32uzbaNames ++ rv32uzbaNames.map(_ + "_uw") + "add_uw" + "slli_uw"
+  val rv64uzbaNames = rv32uzbaNames ++ rv32uzbaNames.map(_ + "_uw") ++ LinkedHashSet("add_uw", "slli_uw")
   val rv64uzba = new AssemblyTestSuite("rv64uzba", rv64uzbaNames)(_)
 
   val rv32uzbbNames = LinkedHashSet("andn", "clz", "cpop", "ctz", "max", "maxu", "min", "minu", "orc_b", "orn", "rev8", "rol", "ror", "rori", "sext_b", "sext_h", "xnor", "zext_h")
   val rv32uzbb = new AssemblyTestSuite("rv32uzbb", rv32uzbbNames)(_)
 
-  val rv64uzbbNames = rv32uzbbNames + "clzw" + "cpopw" + "ctzw" + "rolw" + "roriw"
+  val rv64uzbbNames = rv32uzbbNames.union(LinkedHashSet("clzw", "cpopw", "ctzw", "rolw", "roriw"))
   val rv64uzbb = new AssemblyTestSuite("rv64uzbb", rv64uzbbNames)(_)
 
   val rv32uzbsNames = LinkedHashSet("bclr", "bclri", "bext", "bexti", "binv", "binvi", "bset", "bseti")
@@ -177,10 +177,10 @@ object DefaultTestSuites {
   val rv64uzbsNames = rv32uzbsNames
   val rv64uzbs = new AssemblyTestSuite("rv64uzbs", rv64uzbsNames)(_)
 
-  val rv64siNames = rv32siNames + "icache-alias"
+  val rv64siNames = rv32siNames.union(LinkedHashSet("icache-alias"))
   val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_)
 
-  val rv64miNames = rv32miNames - "shamt" + "breakpoint" + "access"
+  val rv64miNames = rv32miNames.diff(LinkedHashSet("shamt")).union(LinkedHashSet("breakpoint", "access"))
   val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_)
 
   val groundtestNames = LinkedHashSet("simple")
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index be709854f38..009f4937bd5 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -9,8 +9,9 @@ import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy.lazymodule._
 
 import freechips.rocketchip.devices.tilelink.{BasicBusBlockerParams, BasicBusBlocker}
+import org.chipsalliance.diplomacy.DisableMonitors
 import freechips.rocketchip.diplomacy.{
-  AddressSet, DisableMonitors, BufferParams
+  AddressSet, BufferParams
 }
 import freechips.rocketchip.resources.{
   SimpleDevice, Description,
diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala
index 5f0fc655fdc..3bedf0fc3dc 100644
--- a/src/main/scala/tilelink/AtomicAutomata.scala
+++ b/src/main/scala/tilelink/AtomicAutomata.scala
@@ -182,7 +182,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
             when (en) {
               r.fifoId := a_fifoId
               r.bits   := in.a.bits
-              r.lut    := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array(
+              r.lut    := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Seq(
                 TLAtomics.AND  -> 0x8.U,
                 TLAtomics.OR   -> 0xe.U,
                 TLAtomics.XOR  -> 0x6.U,
diff --git a/src/main/scala/tilelink/BusWrapper.scala b/src/main/scala/tilelink/BusWrapper.scala
index c95a572de1e..41557b04bbd 100644
--- a/src/main/scala/tilelink/BusWrapper.scala
+++ b/src/main/scala/tilelink/BusWrapper.scala
@@ -11,7 +11,7 @@ import org.chipsalliance.diplomacy.bundlebridge._
 import org.chipsalliance.diplomacy.lazymodule._
 import org.chipsalliance.diplomacy.nodes._
 
-import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding}
+import freechips.rocketchip.diplomacy.AddressSet
 
 // TODO This class should be moved to package subsystem to resolve
 //      the dependency awkwardness of the following imports
diff --git a/src/main/scala/tilelink/Edges.scala b/src/main/scala/tilelink/Edges.scala
index ef56eb733c6..0373499ed7d 100644
--- a/src/main/scala/tilelink/Edges.scala
+++ b/src/main/scala/tilelink/Edges.scala
@@ -273,17 +273,17 @@ class TLEdge(
 
   // Does the request need T permissions to be executed?
   def needT(a: TLBundleA): Bool = {
-    val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
+    val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Seq(
       TLPermissions.NtoB -> false.B,
       TLPermissions.NtoT -> true.B,
       TLPermissions.BtoT -> true.B))
-    MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
+    MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Seq(
       TLMessages.PutFullData    -> true.B,
       TLMessages.PutPartialData -> true.B,
       TLMessages.ArithmeticData -> true.B,
       TLMessages.LogicalData    -> true.B,
       TLMessages.Get            -> false.B,
-      TLMessages.Hint           -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
+      TLMessages.Hint           -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Seq(
         TLHints.PREFETCH_READ   -> false.B,
         TLHints.PREFETCH_WRITE  -> true.B)),
       TLMessages.AcquireBlock   -> acq_needT,
diff --git a/src/main/scala/tilelink/ErrorEvaluator.scala b/src/main/scala/tilelink/ErrorEvaluator.scala
index e8931e9c650..127649d0d7e 100644
--- a/src/main/scala/tilelink/ErrorEvaluator.scala
+++ b/src/main/scala/tilelink/ErrorEvaluator.scala
@@ -2,6 +2,8 @@
 
 package freechips.rocketchip.tilelink
 
+import scala.language.implicitConversions
+
 import chisel3._
 
 import org.chipsalliance.cde.config._
diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala
index 68eae711aa2..8634b6233f0 100644
--- a/src/main/scala/tilelink/Fragmenter.scala
+++ b/src/main/scala/tilelink/Fragmenter.scala
@@ -285,7 +285,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
         val maxLgHint        = Mux1H(find, maxLgHints)
 
         val limit = if (alwaysMin) lgMinSize else
-          MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
+          MuxLookup(in_a.bits.opcode, lgMinSize)(Seq(
             TLMessages.PutFullData    -> maxLgPutFull,
             TLMessages.PutPartialData -> maxLgPutPartial,
             TLMessages.ArithmeticData -> maxLgArithmetic,
diff --git a/src/main/scala/tilelink/Monitor.scala b/src/main/scala/tilelink/Monitor.scala
index 0c5586cd583..6475db7fb9c 100644
--- a/src/main/scala/tilelink/Monitor.scala
+++ b/src/main/scala/tilelink/Monitor.scala
@@ -8,8 +8,7 @@ import chisel3.experimental.SourceLine
 
 import org.chipsalliance.cde.config._
 import org.chipsalliance.diplomacy._
-
-import freechips.rocketchip.diplomacy.EnableMonitors
+import org.chipsalliance.diplomacy.EnableMonitors
 import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
 import freechips.rocketchip.util.PlusArg
 
diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala
index b7f02563b66..bd795e24af0 100644
--- a/src/main/scala/tilelink/Xbar.scala
+++ b/src/main/scala/tilelink/Xbar.scala
@@ -113,7 +113,7 @@ object TLXbar
       }
     }
   }
-  def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
+  def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]): Unit = {
     val (io_in, edgesIn) = seqIn.unzip
     val (io_out, edgesOut) = seqOut.unzip
 
diff --git a/src/main/scala/tilelink/package.scala b/src/main/scala/tilelink/package.scala
index 317d4052b08..d5cd88e0cfd 100644
--- a/src/main/scala/tilelink/package.scala
+++ b/src/main/scala/tilelink/package.scala
@@ -18,15 +18,15 @@ package object tilelink
   type TLClientPortParameters = TLMasterPortParameters
 
   implicit class TLClockDomainCrossing(private val x: HasClockDomainCrossing) extends AnyVal {
-    def crossIn (n: TLInwardNode) (implicit valName: ValName) = TLInwardClockCrossingHelper (valName.name, x, n)
-    def crossOut(n: TLOutwardNode)(implicit valName: ValName) = TLOutwardClockCrossingHelper(valName.name, x, n)
+    def crossIn (n: TLInwardNode) (implicit valName: ValName) = TLInwardClockCrossingHelper (valName.value, x, n)
+    def crossOut(n: TLOutwardNode)(implicit valName: ValName) = TLOutwardClockCrossingHelper(valName.value, x, n)
     def cross(n: TLInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: TLOutwardNode)(implicit valName: ValName) = crossOut(n)
   }
 
   implicit class TLResetDomainCrossing(private val x: HasResetDomainCrossing) extends AnyVal {
-    def crossIn (n: TLInwardNode) (implicit valName: ValName) = TLInwardResetCrossingHelper (valName.name, x, n)
-    def crossOut(n: TLOutwardNode)(implicit valName: ValName) = TLOutwardResetCrossingHelper(valName.name, x, n)
+    def crossIn (n: TLInwardNode) (implicit valName: ValName) = TLInwardResetCrossingHelper (valName.value, x, n)
+    def crossOut(n: TLOutwardNode)(implicit valName: ValName) = TLOutwardResetCrossingHelper(valName.value, x, n)
     def cross(n: TLInwardNode) (implicit valName: ValName) = crossIn(n)
     def cross(n: TLOutwardNode)(implicit valName: ValName) = crossOut(n)
   }
diff --git a/src/main/scala/trace/TraceEncoder.scala b/src/main/scala/trace/TraceEncoder.scala
index 361a94008d7..7a26ed3ba0f 100644
--- a/src/main/scala/trace/TraceEncoder.scala
+++ b/src/main/scala/trace/TraceEncoder.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import scala.math.min
 
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.diplomacy._
+import org.chipsalliance.diplomacy.lazymodule._
 
 case class TraceEncoderParams(
   encoderBaseAddr: BigInt,
diff --git a/src/main/scala/trace/TraceSink.scala b/src/main/scala/trace/TraceSink.scala
index ff52e4af4be..1c299356cc3 100644
--- a/src/main/scala/trace/TraceSink.scala
+++ b/src/main/scala/trace/TraceSink.scala
@@ -2,9 +2,9 @@ package freechips.rocketchip.trace
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.lazymodule._
+import freechips.rocketchip.tilelink._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.subsystem._
 
diff --git a/src/main/scala/util/MuxLiteral.scala b/src/main/scala/util/MuxLiteral.scala
index 60fcf2d38dd..f9fabcde7c9 100644
--- a/src/main/scala/util/MuxLiteral.scala
+++ b/src/main/scala/util/MuxLiteral.scala
@@ -46,7 +46,7 @@ object MuxTable
       /* The dense encoding case uses a Vec */
       val table = Array.fill(endIndex.toInt) { default }
       simple.foreach { case (k, v) => table(k.toInt) = v }
-      Mux(index >= endIndex.U, default, VecInit(table)(index))
+      Mux(index >= endIndex.U, default, VecInit(table.toIndexedSeq)(index))
     } else {
       /* The sparse encoding case uses switch */
       val out = WireDefault(default)
diff --git a/src/main/scala/util/PlusArg.scala b/src/main/scala/util/PlusArg.scala
index 59a1b4ec3bc..d9f1584d9ea 100644
--- a/src/main/scala/util/PlusArg.scala
+++ b/src/main/scala/util/PlusArg.scala
@@ -3,7 +3,7 @@
 package freechips.rocketchip.util
 
 import chisel3._
-import chisel3.experimental._
+import chisel3.experimental.{IntParam, StringParam}
 import chisel3.util.HasBlackBoxResource
 
 @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
@@ -32,13 +32,13 @@ trait Doctypeable[A] {
 object Doctypes {
 
   /** Converts an Int => "INT" */
-  implicit val intToDoctype    = new Doctypeable[Int]    { def toDoctype(a: Option[Int])    = "INT"    }
+  implicit val intToDoctype:    Doctypeable[Int]    = new Doctypeable[Int]    { def toDoctype(a: Option[Int])    = "INT"    }
 
   /** Converts a BigInt => "INT" */
-  implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT"    }
+  implicit val bigIntToDoctype: Doctypeable[BigInt] = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT"    }
 
   /** Converts a String => "STRING" */
-  implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
+  implicit val stringToDoctype: Doctypeable[String] = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
 
 }
 
diff --git a/src/main/scala/util/RecordMap.scala b/src/main/scala/util/RecordMap.scala
index fb2b227164c..67445fa7ba8 100644
--- a/src/main/scala/util/RecordMap.scala
+++ b/src/main/scala/util/RecordMap.scala
@@ -13,7 +13,7 @@ final class RecordMap[T <: Data] (eltMap: ListMap[String, T])
   eltMap.foreach { case (name, elt) => requireIsChiselType(elt, name) }
 
   // This is needed for Record
-  val elements = ListMap[String, T]() ++ eltMap.mapValues(chiselTypeClone(_).asInstanceOf[T])  // mapValues return value is lazy
+  val elements = ListMap[String, T]() ++ eltMap.view.mapValues(chiselTypeClone(_).asInstanceOf[T]) // view is lazy
 
   def apply(x: Int) = elements.values.toSeq(x)
   def apply(x: String) = elements.get(x)
diff --git a/src/main/scala/util/ShiftQueue.scala b/src/main/scala/util/ShiftQueue.scala
index a1790b04c6c..efa7f56feca 100644
--- a/src/main/scala/util/ShiftQueue.scala
+++ b/src/main/scala/util/ShiftQueue.scala
@@ -15,7 +15,7 @@ class ShiftQueue[T <: Data](gen: T,
                             flow: Boolean = false)
     extends Module {
   val io = IO(new QueueIO(gen, entries) {
-    val mask = Output(UInt(entries.W))
+    val mask = Output(UInt(ShiftQueue.this.entries.W))
   })
 
   private val valid = RegInit(VecInit(Seq.fill(entries) { false.B }))
diff --git a/src/main/scala/util/package.scala b/src/main/scala/util/package.scala
index e1443d13298..4f26e8af93e 100644
--- a/src/main/scala/util/package.scala
+++ b/src/main/scala/util/package.scala
@@ -4,6 +4,7 @@ package freechips.rocketchip
 
 import chisel3._
 import chisel3.util._
+import scala.language.implicitConversions
 import scala.math.min
 import scala.collection.{immutable, mutable}
 
@@ -102,7 +103,7 @@ package object util {
 
   implicit class StringToAugmentedString(private val x: String) extends AnyVal {
     /** converts from camel case to to underscores, also removing all spaces */
-    def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
+    def underscore: String = x.tail.foldLeft(x.headOption.map(c => s"${c.toLower}") getOrElse "") {
       case (acc, c) if c.isUpper => acc + "_" + c.toLower
       case (acc, c) if c == ' ' => acc
       case (acc, c) => acc + c