From e8ab19eabe48a350c82dbba277184e0ec6877dd1 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Tue, 24 Mar 2026 15:18:03 -0700 Subject: [PATCH] Fix AHBToTL elaboration error due to missing user fields Without this change, the following error shows up when connecting an AHBSlaveSourceNode (which can model an external AHB master port) through AHBToTL: [error] generators/rocket-chip/src/main/scala/amba/ahb/ToTL.scala 121:19: unconnected consumer field AHBToTL.d_user.amba_prot: Reg[AMBAProtBundle] [error] d_user :<= in.hauser [error] ^ [error] There were 1 error(s) during hardware elaboration. --- src/main/scala/amba/ahb/Test.scala | 36 +++++++++++++++++++++++++-- src/main/scala/amba/ahb/ToTL.scala | 6 ++++- src/main/scala/unittest/Configs.scala | 1 + 3 files changed, 40 insertions(+), 3 deletions(-) diff --git a/src/main/scala/amba/ahb/Test.scala b/src/main/scala/amba/ahb/Test.scala index 43a57977dcc..8b14b644b65 100644 --- a/src/main/scala/amba/ahb/Test.scala +++ b/src/main/scala/amba/ahb/Test.scala @@ -6,12 +6,12 @@ import chisel3._ import org.chipsalliance.cde.config.Parameters -import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp, SimpleLazyModule} +import org.chipsalliance.diplomacy.lazymodule.{InModuleBody, LazyModule, LazyModuleImp, SimpleLazyModule} import freechips.rocketchip.devices.tilelink.TLTestRAM import freechips.rocketchip.diplomacy.{AddressSet, BufferParams} import freechips.rocketchip.regmapper.{RRTest0, RRTest1} -import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLToAHB, TLDelayer, TLBuffer, TLErrorEvaluator, TLFragmenter} +import freechips.rocketchip.tilelink.{TLFuzzer, TLRAMModel, TLRAM, TLToAHB, TLDelayer, TLBuffer, TLErrorEvaluator, TLFragmenter} import freechips.rocketchip.unittest.{UnitTestModule, UnitTest} class AHBRRTest0(address: BigInt)(implicit p: Parameters) @@ -113,3 +113,35 @@ class AHBBridgeTest(aFlow: Boolean, txns: Int = 5000, timeout: Int = 500000)(imp io.finished := dut.io.finished dut.io.start := io.start } + +/** Test that AHBToTL elaborates when driven by an AHBSlaveSourceNode. */ +class AHBSourceToTLSlave()(implicit p: Parameters) extends SimpleLazyModule { + val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff))) + + val ahbMaster = AHBSlaveSourceNode( + Seq(AHBMasterPortParameters(masters = Seq(AHBMasterParameters(name = "test_ahb_master")))) + ) + + (ram.node + := AHBToTL() + := ahbMaster) + + val idle = InModuleBody { + val (bundle, _) = ahbMaster.out.head + bundle.htrans := 0.U // idle + bundle.hsize := 0.U + bundle.hburst := 0.U + bundle.hwrite := false.B + bundle.hprot := 0.U + bundle.haddr := 0.U + bundle.hwdata := 0.U + bundle.hmastlock := false.B + bundle.hsel := false.B + bundle.hready := true.B + } +} + +class AHBSourceToTLSlaveTest(timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { + val dut = Module(LazyModule(new AHBSourceToTLSlave()).module) + io.finished := true.B +} diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index e34d7c262ba..c0f49da82b9 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -118,7 +118,11 @@ class AHBToTL()(implicit p: Parameters) extends LazyModule d_write := in.hwrite d_addr := in.haddr d_size := Mux(a_burst_ok, a_burst_size, in.hsize) - d_user :<= in.hauser + + Connectable.waiveUnmatched(d_user, in.hauser) match { + case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll + } + d_user.lift(AMBAProt).foreach { x => x.fetch := !in.hprot(0) x.privileged := in.hprot(1) diff --git a/src/main/scala/unittest/Configs.scala b/src/main/scala/unittest/Configs.scala index 655811576b8..7e306289b4a 100644 --- a/src/main/scala/unittest/Configs.scala +++ b/src/main/scala/unittest/Configs.scala @@ -27,6 +27,7 @@ class WithAMBAUnitTests extends Config((site, here, up) => { Module(new AHBBridgeTest(true, txns=8*txns, timeout=timeout)), Module(new AHBNativeTest(true, txns=6*txns, timeout=timeout)), Module(new AHBNativeTest(false, txns=6*txns, timeout=timeout)), + Module(new AHBSourceToTLSlaveTest( timeout=timeout)), Module(new APBBridgeTest(true, txns=6*txns, timeout=timeout)), Module(new APBBridgeTest(false, txns=6*txns, timeout=timeout)), Module(new AXI4LiteFuzzRAMTest( txns=6*txns, timeout=timeout)),