From 1899717a81f21dd868183cdbbded54ee966b7ad3 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Thu, 9 Sep 2021 19:34:58 -0300 Subject: [PATCH 01/10] add hdl for buttons and example program --- Makefile | 2 +- README.md | 308 ++++++++++++++++------------------- README_grahamedgecombe.md | 174 ++++++++++++++++++++ icicle.sv | 16 +- programs/buttons2leds/main.c | 47 ++++++ top.sv | 6 + 6 files changed, 383 insertions(+), 170 deletions(-) create mode 100644 README_grahamedgecombe.md create mode 100644 programs/buttons2leds/main.c diff --git a/Makefile b/Makefile index e1e7b38..e2e9ebf 100644 --- a/Makefile +++ b/Makefile @@ -16,7 +16,7 @@ SVF = $(TOP).svf TIME_RPT = $(TOP).rpt STAT = $(TOP).stat BOARD ?= ice40hx8k-b-evn -PROGRAM ?= hello +PROGRAM ?= buttons2leds C_SRC = $(filter-out programs/uip/fsdata.c, $(wildcard programs/$(PROGRAM)/*.c)) OBJ = $(sort $(addsuffix .o, $(basename $(C_SRC))) start.o) TARGET ?= riscv64-unknown-elf diff --git a/README.md b/README.md index 8a7c3f2..7ba14cf 100644 --- a/README.md +++ b/README.md @@ -1,174 +1,148 @@ -# Icicle +# Icicle en EDU-FPGA -## Introduction +Instrucciones específicas para [EDU-FPGA](http://www.proyecto-ciaa.com.ar/devwiki/doku.php?id=desarrollo%3Aedu-fpga): -Icicle is a 32-bit [RISC-V][riscv] system on chip for [iCE40 HX8K][ice40], -[iCE40 UP5K][ice40-up5k] and [ECP5][ecp5] FPGAs. It can be built with the -open-source [SymbiFlow][symbiflow] toolchain and currently targets several -development boards. +## Instalación nativa de las herramientas -## Current features +Estos pasos fueron probados con `Linux Mint 20 Cinnamon` en un sistema de 64-bits `x86_64`. -* RV32I core with a [classic 5-stage RISC pipeline][classic-risc], static branch - prediction, bypassing and interlocking. It currently implements the entire - [user ISA][riscv-user] parts of the [privileged ISA][riscv-priv]. -* Shared instruction and data memory (8 KiB, implemented with FPGA block RAM). -* Memory-mapped UART and LEDs. -* Memory-mapped SPI flash. +### Prerrequisitos -## Dependencies +- Crear un directorio de trabajo y posicionarse en él. +``` +mkdir -p ~/edufpga-icicle/ +cd ~/edufpga-icicle/ +``` -* [GNU Make][make] -* [GNU RISC-V toolchain][riscv-gnu] -* [Icarus Verilog][iverilog] (`master` branch) -* [nextpnr][nextpnr] or [arachne-pnr][arachne-pnr] -* [Project IceStorm][icestorm] or [Project Trellis][trellis] -* [vim][vim] (for `xxd`) -* [Yosys][yosys] (`master` branch) +- Instalar dependencias disponibles en el repositorio (`make`, `vim`, entre otras necesarias para construir las herramientas). -## Building and testing - -### Supported boards - -Icicle supports several development boards: - -* `blackice-ii`: [BlackIce II][blackice-ii-board] -* `ecp5-evn`: [ECP5 evaluation board][ecp5-evn] -* `edufpga`: [EDU-CIAA-FPGA iCE40-HX4k board](./EDU-FPGA.md) -* `ice40hx8k-b-evn`: [iCE40-HX8K breakout board][ice40-hx8k-breakout] -* `icebreaker`: [iCEBreaker][icebreaker] -* `upduino`: [UPduino][upduino] - -`` should be replaced with the internal name of your development board in -the rest of the instructions (e.g. `ice40hx8k-b-evn` for the iCE40-HX8K breakout -board). - -### Building - -* Run `make BOARD= syntax` to check the syntax with [Icarus][iverilog], - which has a stricter parser than [Yosys][yosys]. At the time of writing the - `master` branch of Icarus is required as there isn't a stable release with - `always_comb`/`always_ff` support yet. -* Run `make BOARD=` to synthesize the design, place and route, compile - the demo program in `progmem.c` and create the bitstream. - -### Programming - -#### BlackIce II - -* Configure jumper on board for [DFU Mode][dfu-mode] and connect both USB1 and - USB2 on the board to host USB ports. -* Run `make BOARD=blackice-ii dfu-flash` to flash the bitstream. - -#### ECP5 evaluation board - -* Remove R22, R23 and R24 to disconnect the channel B of the FTDI chip from the - I2C bus. -* Populate R34 and R35 with zero-ohm resistors to connect channel B of the FTDI - chip to the UART RX and TX pins. -* Optionally populate R21 with a zero-ohm resistor to enable the UART TX - indicator LED. - -#### EDU-FPGA - -* Run `make BOARD=edufpga flash` to flash the bitstream. - -#### iCE40-HX8K breakout board - -* Configure the jumpers for flash programming. -* Run `make BOARD=ice40hx8k-b-evn flash` to flash the bitstream. - -### Testing - -* If your chosen board has built-in LEDs, some of the LEDs should turn on and blink. -* Run `picocom -b 9600 /dev/ttyUSBn` (replacing `ttyUSBn` with the name of the - serial port) to connect to the serial port. `Hello, world!` should be printed - once per second. - -### Other targets - -The `make BOARD= stat` target runs `icebox_stat` and the -`make BOARD= time` target prints the `icetime` report. - -The `Makefile` runs the [IceStorm][icestorm] toolchain in quiet mode. Unset the -`QUIET` variable to run the toolchain in verbose mode - e.g. -`make BOARD= QUIET= ...`. - -Set the `PNR` variable to `arachne-pnr` to use [arachne-pnr][arachne-pnr] -instead of [nextpnr][nextpnr] (the default) - e.g. `make PNR=arachne-pnr`. - -## Formal verification - -Icicle supports the RISC-V Formal Interface (RVFI), allowing it to be formally -verified with [SymbiYosys][symbiyosys] and [riscv-formal][riscv-formal]: - -* Run `git clone https://github.com/SymbioticEDA/riscv-formal` to clone - riscv-formal. -* Run `cd riscv-formal/cores && git clone https://github.com/grahamedgecombe/icicle` - to clone Icicle in the `cores` subdirectory. -* Run ``cd icicle && python ../../checks/genchecks.py && make -C checks -j `nproc``` - to verify the core. - -## Planned features - -* Use remaining block RAM tiles to eke out as much memory as possible. -* Use the SPRAM tiles on UP5K devices. -* Implement remaining bits of the user ISA. -* Implement machine mode from the privileged ISA. -* Interrupts/exceptions. -* Unaligned memory access support. -* Memory-mapped GPIOs. -* Add XIP, DDR, DSPI and QSPI support to the SPI flash controller. -* Improved reset support (a reset signal + boot ROM to zero all the registers). -* Automated tests. -* Multiply/divide support. -* Compressed instruction support. -* Add flags to disable certain features (e.g. privileged mode) to save LUTs on - smaller devices (e.g. the UP5K). -* Investigate using DSP tiles on the UP5K. - -## Size and performance - -The entire system on chip currently occupies around 3,000 LUTs on an iCE40 when -synthesized with [Yosys][yosys]. - -If bypassing and branch prediction are disabled [nextpnr][nextpnr] estimates it -can be clocked at around 50 MHz on a HX series device and 20 MHz on a UP series -device. - -The core is capable of issuing and retiring one instruction per clock cycle, -although the actual number of instructions per cycle will be slightly less than -this in practice due to interlocking, branch mispredictions and the shared -memory bus. - -## License - -This project is available under the terms of the ISC license, which is similar -to the 2-clause BSD license. See the `LICENSE` file for the copyright -information and licensing terms. - -[arachne-pnr]: https://github.com/cseed/arachne-pnr#readme -[blackice-ii-board]: https://github.com/mystorm-org/BlackIce-II#readme -[classic-risc]: https://en.wikipedia.org/wiki/Classic_RISC_pipeline -[dfu-mode]: https://github.com/mystorm-org/BlackIce-II/wiki/DFU-operations-on-the-BlackIce-II -[ecp5-evn]: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard.aspx -[ecp5]: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx -[ice40-hx8k-breakout]: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx -[ice40-up5k]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx -[ice40]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx -[icebreaker]: https://github.com/icebreaker-fpga/ -[icestorm]: http://www.clifford.at/icestorm/ -[iverilog]: http://iverilog.icarus.com/ -[make]: https://www.gnu.org/software/make/ -[nextpnr]: https://github.com/YosysHQ/nextpnr#readme -[riscv-formal]: https://github.com/SymbioticEDA/riscv-formal -[riscv-gnu]: https://github.com/riscv/riscv-gnu-toolchain#readme -[riscv-priv]: https://riscv.org/specifications/privileged-isa/ -[riscv-user]: https://riscv.org/specifications/ -[riscv]: https://riscv.org/risc-v-isa/ -[symbiflow]: https://symbiflow.github.io/ -[symbiyosys]: https://symbiyosys.readthedocs.io/ -[trellis]: https://github.com/SymbiFlow/prjtrellis#readme -[upduino]: http://gnarlygrey.atspace.cc/development-platform.html#upduino -[vim]: https://www.vim.org/ -[yosys]: http://www.clifford.at/yosys/ +``` +sudo apt update +sudo apt install git make arachne-pnr fpga-icestorm vim autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev gtkterm clang libreadline-dev tcl-dev libffi-dev graphviz xdot pkg-config libboost-system-dev libboost-python-dev libboost-filesystem-dev mercurial libftdi-dev qt5-default python3-dev libboost-all-dev cmake libeigen3-dev +``` + +### Toolchain RISC-V + +Clonar y construir el toolchain para `RV32I`. La instalación necesita privilegios de root. + +**NOTA**: Este repositorio es grande (~7GB). Clonarlo y luego construirlo lleva tiempo, ¡paciencia! + +``` +cd ~/edufpga-icicle/ +git clone --recursive https://github.com/riscv/riscv-gnu-toolchain +cd riscv-gnu-toolchain + +./configure --prefix=/opt/riscv +sudo make # compila e instala +``` + +### Icarus Verilog + +La instalación necesita privilegios de root. + +``` +cd ~/edufpga-icicle/ +git clone git://github.com/steveicarus/iverilog.git +cd iverilog +sh autoconf.sh +./configure +make +sudo make install +``` + +### IceStorm + +La instalación necesita privilegios de root. + +``` +cd ~/edufpga-icicle/ +git clone https://github.com/YosysHQ/icestorm.git icestorm +cd icestorm +make -j$(nproc) +sudo make install +``` + +### NextPNR + +La instalación necesita privilegios de root. + +``` +cd ~/edufpga-icicle/ +git clone https://github.com/YosysHQ/nextpnr nextpnr --recursive +cd nextpnr +cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . +make -j$(nproc) +sudo make install +``` + +### Yosys + +La instalación necesita privilegios de root. + +``` +cd ~/edufpga-icicle/ +git clone https://github.com/YosysHQ/yosys.git yosys +cd yosys +make config-gcc +make -j$(nproc) +sudo make install +``` + +## Generación del bitstream + +- Asegurar que el compilador esté disponible en `PATH`: +``` +export PATH=/opt/riscv/bin/:$PATH +``` +Así el comando `riscv64-unknown-elf-gcc` debería ser accesible. + +- Clonar repositorio, construir y grabar memoria SPI de la EDU-FPGA: +``` +cd ~/edufpga-icicle/ +git clone https://github.com/ciaa/icicle.git +cd icicle +make BOARD=edufpga +# antes de ejecutar el siguiente comando, conectar la EDU-FPGA a la PC +make BOARD=edufpga flash +``` + +Así se ve la salida típica de estos comandos: + +``` +$ make BOARD=edufpga +riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=36000000 -Os -ffreestanding -nostartfiles -g -Iprograms/hello -c -o programs/hello/main.o programs/hello/main.c +riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=36000000 -Os -ffreestanding -nostartfiles -g -Iprograms/hello -Wl,-Tprogmem.lds -o progmem programs/hello/main.o start.o +riscv64-unknown-elf-objcopy -O binary progmem progmem.bin +xxd -p -c 4 < progmem.bin > progmem.hex +yosys -q ice40.ys +arachne-pnr -q -d 8k -P tq144:4k -o top_syn.asc -p boards/edufpga.pcf top.blif +icebram progmem_syn.hex progmem.hex < top_syn.asc > top.asc +icepack top.asc top.bin +``` +``` +$ make BOARD=edufpga flash +icetime -t -m -d hx8k -P tq144:4k -p boards/edufpga.pcf -c 36 -r top.rpt top_syn.asc +// Reading input .pcf file.. +// Reading input .asc file.. +// Reading 8k chipdb file.. +// Creating timing netlist.. +// Timing estimate: 27.43 ns (36.45 MHz) +// Checking 27.78 ns (36.00 MHz) clock constraint: PASSED. +iceprog top.bin +init.. +cdone: high +reset.. +cdone: low +flash ID: 0xEF 0x30 0x13 0x00 +file size: 135100 +erase 64kB sector at 0x000000.. +erase 64kB sector at 0x010000.. +erase 64kB sector at 0x020000.. +programming.. +reading.. +VERIFY OK +cdone: high +Bye. +``` + +¡Listo! Deberías ver destellar los LEDs de la EDU-FPGA y por la UART (`/dev/ttyUSB1`) deberías observar el mensaje `Hello, world!`. diff --git a/README_grahamedgecombe.md b/README_grahamedgecombe.md new file mode 100644 index 0000000..8a7c3f2 --- /dev/null +++ b/README_grahamedgecombe.md @@ -0,0 +1,174 @@ +# Icicle + +## Introduction + +Icicle is a 32-bit [RISC-V][riscv] system on chip for [iCE40 HX8K][ice40], +[iCE40 UP5K][ice40-up5k] and [ECP5][ecp5] FPGAs. It can be built with the +open-source [SymbiFlow][symbiflow] toolchain and currently targets several +development boards. + +## Current features + +* RV32I core with a [classic 5-stage RISC pipeline][classic-risc], static branch + prediction, bypassing and interlocking. It currently implements the entire + [user ISA][riscv-user] parts of the [privileged ISA][riscv-priv]. +* Shared instruction and data memory (8 KiB, implemented with FPGA block RAM). +* Memory-mapped UART and LEDs. +* Memory-mapped SPI flash. + +## Dependencies + +* [GNU Make][make] +* [GNU RISC-V toolchain][riscv-gnu] +* [Icarus Verilog][iverilog] (`master` branch) +* [nextpnr][nextpnr] or [arachne-pnr][arachne-pnr] +* [Project IceStorm][icestorm] or [Project Trellis][trellis] +* [vim][vim] (for `xxd`) +* [Yosys][yosys] (`master` branch) + +## Building and testing + +### Supported boards + +Icicle supports several development boards: + +* `blackice-ii`: [BlackIce II][blackice-ii-board] +* `ecp5-evn`: [ECP5 evaluation board][ecp5-evn] +* `edufpga`: [EDU-CIAA-FPGA iCE40-HX4k board](./EDU-FPGA.md) +* `ice40hx8k-b-evn`: [iCE40-HX8K breakout board][ice40-hx8k-breakout] +* `icebreaker`: [iCEBreaker][icebreaker] +* `upduino`: [UPduino][upduino] + +`` should be replaced with the internal name of your development board in +the rest of the instructions (e.g. `ice40hx8k-b-evn` for the iCE40-HX8K breakout +board). + +### Building + +* Run `make BOARD= syntax` to check the syntax with [Icarus][iverilog], + which has a stricter parser than [Yosys][yosys]. At the time of writing the + `master` branch of Icarus is required as there isn't a stable release with + `always_comb`/`always_ff` support yet. +* Run `make BOARD=` to synthesize the design, place and route, compile + the demo program in `progmem.c` and create the bitstream. + +### Programming + +#### BlackIce II + +* Configure jumper on board for [DFU Mode][dfu-mode] and connect both USB1 and + USB2 on the board to host USB ports. +* Run `make BOARD=blackice-ii dfu-flash` to flash the bitstream. + +#### ECP5 evaluation board + +* Remove R22, R23 and R24 to disconnect the channel B of the FTDI chip from the + I2C bus. +* Populate R34 and R35 with zero-ohm resistors to connect channel B of the FTDI + chip to the UART RX and TX pins. +* Optionally populate R21 with a zero-ohm resistor to enable the UART TX + indicator LED. + +#### EDU-FPGA + +* Run `make BOARD=edufpga flash` to flash the bitstream. + +#### iCE40-HX8K breakout board + +* Configure the jumpers for flash programming. +* Run `make BOARD=ice40hx8k-b-evn flash` to flash the bitstream. + +### Testing + +* If your chosen board has built-in LEDs, some of the LEDs should turn on and blink. +* Run `picocom -b 9600 /dev/ttyUSBn` (replacing `ttyUSBn` with the name of the + serial port) to connect to the serial port. `Hello, world!` should be printed + once per second. + +### Other targets + +The `make BOARD= stat` target runs `icebox_stat` and the +`make BOARD= time` target prints the `icetime` report. + +The `Makefile` runs the [IceStorm][icestorm] toolchain in quiet mode. Unset the +`QUIET` variable to run the toolchain in verbose mode - e.g. +`make BOARD= QUIET= ...`. + +Set the `PNR` variable to `arachne-pnr` to use [arachne-pnr][arachne-pnr] +instead of [nextpnr][nextpnr] (the default) - e.g. `make PNR=arachne-pnr`. + +## Formal verification + +Icicle supports the RISC-V Formal Interface (RVFI), allowing it to be formally +verified with [SymbiYosys][symbiyosys] and [riscv-formal][riscv-formal]: + +* Run `git clone https://github.com/SymbioticEDA/riscv-formal` to clone + riscv-formal. +* Run `cd riscv-formal/cores && git clone https://github.com/grahamedgecombe/icicle` + to clone Icicle in the `cores` subdirectory. +* Run ``cd icicle && python ../../checks/genchecks.py && make -C checks -j `nproc``` + to verify the core. + +## Planned features + +* Use remaining block RAM tiles to eke out as much memory as possible. +* Use the SPRAM tiles on UP5K devices. +* Implement remaining bits of the user ISA. +* Implement machine mode from the privileged ISA. +* Interrupts/exceptions. +* Unaligned memory access support. +* Memory-mapped GPIOs. +* Add XIP, DDR, DSPI and QSPI support to the SPI flash controller. +* Improved reset support (a reset signal + boot ROM to zero all the registers). +* Automated tests. +* Multiply/divide support. +* Compressed instruction support. +* Add flags to disable certain features (e.g. privileged mode) to save LUTs on + smaller devices (e.g. the UP5K). +* Investigate using DSP tiles on the UP5K. + +## Size and performance + +The entire system on chip currently occupies around 3,000 LUTs on an iCE40 when +synthesized with [Yosys][yosys]. + +If bypassing and branch prediction are disabled [nextpnr][nextpnr] estimates it +can be clocked at around 50 MHz on a HX series device and 20 MHz on a UP series +device. + +The core is capable of issuing and retiring one instruction per clock cycle, +although the actual number of instructions per cycle will be slightly less than +this in practice due to interlocking, branch mispredictions and the shared +memory bus. + +## License + +This project is available under the terms of the ISC license, which is similar +to the 2-clause BSD license. See the `LICENSE` file for the copyright +information and licensing terms. + +[arachne-pnr]: https://github.com/cseed/arachne-pnr#readme +[blackice-ii-board]: https://github.com/mystorm-org/BlackIce-II#readme +[classic-risc]: https://en.wikipedia.org/wiki/Classic_RISC_pipeline +[dfu-mode]: https://github.com/mystorm-org/BlackIce-II/wiki/DFU-operations-on-the-BlackIce-II +[ecp5-evn]: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard.aspx +[ecp5]: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx +[ice40-hx8k-breakout]: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx +[ice40-up5k]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx +[ice40]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx +[icebreaker]: https://github.com/icebreaker-fpga/ +[icestorm]: http://www.clifford.at/icestorm/ +[iverilog]: http://iverilog.icarus.com/ +[make]: https://www.gnu.org/software/make/ +[nextpnr]: https://github.com/YosysHQ/nextpnr#readme +[riscv-formal]: https://github.com/SymbioticEDA/riscv-formal +[riscv-gnu]: https://github.com/riscv/riscv-gnu-toolchain#readme +[riscv-priv]: https://riscv.org/specifications/privileged-isa/ +[riscv-user]: https://riscv.org/specifications/ +[riscv]: https://riscv.org/risc-v-isa/ +[symbiflow]: https://symbiflow.github.io/ +[symbiyosys]: https://symbiyosys.readthedocs.io/ +[trellis]: https://github.com/SymbiFlow/prjtrellis#readme +[upduino]: http://gnarlygrey.atspace.cc/development-platform.html#upduino +[vim]: https://www.vim.org/ +[yosys]: http://www.clifford.at/yosys/ diff --git a/icicle.sv b/icicle.sv index bda3441..dac20c7 100644 --- a/icicle.sv +++ b/icicle.sv @@ -38,6 +38,9 @@ module icicle ( /* LEDs */ output logic [7:0] leds, + /* BUTTONS */ + input [7:0] buttons, + /* UART */ input uart_rx, output logic uart_tx @@ -69,8 +72,8 @@ module icicle ( logic mem_ready; logic mem_fault; - assign mem_read_value = ram_read_value | leds_read_value | uart_read_value | timer_read_value | flash_read_value; - assign mem_ready = ram_ready | leds_ready | uart_ready | timer_ready | flash_ready | mem_fault; + assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | uart_read_value | timer_read_value | flash_read_value; + assign mem_ready = ram_ready | leds_ready | buttons_ready | uart_ready | timer_ready | flash_ready | mem_fault; bus_arbiter bus_arbiter ( .clk(clk), @@ -135,6 +138,7 @@ module icicle ( logic ram_sel; logic leds_sel; + logic buttons_sel; logic uart_sel; logic timer_sel; logic flash_sel; @@ -142,6 +146,7 @@ module icicle ( always_comb begin ram_sel = 0; leds_sel = 0; + buttons_sel = 0; uart_sel = 0; timer_sel = 0; flash_sel = 0; @@ -150,6 +155,7 @@ module icicle ( casez (mem_address) 32'b00000000_00000000_????????_????????: ram_sel = 1; 32'b00000000_00000001_00000000_000000??: leds_sel = 1; + 32'b00000000_00000001_00000000_000001??: buttons_sel = 1; 32'b00000000_00000010_00000000_0000????: uart_sel = 1; 32'b00000000_00000011_00000000_0000????: timer_sel = 1; 32'b00000001_????????_????????_????????: flash_sel = 1; @@ -186,6 +192,12 @@ module icicle ( leds <= mem_write_value[7:0]; end + logic [31:0] buttons_read_value; + logic buttons_ready; + + assign buttons_read_value = {24'b0, buttons_sel ? buttons : 8'b0}; + assign buttons_ready = buttons_sel; + logic [31:0] uart_read_value; logic uart_ready; diff --git a/programs/buttons2leds/main.c b/programs/buttons2leds/main.c new file mode 100644 index 0000000..4692136 --- /dev/null +++ b/programs/buttons2leds/main.c @@ -0,0 +1,47 @@ +#include + +// 32'b00000000_00000001_00000000_000000??: leds_sel = 1; +// 32'b00000000_00000001_00000000_000001??: buttons_sel = + +#define LEDS *((volatile uint32_t *) 0x00010000) +#define BUTTONS *((volatile uint32_t *) 0x00010004) +#define UART_BAUD *((volatile uint32_t *) 0x00020000) +#define UART_STATUS *((volatile uint32_t *) 0x00020004) +#define UART_DATA *((volatile int32_t *) 0x00020008) +#define MTIME *((volatile uint64_t *) 0x00030000) +#define MTIMECMP *((volatile uint64_t *) 0x00030008) + +#define UART_STATUS_TX_READY 0x1 +#define UART_STATUS_RX_READY 0x2 + +#define BAUD_RATE 9600 + +static void uart_putc(char c) { + while (!(UART_STATUS & UART_STATUS_TX_READY)); + UART_DATA = c; +} + +static void uart_puts(const char *str) { + char c; + while ((c = *str++)) { + uart_putc(c); + } +} + +static inline uint32_t rdcycle(void) { + uint32_t cycle; + asm volatile ("rdcycle %0" : "=r"(cycle)); + return cycle; +} + +int main() { + UART_BAUD = FREQ / BAUD_RATE; + LEDS = 0xAA; + + for (;;) { + uart_puts("Press buttons, should turn on leds!\r\n"); + LEDS = ~BUTTONS; + uint32_t start = rdcycle(); + while ((rdcycle() - start) <= FREQ); + } +} diff --git a/top.sv b/top.sv index 3407044..fa1e314 100644 --- a/top.sv +++ b/top.sv @@ -19,6 +19,9 @@ module top ( /* LEDs */ output logic [7:0] leds, + /* BUTTONS */ + input [7:0] buttons, + /* UART */ input uart_rx, output logic uart_tx @@ -126,6 +129,9 @@ module top ( /* LEDs */ .leds(leds), + /* BUTTONs */ + .buttons(buttons), + /* UART */ .uart_rx(uart_rx), .uart_tx(uart_tx) From ab15a2723f4451dce795e9f865c0985543f1eb82 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Fri, 10 Sep 2021 10:00:29 -0300 Subject: [PATCH 02/10] forgotten commit --- README.md | 62 ++++++++++++++++++++++++++++++++-------------- boards/edufpga.pcf | 10 ++++++++ 2 files changed, 53 insertions(+), 19 deletions(-) diff --git a/README.md b/README.md index 7ba14cf..90c75b5 100644 --- a/README.md +++ b/README.md @@ -1,24 +1,27 @@ -# Icicle en EDU-FPGA +# XXXX en icicle en EDU-FPGA + + Instrucciones específicas para [EDU-FPGA](http://www.proyecto-ciaa.com.ar/devwiki/doku.php?id=desarrollo%3Aedu-fpga): ## Instalación nativa de las herramientas -Estos pasos fueron probados con `Linux Mint 20 Cinnamon` en un sistema de 64-bits `x86_64`. +Estos pasos fueron probados con `Linux Mint 21 Mate` en un sistema de 64-bits `x86_64`. ### Prerrequisitos - Crear un directorio de trabajo y posicionarse en él. ``` -mkdir -p ~/edufpga-icicle/ -cd ~/edufpga-icicle/ +mkdir -p ~/workspace/ +cd ~/workspace/ ``` -- Instalar dependencias disponibles en el repositorio (`make`, `vim`, entre otras necesarias para construir las herramientas). +- Instalar dependencias disponibles en el repositorio. ``` sudo apt update -sudo apt install git make arachne-pnr fpga-icestorm vim autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev gtkterm clang libreadline-dev tcl-dev libffi-dev graphviz xdot pkg-config libboost-system-dev libboost-python-dev libboost-filesystem-dev mercurial libftdi-dev qt5-default python3-dev libboost-all-dev cmake libeigen3-dev +sudo apt install gperf build-essential cmake python3-dev texinfo vim libboost-all-dev tcl-dev libreadline-dev libffi-dev libeigen3-dev + ``` ### Toolchain RISC-V @@ -28,11 +31,11 @@ Clonar y construir el toolchain para `RV32I`. La instalación necesita privilegi **NOTA**: Este repositorio es grande (~7GB). Clonarlo y luego construirlo lleva tiempo, ¡paciencia! ``` -cd ~/edufpga-icicle/ +cd ~/workspace/ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -./configure --prefix=/opt/riscv +./configure sudo make # compila e instala ``` @@ -41,7 +44,7 @@ sudo make # compila e instala La instalación necesita privilegios de root. ``` -cd ~/edufpga-icicle/ +cd ~/workspace/ git clone git://github.com/steveicarus/iverilog.git cd iverilog sh autoconf.sh @@ -55,7 +58,7 @@ sudo make install La instalación necesita privilegios de root. ``` -cd ~/edufpga-icicle/ +cd ~/workspace/ git clone https://github.com/YosysHQ/icestorm.git icestorm cd icestorm make -j$(nproc) @@ -67,7 +70,7 @@ sudo make install La instalación necesita privilegios de root. ``` -cd ~/edufpga-icicle/ +cd ~/workspace/ git clone https://github.com/YosysHQ/nextpnr nextpnr --recursive cd nextpnr cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . @@ -80,7 +83,7 @@ sudo make install La instalación necesita privilegios de root. ``` -cd ~/edufpga-icicle/ +cd ~/workspace/ git clone https://github.com/YosysHQ/yosys.git yosys cd yosys make config-gcc @@ -88,19 +91,29 @@ make -j$(nproc) sudo make install ``` -## Generación del bitstream +## Permisos -- Asegurar que el compilador esté disponible en `PATH`: +Para que `iceprog` pueda acceder a la placa, puede hacer falta: + ``` -export PATH=/opt/riscv/bin/:$PATH +echo 'ACTION=="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE:="666"' |\ +sudo tee -a /etc/udev/rules.d/70-lattice.rules 1>/dev/null +sudo service udev restart ``` -Así el comando `riscv64-unknown-elf-gcc` debería ser accesible. +## Conexión en Virtual Box + +No te olvides de conectar a la virtual: + +Devices -> USB -> FTDI Dual RS232-HS[0700] + +## Generación del bitstream + - Clonar repositorio, construir y grabar memoria SPI de la EDU-FPGA: ``` -cd ~/edufpga-icicle/ -git clone https://github.com/ciaa/icicle.git -cd icicle +cd ~/workspace/ +git clone https://github.com/cpantel/XXX.git +cd XXX make BOARD=edufpga # antes de ejecutar el siguiente comando, conectar la EDU-FPGA a la PC make BOARD=edufpga flash @@ -146,3 +159,14 @@ Bye. ``` ¡Listo! Deberías ver destellar los LEDs de la EDU-FPGA y por la UART (`/dev/ttyUSB1`) deberías observar el mensaje `Hello, world!`. + +``` +$ cat /dev/ttyUSB1 +Hello, world! + +Hello, world! + +Hello, world! +``` + + diff --git a/boards/edufpga.pcf b/boards/edufpga.pcf index ce84c79..373bc71 100644 --- a/boards/edufpga.pcf +++ b/boards/edufpga.pcf @@ -7,5 +7,15 @@ set_io leds[4] 7 set_io leds[5] 8 set_io leds[6] 9 set_io leds[7] 10 + +set_io buttons[0] 31 +set_io buttons[1] 32 +set_io buttons[2] 33 +set_io buttons[3] 34 +set_io buttons[4] 11 +set_io buttons[5] 12 +set_io buttons[6] 15 +set_io buttons[7] 16 + set_io uart_rx 55 set_io uart_tx 56 From a309dbee30d6e9d6ab98d98de51181275f68da57 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Wed, 15 Sep 2021 19:15:02 -0300 Subject: [PATCH 03/10] failed to unhardcode leds and buttons length --- boards/edufpga.pcf | 78 ++++++++++++++++++++++++++++++++++++++++++---- icicle.sv | 10 +++--- top.sv | 9 ++++-- 3 files changed, 83 insertions(+), 14 deletions(-) diff --git a/boards/edufpga.pcf b/boards/edufpga.pcf index 373bc71..31cb9a3 100644 --- a/boards/edufpga.pcf +++ b/boards/edufpga.pcf @@ -1,21 +1,87 @@ +# set_io clk 94 +set_io uart_rx 55 +set_io uart_tx 56 + +# real board leds set_io leds[0] 1 set_io leds[1] 2 set_io leds[2] 3 set_io leds[3] 4 -set_io leds[4] 7 -set_io leds[5] 8 -set_io leds[6] 9 -set_io leds[7] 10 +# real board buttons set_io buttons[0] 31 set_io buttons[1] 32 set_io buttons[2] 33 set_io buttons[3] 34 + +set_io leds[4] 7 +set_io leds[5] 8 +set_io leds[6] 9 +set_io leds[7] 10 + set_io buttons[4] 11 set_io buttons[5] 12 set_io buttons[6] 15 set_io buttons[7] 16 -set_io uart_rx 55 -set_io uart_tx 56 +# pmod0 +#set_io pmod0[0] 11 +#set_io pmod0[1] 12 +#set_io pmod0[2] 15 +#set_io pmod0[3] 16 +#set_io pmod0[4] 7 +#set_io pmod0[5] 8 +#set_io pmod0[6] 9 +#set_io pmod0[7] 10 + + +#pmod1 +set_io pmod1[0] 24 +set_io pmod1[1] 23 +set_io pmod1[2] 22 +set_io pmod1[3] 21 +set_io pmod1[4] 20 +set_io pmod1[5] 19 +set_io pmod1[6] 18 +set_io pmod1[7] 17 + + + +# arduino connector +set_io arduino1[0] 107 +set_io arduino1[1] 106 +set_io arduino1[2] 105 +set_io arduino1[3] 104 +set_io arduino1[4] 99 +set_io arduino1[5] 98 +set_io arduino1[6] 97 +set_io arduino1[7] 96 +set_io arduino1[8] 95 +set_io arduino1[9] 85 +set_io arduino1[10] 84 +set_io arduino1[11] 83 +set_io arduino1[12] 89 +set_io arduino1[13] 81 +set_io arduino1[14] 80 +set_io arduino1[15] 79 + + +set_io arduino0[0] 122 +set_io arduino0[1] 124 +set_io arduino0[2] 125 +set_io arduino0[3] 128 +set_io arduino0[4] 129 +set_io arduino0[5] 130 +set_io arduino0[6] 134 +set_io arduino0[7] 135 +set_io arduino0[8] 136 +set_io arduino0[9] 137 +set_io arduino0[10] 138 +set_io arduino0[11] 139 +set_io arduino0[12] 141 +set_io arduino0[13] 143 +set_io arduino0[14] 142 +set_io arduino0[15] 144 + + diff --git a/icicle.sv b/icicle.sv index dac20c7..87510aa 100644 --- a/icicle.sv +++ b/icicle.sv @@ -17,7 +17,7 @@ `define RESET_VECTOR 32'h00000000 `endif -module icicle ( +module icicle #( parameter LEDCOUNT, BUTTONCOUNT) ( input clk, input reset, @@ -36,10 +36,10 @@ module icicle ( `endif /* LEDs */ - output logic [7:0] leds, + output logic [LEDCOUNT -1 :0] leds, /* BUTTONS */ - input [7:0] buttons, + input [BUTTONCOUNT - 1:0] buttons, /* UART */ input uart_rx, @@ -184,7 +184,7 @@ module icicle ( logic [31:0] leds_read_value; logic leds_ready; - assign leds_read_value = {24'b0, leds_sel ? leds : 8'b0}; + assign leds_read_value = {32-LEDCOUNT'b0, leds_sel ? leds : LEDCOUNT'b0}; assign leds_ready = leds_sel; always_ff @(posedge clk) begin @@ -195,7 +195,7 @@ module icicle ( logic [31:0] buttons_read_value; logic buttons_ready; - assign buttons_read_value = {24'b0, buttons_sel ? buttons : 8'b0}; + assign buttons_read_value = {32-BUTTONCOUNT'b0, buttons_sel ? buttons : BUTTONCOUNT'b0}; assign buttons_ready = buttons_sel; logic [31:0] uart_read_value; diff --git a/top.sv b/top.sv index fa1e314..57dcacd 100644 --- a/top.sv +++ b/top.sv @@ -17,10 +17,10 @@ module top ( `endif /* LEDs */ - output logic [7:0] leds, + output logic [LEDCOUNT -1:0] leds, /* BUTTONS */ - input [7:0] buttons, + input [BUTTONCOUNT - 1:0] buttons, /* UART */ input uart_rx, @@ -35,6 +35,9 @@ module top ( .CLKHF(clk) ); `endif + parameter LEDCOUNT = 8; + parameter BUTTONCOUNT = 8; + `ifdef SPI_FLASH logic flash_io0_en; @@ -108,7 +111,7 @@ module top ( .out(pll_locked) ); - icicle icicle ( + icicle #( .LEDCOUNT(LEDCOUNT), .BUTTONCOUNT(BUTTONCOUNT)) icicle ( .clk(pll_clk), .reset(reset), From a55cd1b5b27088262c187f9ce5f366c193fa7448 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Wed, 15 Sep 2021 20:09:53 -0300 Subject: [PATCH 04/10] unhardcoded leds and buttons lengths --- boards/edufpga.pcf | 16 ++++++++-------- icicle.sv | 8 ++++---- top.sv | 9 ++++++--- 3 files changed, 18 insertions(+), 15 deletions(-) diff --git a/boards/edufpga.pcf b/boards/edufpga.pcf index 31cb9a3..6fb2c19 100644 --- a/boards/edufpga.pcf +++ b/boards/edufpga.pcf @@ -15,15 +15,15 @@ set_io buttons[1] 32 set_io buttons[2] 33 set_io buttons[3] 34 -set_io leds[4] 7 -set_io leds[5] 8 -set_io leds[6] 9 -set_io leds[7] 10 +#set_io leds[4] 7 +#set_io leds[5] 8 +#set_io leds[6] 9 +#set_io leds[7] 10 -set_io buttons[4] 11 -set_io buttons[5] 12 -set_io buttons[6] 15 -set_io buttons[7] 16 +#set_io buttons[4] 11 +#set_io buttons[5] 12 +#set_io buttons[6] 15 +#set_io buttons[7] 16 # pmod0 #set_io pmod0[0] 11 diff --git a/icicle.sv b/icicle.sv index 87510aa..f1547d6 100644 --- a/icicle.sv +++ b/icicle.sv @@ -17,7 +17,7 @@ `define RESET_VECTOR 32'h00000000 `endif -module icicle #( parameter LEDCOUNT, BUTTONCOUNT) ( +module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( input clk, input reset, @@ -184,18 +184,18 @@ module icicle #( parameter LEDCOUNT, BUTTONCOUNT) ( logic [31:0] leds_read_value; logic leds_ready; - assign leds_read_value = {32-LEDCOUNT'b0, leds_sel ? leds : LEDCOUNT'b0}; + assign leds_read_value = {(32-LEDCOUNT)'b0, leds_sel ? leds : LEDCOUNT'b0}; assign leds_ready = leds_sel; always_ff @(posedge clk) begin if (leds_sel && mem_write_mask[0]) - leds <= mem_write_value[7:0]; + leds <= mem_write_value[LEDCOUNT -1:0]; end logic [31:0] buttons_read_value; logic buttons_ready; - assign buttons_read_value = {32-BUTTONCOUNT'b0, buttons_sel ? buttons : BUTTONCOUNT'b0}; + assign buttons_read_value = {(32-BUTTONCOUNT)'b0, buttons_sel ? buttons : BUTTONCOUNT'b0}; assign buttons_ready = buttons_sel; logic [31:0] uart_read_value; diff --git a/top.sv b/top.sv index 57dcacd..203af2e 100644 --- a/top.sv +++ b/top.sv @@ -3,7 +3,11 @@ `include "pll.sv" `include "sync.sv" -module top ( +module top #( + parameter LEDCOUNT = 4, + parameter BUTTONCOUNT = 4 +) +( `ifndef INTERNAL_OSC input clk, `endif @@ -35,8 +39,7 @@ module top ( .CLKHF(clk) ); `endif - parameter LEDCOUNT = 8; - parameter BUTTONCOUNT = 8; + `ifdef SPI_FLASH From d589506fc772a7c014ff9889a8a9b5bc0835762e Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Wed, 15 Sep 2021 21:06:57 -0300 Subject: [PATCH 05/10] added pmod0 as output --- Makefile | 2 +- boards/edufpga.pcf | 142 ++++++++++++------------ icicle.sv | 37 ++++-- programs/buttons2ledsPmodCounter/main.c | 50 +++++++++ top.sv | 12 +- 5 files changed, 158 insertions(+), 85 deletions(-) create mode 100644 programs/buttons2ledsPmodCounter/main.c diff --git a/Makefile b/Makefile index e2e9ebf..b3d0c2a 100644 --- a/Makefile +++ b/Makefile @@ -16,7 +16,7 @@ SVF = $(TOP).svf TIME_RPT = $(TOP).rpt STAT = $(TOP).stat BOARD ?= ice40hx8k-b-evn -PROGRAM ?= buttons2leds +PROGRAM ?= buttons2ledsPmodCounter C_SRC = $(filter-out programs/uip/fsdata.c, $(wildcard programs/$(PROGRAM)/*.c)) OBJ = $(sort $(addsuffix .o, $(basename $(C_SRC))) start.o) TARGET ?= riscv64-unknown-elf diff --git a/boards/edufpga.pcf b/boards/edufpga.pcf index 6fb2c19..c4c22bf 100644 --- a/boards/edufpga.pcf +++ b/boards/edufpga.pcf @@ -1,87 +1,87 @@ -# -set_io clk 94 -set_io uart_rx 55 -set_io uart_tx 56 +# clock +set_io clk 94 #input + +# uart +set_io uart_rx 55 #input +set_io uart_tx 56 #output # real board leds -set_io leds[0] 1 -set_io leds[1] 2 -set_io leds[2] 3 -set_io leds[3] 4 +set_io leds[0] 1 #output +set_io leds[1] 2 #output +set_io leds[2] 3 #output +set_io leds[3] 4 #output # real board buttons -set_io buttons[0] 31 -set_io buttons[1] 32 -set_io buttons[2] 33 -set_io buttons[3] 34 +set_io buttons[0] 31 #input +set_io buttons[1] 32 #input +set_io buttons[2] 33 #input +set_io buttons[3] 34 #input -#set_io leds[4] 7 -#set_io leds[5] 8 -#set_io leds[6] 9 -#set_io leds[7] 10 +#set_io leds[4] 7 #output +#set_io leds[5] 8 #output +#set_io leds[6] 9 #output +#set_io leds[7] 10 #output -#set_io buttons[4] 11 -#set_io buttons[5] 12 -#set_io buttons[6] 15 -#set_io buttons[7] 16 +#set_io buttons[4] 11 #input +#set_io buttons[5] 12 #input +#set_io buttons[6] 15 #input +#set_io buttons[7] 16 #input -# pmod0 -#set_io pmod0[0] 11 -#set_io pmod0[1] 12 -#set_io pmod0[2] 15 -#set_io pmod0[3] 16 -#set_io pmod0[4] 7 -#set_io pmod0[5] 8 -#set_io pmod0[6] 9 -#set_io pmod0[7] 10 +# pmod0 (near arduino connector) +set_io pmod0[0] 11 #output +set_io pmod0[1] 12 #output +set_io pmod0[2] 15 #output +set_io pmod0[3] 16 #output +set_io pmod0[4] 7 #output +set_io pmod0[5] 8 #output +set_io pmod0[6] 9 #output +set_io pmod0[7] 10 #output #pmod1 -set_io pmod1[0] 24 -set_io pmod1[1] 23 -set_io pmod1[2] 22 -set_io pmod1[3] 21 -set_io pmod1[4] 20 -set_io pmod1[5] 19 -set_io pmod1[6] 18 -set_io pmod1[7] 17 +set_io pmod1[0] 24 #input +set_io pmod1[1] 23 #input +set_io pmod1[2] 22 #input +set_io pmod1[3] 21 #input +set_io pmod1[4] 20 #input +set_io pmod1[5] 19 #input +set_io pmod1[6] 18 #input +set_io pmod1[7] 17 #input # arduino connector -set_io arduino1[0] 107 -set_io arduino1[1] 106 -set_io arduino1[2] 105 -set_io arduino1[3] 104 -set_io arduino1[4] 99 -set_io arduino1[5] 98 -set_io arduino1[6] 97 -set_io arduino1[7] 96 -set_io arduino1[8] 95 -set_io arduino1[9] 85 -set_io arduino1[10] 84 -set_io arduino1[11] 83 -set_io arduino1[12] 89 -set_io arduino1[13] 81 -set_io arduino1[14] 80 -set_io arduino1[15] 79 - - -set_io arduino0[0] 122 -set_io arduino0[1] 124 -set_io arduino0[2] 125 -set_io arduino0[3] 128 -set_io arduino0[4] 129 -set_io arduino0[5] 130 -set_io arduino0[6] 134 -set_io arduino0[7] 135 -set_io arduino0[8] 136 -set_io arduino0[9] 137 -set_io arduino0[10] 138 -set_io arduino0[11] 139 -set_io arduino0[12] 141 -set_io arduino0[13] 143 -set_io arduino0[14] 142 -set_io arduino0[15] 144 +set_io arduino1[0] 107 #output +set_io arduino1[1] 106 #output +set_io arduino1[2] 105 #output +set_io arduino1[3] 104 #output +set_io arduino1[4] 99 #output +set_io arduino1[5] 98 #output +set_io arduino1[6] 97 #output +set_io arduino1[7] 96 #output +set_io arduino1[8] 95 #output +set_io arduino1[9] 85 #output +set_io arduino1[10] 84 #output +set_io arduino1[11] 83 #output +set_io arduino1[12] 89 #output +set_io arduino1[13] 81 #output +set_io arduino1[14] 80 #output +set_io arduino1[15] 79 #output +set_io arduino0[0] 122 #output +set_io arduino0[1] 124 #output +set_io arduino0[2] 125 #output +set_io arduino0[3] 128 #output +set_io arduino0[4] 129 #output +set_io arduino0[5] 130 #output +set_io arduino0[6] 134 #output +set_io arduino0[7] 135 #output +set_io arduino0[8] 136 #output +set_io arduino0[9] 137 #output +set_io arduino0[10] 138 #output +set_io arduino0[11] 139 #output +set_io arduino0[12] 141 #output +set_io arduino0[13] 143 #output +set_io arduino0[14] 142 #output +set_io arduino0[15] 144 #output diff --git a/icicle.sv b/icicle.sv index f1547d6..52972c8 100644 --- a/icicle.sv +++ b/icicle.sv @@ -41,6 +41,9 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( /* BUTTONS */ input [BUTTONCOUNT - 1:0] buttons, + /* PMOD0 */ + output logic [7:0] pmod0, + /* UART */ input uart_rx, output logic uart_tx @@ -72,8 +75,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic mem_ready; logic mem_fault; - assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | uart_read_value | timer_read_value | flash_read_value; - assign mem_ready = ram_ready | leds_ready | buttons_ready | uart_ready | timer_ready | flash_ready | mem_fault; + assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | pmod0_read_value | uart_read_value | timer_read_value | flash_read_value; + assign mem_ready = ram_ready | leds_ready | buttons_ready | pmod0_ready | uart_ready | timer_ready | flash_ready | mem_fault; bus_arbiter bus_arbiter ( .clk(clk), @@ -139,6 +142,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic ram_sel; logic leds_sel; logic buttons_sel; + logic pmod0_sel; logic uart_sel; logic timer_sel; logic flash_sel; @@ -146,20 +150,22 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( always_comb begin ram_sel = 0; leds_sel = 0; - buttons_sel = 0; + buttons_sel = 0; + pmod0_sel = 0; uart_sel = 0; timer_sel = 0; flash_sel = 0; mem_fault = 0; casez (mem_address) - 32'b00000000_00000000_????????_????????: ram_sel = 1; - 32'b00000000_00000001_00000000_000000??: leds_sel = 1; - 32'b00000000_00000001_00000000_000001??: buttons_sel = 1; - 32'b00000000_00000010_00000000_0000????: uart_sel = 1; - 32'b00000000_00000011_00000000_0000????: timer_sel = 1; - 32'b00000001_????????_????????_????????: flash_sel = 1; - default: mem_fault = 1; + 32'b00000000_00000000_????????_????????: ram_sel = 1; + 32'b00000000_00000001_00000000_000000??: leds_sel = 1; // 0x00010000 + 32'b00000000_00000001_00000000_000001??: buttons_sel = 1; // 0x00010004 + 32'b00000000_00000001_00000000_000010??: pmod0_sel = 1; // 0x00010008 + 32'b00000000_00000010_00000000_0000????: uart_sel = 1; // 0x00020000 + 32'b00000000_00000011_00000000_0000????: timer_sel = 1; // 0x00030000 + 32'b00000001_????????_????????_????????: flash_sel = 1; + default: mem_fault = 1; endcase end @@ -201,6 +207,17 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic [31:0] uart_read_value; logic uart_ready; + logic [31:0] pmod0_read_value; + logic pmod0_ready; + + assign pmod0_read_value = {24'b0, pmod0_sel ? leds : 8'b0}; + assign pmod0_ready = pmod0_sel; + + always_ff @(posedge clk) begin + if (pmod0_sel && mem_write_mask[0]) + pmod0 <= mem_write_value[7:0]; + end + uart uart ( .clk(clk), .reset(reset), diff --git a/programs/buttons2ledsPmodCounter/main.c b/programs/buttons2ledsPmodCounter/main.c new file mode 100644 index 0000000..b7a0a97 --- /dev/null +++ b/programs/buttons2ledsPmodCounter/main.c @@ -0,0 +1,50 @@ +#include + +// 32'b00000000_00000001_00000000_000000??: leds_sel = 1; +// 32'b00000000_00000001_00000000_000001??: buttons_sel = + +#define LEDS *((volatile uint32_t *) 0x00010000) +#define BUTTONS *((volatile uint32_t *) 0x00010004) +#define PMOD0 *((volatile uint32_t *) 0x00010008) +#define UART_BAUD *((volatile uint32_t *) 0x00020000) +#define UART_STATUS *((volatile uint32_t *) 0x00020004) +#define UART_DATA *((volatile int32_t *) 0x00020008) +#define MTIME *((volatile uint64_t *) 0x00030000) +#define MTIMECMP *((volatile uint64_t *) 0x00030008) + +#define UART_STATUS_TX_READY 0x1 +#define UART_STATUS_RX_READY 0x2 + +#define BAUD_RATE 9600 + +static void uart_putc(char c) { + while (!(UART_STATUS & UART_STATUS_TX_READY)); + UART_DATA = c; +} + +static void uart_puts(const char *str) { + char c; + while ((c = *str++)) { + uart_putc(c); + } +} + +static inline uint32_t rdcycle(void) { + uint32_t cycle; + asm volatile ("rdcycle %0" : "=r"(cycle)); + return cycle; +} + +int main() { + char counter = 0; + UART_BAUD = FREQ / BAUD_RATE; + PMOD0 = counter; + + for (;;) { + uart_puts("Press buttons, should turn on leds, while counter goes up in pmod0!\r\n"); + LEDS = ~BUTTONS; + PMOD0 = counter++; + uint32_t start = rdcycle(); + while ((rdcycle() - start) <= FREQ); + } +} diff --git a/top.sv b/top.sv index 203af2e..7af1d12 100644 --- a/top.sv +++ b/top.sv @@ -24,7 +24,10 @@ module top #( output logic [LEDCOUNT -1:0] leds, /* BUTTONS */ - input [BUTTONCOUNT - 1:0] buttons, + input [BUTTONCOUNT - 1:0] buttons, + + /* PMOD0 */ + output logic [7:0] pmod0, /* UART */ input uart_rx, @@ -135,8 +138,11 @@ module top #( /* LEDs */ .leds(leds), - /* BUTTONs */ - .buttons(buttons), + /* BUTTONs */ + .buttons(buttons), + + /* PMOD0 */ + .pmod0(pmod0), /* UART */ .uart_rx(uart_rx), From c4dfca2547e33654301699d324f684f23b51df0b Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Thu, 16 Sep 2021 15:15:03 -0300 Subject: [PATCH 06/10] defaulted board to edupfga --- Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index b3d0c2a..d88d73a 100644 --- a/Makefile +++ b/Makefile @@ -15,8 +15,8 @@ BIN = $(TOP).bin SVF = $(TOP).svf TIME_RPT = $(TOP).rpt STAT = $(TOP).stat -BOARD ?= ice40hx8k-b-evn -PROGRAM ?= buttons2ledsPmodCounter +BOARD ?= edufpga +PROGRAM ?= hello C_SRC = $(filter-out programs/uip/fsdata.c, $(wildcard programs/$(PROGRAM)/*.c)) OBJ = $(sort $(addsuffix .o, $(basename $(C_SRC))) start.o) TARGET ?= riscv64-unknown-elf From d5be4aee22249c7da9cf68fec6b2b13a91847e65 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Thu, 16 Sep 2021 15:17:14 -0300 Subject: [PATCH 07/10] added arduino as output --- boards/edufpga.pcf | 64 +++++++++---------- icicle.sv | 41 ++++++++++-- .../main.c | 59 +++++++++++++++++ top.sv | 7 ++ 4 files changed, 134 insertions(+), 37 deletions(-) create mode 100644 programs/buttons2ledsPmodCounterArduinoShift/main.c diff --git a/boards/edufpga.pcf b/boards/edufpga.pcf index c4c22bf..6eb0140 100644 --- a/boards/edufpga.pcf +++ b/boards/edufpga.pcf @@ -51,37 +51,37 @@ set_io pmod1[7] 17 #input # arduino connector -set_io arduino1[0] 107 #output -set_io arduino1[1] 106 #output -set_io arduino1[2] 105 #output -set_io arduino1[3] 104 #output -set_io arduino1[4] 99 #output -set_io arduino1[5] 98 #output -set_io arduino1[6] 97 #output -set_io arduino1[7] 96 #output -set_io arduino1[8] 95 #output -set_io arduino1[9] 85 #output -set_io arduino1[10] 84 #output -set_io arduino1[11] 83 #output -set_io arduino1[12] 89 #output -set_io arduino1[13] 81 #output -set_io arduino1[14] 80 #output -set_io arduino1[15] 79 #output +set_io arduino[0] 107 #output +set_io arduino[1] 106 #output +set_io arduino[2] 105 #output +set_io arduino[3] 104 #output +set_io arduino[4] 99 #output +set_io arduino[5] 98 #output +set_io arduino[6] 97 #output +set_io arduino[7] 96 #output +set_io arduino[8] 95 #output +set_io arduino[9] 85 #output +set_io arduino[10] 84 #output +set_io arduino[11] 83 #output +set_io arduino[12] 82 #output +set_io arduino[13] 81 #output +set_io arduino[14] 80 #output +set_io arduino[15] 79 #output -set_io arduino0[0] 122 #output -set_io arduino0[1] 124 #output -set_io arduino0[2] 125 #output -set_io arduino0[3] 128 #output -set_io arduino0[4] 129 #output -set_io arduino0[5] 130 #output -set_io arduino0[6] 134 #output -set_io arduino0[7] 135 #output -set_io arduino0[8] 136 #output -set_io arduino0[9] 137 #output -set_io arduino0[10] 138 #output -set_io arduino0[11] 139 #output -set_io arduino0[12] 141 #output -set_io arduino0[13] 143 #output -set_io arduino0[14] 142 #output -set_io arduino0[15] 144 #output +set_io arduino[16] 122 #output +set_io arduino[17] 124 #output +set_io arduino[18] 125 #output +set_io arduino[19] 128 #output +set_io arduino[20] 129 #output +set_io arduino[21] 130 #output +set_io arduino[22] 134 #output +set_io arduino[23] 135 #output +set_io arduino[24] 136 #output +set_io arduino[25] 137 #output +set_io arduino[26] 138 #output +set_io arduino[27] 139 #output +set_io arduino[28] 141 #output +set_io arduino[29] 143 #output +set_io arduino[30] 142 #output +set_io arduino[31] 144 #output diff --git a/icicle.sv b/icicle.sv index 52972c8..55fe1e4 100644 --- a/icicle.sv +++ b/icicle.sv @@ -44,6 +44,9 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( /* PMOD0 */ output logic [7:0] pmod0, + /* ARDUINO */ + output logic [31:0] arduino, + /* UART */ input uart_rx, output logic uart_tx @@ -75,8 +78,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic mem_ready; logic mem_fault; - assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | pmod0_read_value | uart_read_value | timer_read_value | flash_read_value; - assign mem_ready = ram_ready | leds_ready | buttons_ready | pmod0_ready | uart_ready | timer_ready | flash_ready | mem_fault; + assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | pmod0_read_value | arduino_read_value | uart_read_value | timer_read_value | flash_read_value; + assign mem_ready = ram_ready | leds_ready | buttons_ready | pmod0_ready | arduino_ready | uart_ready | timer_ready | flash_ready | mem_fault; bus_arbiter bus_arbiter ( .clk(clk), @@ -143,6 +146,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic leds_sel; logic buttons_sel; logic pmod0_sel; + logic arduino_sel; logic uart_sel; logic timer_sel; logic flash_sel; @@ -152,6 +156,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( leds_sel = 0; buttons_sel = 0; pmod0_sel = 0; + arduino_sel = 0; uart_sel = 0; timer_sel = 0; flash_sel = 0; @@ -162,6 +167,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( 32'b00000000_00000001_00000000_000000??: leds_sel = 1; // 0x00010000 32'b00000000_00000001_00000000_000001??: buttons_sel = 1; // 0x00010004 32'b00000000_00000001_00000000_000010??: pmod0_sel = 1; // 0x00010008 + 32'b00000000_00000001_00000000_000011??: arduino_sel = 1; // 0x0001000c 32'b00000000_00000010_00000000_0000????: uart_sel = 1; // 0x00020000 32'b00000000_00000011_00000000_0000????: timer_sel = 1; // 0x00030000 32'b00000001_????????_????????_????????: flash_sel = 1; @@ -187,6 +193,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( .ready_out(ram_ready) ); + /* LEDs */ logic [31:0] leds_read_value; logic leds_ready; @@ -198,14 +205,15 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( leds <= mem_write_value[LEDCOUNT -1:0]; end + /* BUTTONS */ + logic [31:0] buttons_read_value; logic buttons_ready; assign buttons_read_value = {(32-BUTTONCOUNT)'b0, buttons_sel ? buttons : BUTTONCOUNT'b0}; assign buttons_ready = buttons_sel; - - logic [31:0] uart_read_value; - logic uart_ready; + + /* PMOD0 */ logic [31:0] pmod0_read_value; logic pmod0_ready; @@ -218,6 +226,29 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( pmod0 <= mem_write_value[7:0]; end + /* ARDUINO */ + + logic [31:0] arduino_read_value; + logic arduino_ready; + + assign arduino_read_value = {arduino_sel ? leds : 32'b0}; + assign arduino_ready = arduino_sel; + + always_ff @(posedge clk) begin + if (arduino_sel && mem_write_mask[0]) + arduino[7:0] <= mem_write_value[7:0]; + if (arduino_sel && mem_write_mask[1]) + arduino[15:8] <= mem_write_value[15:8]; + if (arduino_sel && mem_write_mask[2]) + arduino[23:16] <= mem_write_value[23:16]; + if (arduino_sel && mem_write_mask[3]) + arduino[31:24] <= mem_write_value[31:24]; + end + + + logic [31:0] uart_read_value; + logic uart_ready; + uart uart ( .clk(clk), .reset(reset), diff --git a/programs/buttons2ledsPmodCounterArduinoShift/main.c b/programs/buttons2ledsPmodCounterArduinoShift/main.c new file mode 100644 index 0000000..3203f49 --- /dev/null +++ b/programs/buttons2ledsPmodCounterArduinoShift/main.c @@ -0,0 +1,59 @@ +#include + +// 32'b00000000_00000001_00000000_000000??: leds_sel = 1; +// 32'b00000000_00000001_00000000_000001??: buttons_sel = + +#define LEDS *((volatile uint32_t *) 0x00010000) +#define BUTTONS *((volatile uint32_t *) 0x00010004) +#define PMOD0 *((volatile uint32_t *) 0x00010008) +#define ARDUINO *((volatile uint32_t *) 0x0001000c) +#define UART_BAUD *((volatile uint32_t *) 0x00020000) +#define UART_STATUS *((volatile uint32_t *) 0x00020004) +#define UART_DATA *((volatile int32_t *) 0x00020008) +#define MTIME *((volatile uint64_t *) 0x00030000) +#define MTIMECMP *((volatile uint64_t *) 0x00030008) + +#define UART_STATUS_TX_READY 0x1 +#define UART_STATUS_RX_READY 0x2 + +#define BAUD_RATE 9600 + +static void uart_putc(char c) { + while (!(UART_STATUS & UART_STATUS_TX_READY)); + UART_DATA = c; +} + +static void uart_puts(const char *str) { + char c; + while ((c = *str++)) { + uart_putc(c); + } +} + +static inline uint32_t rdcycle(void) { + uint32_t cycle; + asm volatile ("rdcycle %0" : "=r"(cycle)); + return cycle; +} + +int main() { + char counter = 0; + unsigned int shift = 1; + UART_BAUD = FREQ / BAUD_RATE; + PMOD0 = counter; + + for (;;) { + uart_puts("Press buttons, should turn on leds, while counter goes up in pmod0 and the arduino connector shifts!\r\n"); + LEDS = ~BUTTONS; + PMOD0 = counter++; + + ARDUINO = shift; + shift = shift << 1; + if (shift == 0) { + shift = 1; + } + + uint32_t start = rdcycle(); + while ((rdcycle() - start) <= FREQ); + } +} diff --git a/top.sv b/top.sv index 7af1d12..2f698b9 100644 --- a/top.sv +++ b/top.sv @@ -29,6 +29,9 @@ module top #( /* PMOD0 */ output logic [7:0] pmod0, + /* ARDUINO */ + output logic [31:0] arduino, + /* UART */ input uart_rx, output logic uart_tx @@ -144,6 +147,10 @@ module top #( /* PMOD0 */ .pmod0(pmod0), + /* ARDUINO */ + .arduino(arduino), + + /* UART */ .uart_rx(uart_rx), .uart_tx(uart_tx) From 734d3564494616e57c138e95f6ce1d548564d7eb Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Thu, 16 Sep 2021 16:41:34 -0300 Subject: [PATCH 08/10] added pmod1 as input, fixed pmod0 and arduino reading from leds --- icicle.sv | 24 ++++++-- .../buttons2ledsArduinoShiftPmodToPmod/main.c | 56 +++++++++++++++++++ top.sv | 8 ++- 3 files changed, 82 insertions(+), 6 deletions(-) create mode 100644 programs/buttons2ledsArduinoShiftPmodToPmod/main.c diff --git a/icicle.sv b/icicle.sv index 55fe1e4..6ffa0ed 100644 --- a/icicle.sv +++ b/icicle.sv @@ -44,6 +44,9 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( /* PMOD0 */ output logic [7:0] pmod0, + /* PMOD1 */ + input [7:0] pmod1, + /* ARDUINO */ output logic [31:0] arduino, @@ -78,8 +81,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic mem_ready; logic mem_fault; - assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | pmod0_read_value | arduino_read_value | uart_read_value | timer_read_value | flash_read_value; - assign mem_ready = ram_ready | leds_ready | buttons_ready | pmod0_ready | arduino_ready | uart_ready | timer_ready | flash_ready | mem_fault; + assign mem_read_value = ram_read_value | leds_read_value | buttons_read_value | pmod0_read_value | pmod1_read_value | arduino_read_value | uart_read_value | timer_read_value | flash_read_value; + assign mem_ready = ram_ready | leds_ready | buttons_ready | pmod0_ready | pmod1_ready | arduino_ready | uart_ready | timer_ready | flash_ready | mem_fault; bus_arbiter bus_arbiter ( .clk(clk), @@ -146,6 +149,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic leds_sel; logic buttons_sel; logic pmod0_sel; + logic pmod1_sel; logic arduino_sel; logic uart_sel; logic timer_sel; @@ -156,6 +160,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( leds_sel = 0; buttons_sel = 0; pmod0_sel = 0; + pmod1_sel = 0; arduino_sel = 0; uart_sel = 0; timer_sel = 0; @@ -167,7 +172,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( 32'b00000000_00000001_00000000_000000??: leds_sel = 1; // 0x00010000 32'b00000000_00000001_00000000_000001??: buttons_sel = 1; // 0x00010004 32'b00000000_00000001_00000000_000010??: pmod0_sel = 1; // 0x00010008 - 32'b00000000_00000001_00000000_000011??: arduino_sel = 1; // 0x0001000c + 32'b00000000_00000001_00000000_000011??: pmod1_sel = 1; // 0x0001000c + 32'b00000000_00000001_00000000_000100??: arduino_sel = 1; // 0x00010010 32'b00000000_00000010_00000000_0000????: uart_sel = 1; // 0x00020000 32'b00000000_00000011_00000000_0000????: timer_sel = 1; // 0x00030000 32'b00000001_????????_????????_????????: flash_sel = 1; @@ -218,7 +224,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic [31:0] pmod0_read_value; logic pmod0_ready; - assign pmod0_read_value = {24'b0, pmod0_sel ? leds : 8'b0}; + assign pmod0_read_value = {24'b0, pmod0_sel ? pmod0 : 8'b0}; assign pmod0_ready = pmod0_sel; always_ff @(posedge clk) begin @@ -226,12 +232,20 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( pmod0 <= mem_write_value[7:0]; end + /* PMOD1 */ + + logic [31:0] pmod1_read_value; + logic pmod1_ready; + + assign pmod1_read_value = {24'b0, pmod1_sel ? pmod1 : 8'b0}; + assign pmod1_ready = pmod1_sel; + /* ARDUINO */ logic [31:0] arduino_read_value; logic arduino_ready; - assign arduino_read_value = {arduino_sel ? leds : 32'b0}; + assign arduino_read_value = {arduino_sel ? arduino : 32'b0}; assign arduino_ready = arduino_sel; always_ff @(posedge clk) begin diff --git a/programs/buttons2ledsArduinoShiftPmodToPmod/main.c b/programs/buttons2ledsArduinoShiftPmodToPmod/main.c new file mode 100644 index 0000000..36a14eb --- /dev/null +++ b/programs/buttons2ledsArduinoShiftPmodToPmod/main.c @@ -0,0 +1,56 @@ +#include + + +#define LEDS *((volatile uint32_t *) 0x00010000) +#define BUTTONS *((volatile uint32_t *) 0x00010004) +#define PMOD0 *((volatile uint32_t *) 0x00010008) +#define PMOD1 *((volatile uint32_t *) 0x0001000c) +#define ARDUINO *((volatile uint32_t *) 0x00010010) +#define UART_BAUD *((volatile uint32_t *) 0x00020000) +#define UART_STATUS *((volatile uint32_t *) 0x00020004) +#define UART_DATA *((volatile int32_t *) 0x00020008) +#define MTIME *((volatile uint64_t *) 0x00030000) +#define MTIMECMP *((volatile uint64_t *) 0x00030008) + +#define UART_STATUS_TX_READY 0x1 +#define UART_STATUS_RX_READY 0x2 + +#define BAUD_RATE 9600 + +static void uart_putc(char c) { + while (!(UART_STATUS & UART_STATUS_TX_READY)); + UART_DATA = c; +} + +static void uart_puts(const char *str) { + char c; + while ((c = *str++)) { + uart_putc(c); + } +} + +static inline uint32_t rdcycle(void) { + uint32_t cycle; + asm volatile ("rdcycle %0" : "=r"(cycle)); + return cycle; +} + +int main() { + unsigned int shift = 1; + UART_BAUD = FREQ / BAUD_RATE; + + for (;;) { + uart_puts("Press buttons, should turn on leds, while the arduino connector shifts and pmod0 mimics pmod1!\r\n"); + LEDS = ~BUTTONS; + PMOD0 = PMOD1; + + ARDUINO = shift; + shift = shift << 1; + if (shift == 0) { + shift = 1; + } + + uint32_t start = rdcycle(); + while ((rdcycle() - start) <= FREQ); + } +} diff --git a/top.sv b/top.sv index 2f698b9..a5cf8bf 100644 --- a/top.sv +++ b/top.sv @@ -29,6 +29,10 @@ module top #( /* PMOD0 */ output logic [7:0] pmod0, + /* PMOD1 */ + input [7:0] pmod1, + + /* ARDUINO */ output logic [31:0] arduino, @@ -147,10 +151,12 @@ module top #( /* PMOD0 */ .pmod0(pmod0), + /* PMOD1 */ + .pmod1(pmod1), + /* ARDUINO */ .arduino(arduino), - /* UART */ .uart_rx(uart_rx), .uart_tx(uart_tx) From 0fdc5723b196bad41ab6432138acf78603033367 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Sat, 18 Sep 2021 10:06:56 -0300 Subject: [PATCH 09/10] conditional devices inclusion, removed useless example, better shifting program example --- boards/edufpga-defines.sv | 3 + icicle.sv | 21 +++++++ .../buttons2ledsArduinoShiftPmodToPmod/main.c | 6 +- .../main.c | 59 ------------------- top.sv | 13 +++- 5 files changed, 39 insertions(+), 63 deletions(-) delete mode 100644 programs/buttons2ledsPmodCounterArduinoShift/main.c diff --git a/boards/edufpga-defines.sv b/boards/edufpga-defines.sv index b09fa72..45482fd 100644 --- a/boards/edufpga-defines.sv +++ b/boards/edufpga-defines.sv @@ -1 +1,4 @@ // Defines for EDU-FPGA +`define PMOD0 +`define PMOD1 +`define ARDUINO diff --git a/icicle.sv b/icicle.sv index 6ffa0ed..9ce7609 100644 --- a/icicle.sv +++ b/icicle.sv @@ -224,6 +224,7 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( logic [31:0] pmod0_read_value; logic pmod0_ready; +`ifdef PMOD0 assign pmod0_read_value = {24'b0, pmod0_sel ? pmod0 : 8'b0}; assign pmod0_ready = pmod0_sel; @@ -231,20 +232,30 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( if (pmod0_sel && mem_write_mask[0]) pmod0 <= mem_write_value[7:0]; end +`else + assign pmod0_read_value = 0; + assign pmod0_ready = pmod0_sel; +`endif /* PMOD1 */ logic [31:0] pmod1_read_value; logic pmod1_ready; +`ifdef PMOD1 assign pmod1_read_value = {24'b0, pmod1_sel ? pmod1 : 8'b0}; assign pmod1_ready = pmod1_sel; +`else + assign pmod1_read_value = 0; + assign pmod1_ready = pmod1_sel; +`endif /* ARDUINO */ logic [31:0] arduino_read_value; logic arduino_ready; +`ifdef ARDUINO assign arduino_read_value = {arduino_sel ? arduino : 32'b0}; assign arduino_ready = arduino_sel; @@ -259,6 +270,12 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( arduino[31:24] <= mem_write_value[31:24]; end +`else + assign arduino_read_value = 0; + assign arduino_ready = arduino_sel; +`endif + + /* UART */ logic [31:0] uart_read_value; logic uart_ready; @@ -281,6 +298,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( .ready_out(uart_ready) ); + /* TIMER */ + logic [31:0] timer_read_value; logic timer_ready; @@ -301,6 +320,8 @@ module icicle #( parameter LEDCOUNT, parameter BUTTONCOUNT) ( .ready_out(timer_ready) ); + /* FLASH */ + logic [31:0] flash_read_value; logic flash_ready; diff --git a/programs/buttons2ledsArduinoShiftPmodToPmod/main.c b/programs/buttons2ledsArduinoShiftPmodToPmod/main.c index 36a14eb..efb04a8 100644 --- a/programs/buttons2ledsArduinoShiftPmodToPmod/main.c +++ b/programs/buttons2ledsArduinoShiftPmodToPmod/main.c @@ -36,7 +36,7 @@ static inline uint32_t rdcycle(void) { } int main() { - unsigned int shift = 1; + unsigned int shift = 0x01010101; UART_BAUD = FREQ / BAUD_RATE; for (;;) { @@ -46,8 +46,8 @@ int main() { ARDUINO = shift; shift = shift << 1; - if (shift == 0) { - shift = 1; + if (shift == 0x01010100) { + shift |= 1; } uint32_t start = rdcycle(); diff --git a/programs/buttons2ledsPmodCounterArduinoShift/main.c b/programs/buttons2ledsPmodCounterArduinoShift/main.c deleted file mode 100644 index 3203f49..0000000 --- a/programs/buttons2ledsPmodCounterArduinoShift/main.c +++ /dev/null @@ -1,59 +0,0 @@ -#include - -// 32'b00000000_00000001_00000000_000000??: leds_sel = 1; -// 32'b00000000_00000001_00000000_000001??: buttons_sel = - -#define LEDS *((volatile uint32_t *) 0x00010000) -#define BUTTONS *((volatile uint32_t *) 0x00010004) -#define PMOD0 *((volatile uint32_t *) 0x00010008) -#define ARDUINO *((volatile uint32_t *) 0x0001000c) -#define UART_BAUD *((volatile uint32_t *) 0x00020000) -#define UART_STATUS *((volatile uint32_t *) 0x00020004) -#define UART_DATA *((volatile int32_t *) 0x00020008) -#define MTIME *((volatile uint64_t *) 0x00030000) -#define MTIMECMP *((volatile uint64_t *) 0x00030008) - -#define UART_STATUS_TX_READY 0x1 -#define UART_STATUS_RX_READY 0x2 - -#define BAUD_RATE 9600 - -static void uart_putc(char c) { - while (!(UART_STATUS & UART_STATUS_TX_READY)); - UART_DATA = c; -} - -static void uart_puts(const char *str) { - char c; - while ((c = *str++)) { - uart_putc(c); - } -} - -static inline uint32_t rdcycle(void) { - uint32_t cycle; - asm volatile ("rdcycle %0" : "=r"(cycle)); - return cycle; -} - -int main() { - char counter = 0; - unsigned int shift = 1; - UART_BAUD = FREQ / BAUD_RATE; - PMOD0 = counter; - - for (;;) { - uart_puts("Press buttons, should turn on leds, while counter goes up in pmod0 and the arduino connector shifts!\r\n"); - LEDS = ~BUTTONS; - PMOD0 = counter++; - - ARDUINO = shift; - shift = shift << 1; - if (shift == 0) { - shift = 1; - } - - uint32_t start = rdcycle(); - while ((rdcycle() - start) <= FREQ); - } -} diff --git a/top.sv b/top.sv index a5cf8bf..8e51d56 100644 --- a/top.sv +++ b/top.sv @@ -27,14 +27,19 @@ module top #( input [BUTTONCOUNT - 1:0] buttons, /* PMOD0 */ +`ifdef PMOD0 output logic [7:0] pmod0, +`endif /* PMOD1 */ +`ifdef PMOD1 input [7:0] pmod1, - +`endif /* ARDUINO */ +`ifdef ARDUINO output logic [31:0] arduino, +`endif /* UART */ input uart_rx, @@ -149,13 +154,19 @@ module top #( .buttons(buttons), /* PMOD0 */ +`ifdef PMOD0 .pmod0(pmod0), +`endif /* PMOD1 */ +`ifdef PMOD1 .pmod1(pmod1), +`endif /* ARDUINO */ +`ifdef ARDUINO .arduino(arduino), +`endif /* UART */ .uart_rx(uart_rx), From f04a5c84e019aebcc465295bf0728ac9d2b6e041 Mon Sep 17 00:00:00 2001 From: Carlos Pantelides Date: Sat, 18 Sep 2021 17:01:46 -0300 Subject: [PATCH 10/10] restored original readme.md --- README.md | 312 +++++++++++++++++++------------------- README_grahamedgecombe.md | 174 --------------------- 2 files changed, 157 insertions(+), 329 deletions(-) delete mode 100644 README_grahamedgecombe.md diff --git a/README.md b/README.md index 90c75b5..8a7c3f2 100644 --- a/README.md +++ b/README.md @@ -1,172 +1,174 @@ -# XXXX en icicle en EDU-FPGA +# Icicle +## Introduction +Icicle is a 32-bit [RISC-V][riscv] system on chip for [iCE40 HX8K][ice40], +[iCE40 UP5K][ice40-up5k] and [ECP5][ecp5] FPGAs. It can be built with the +open-source [SymbiFlow][symbiflow] toolchain and currently targets several +development boards. -Instrucciones específicas para [EDU-FPGA](http://www.proyecto-ciaa.com.ar/devwiki/doku.php?id=desarrollo%3Aedu-fpga): +## Current features -## Instalación nativa de las herramientas +* RV32I core with a [classic 5-stage RISC pipeline][classic-risc], static branch + prediction, bypassing and interlocking. It currently implements the entire + [user ISA][riscv-user] parts of the [privileged ISA][riscv-priv]. +* Shared instruction and data memory (8 KiB, implemented with FPGA block RAM). +* Memory-mapped UART and LEDs. +* Memory-mapped SPI flash. -Estos pasos fueron probados con `Linux Mint 21 Mate` en un sistema de 64-bits `x86_64`. +## Dependencies -### Prerrequisitos +* [GNU Make][make] +* [GNU RISC-V toolchain][riscv-gnu] +* [Icarus Verilog][iverilog] (`master` branch) +* [nextpnr][nextpnr] or [arachne-pnr][arachne-pnr] +* [Project IceStorm][icestorm] or [Project Trellis][trellis] +* [vim][vim] (for `xxd`) +* [Yosys][yosys] (`master` branch) -- Crear un directorio de trabajo y posicionarse en él. -``` -mkdir -p ~/workspace/ -cd ~/workspace/ -``` +## Building and testing -- Instalar dependencias disponibles en el repositorio. +### Supported boards -``` -sudo apt update -sudo apt install gperf build-essential cmake python3-dev texinfo vim libboost-all-dev tcl-dev libreadline-dev libffi-dev libeigen3-dev +Icicle supports several development boards: -``` +* `blackice-ii`: [BlackIce II][blackice-ii-board] +* `ecp5-evn`: [ECP5 evaluation board][ecp5-evn] +* `edufpga`: [EDU-CIAA-FPGA iCE40-HX4k board](./EDU-FPGA.md) +* `ice40hx8k-b-evn`: [iCE40-HX8K breakout board][ice40-hx8k-breakout] +* `icebreaker`: [iCEBreaker][icebreaker] +* `upduino`: [UPduino][upduino] -### Toolchain RISC-V +`` should be replaced with the internal name of your development board in +the rest of the instructions (e.g. `ice40hx8k-b-evn` for the iCE40-HX8K breakout +board). -Clonar y construir el toolchain para `RV32I`. La instalación necesita privilegios de root. +### Building -**NOTA**: Este repositorio es grande (~7GB). Clonarlo y luego construirlo lleva tiempo, ¡paciencia! +* Run `make BOARD= syntax` to check the syntax with [Icarus][iverilog], + which has a stricter parser than [Yosys][yosys]. At the time of writing the + `master` branch of Icarus is required as there isn't a stable release with + `always_comb`/`always_ff` support yet. +* Run `make BOARD=` to synthesize the design, place and route, compile + the demo program in `progmem.c` and create the bitstream. -``` -cd ~/workspace/ -git clone --recursive https://github.com/riscv/riscv-gnu-toolchain -cd riscv-gnu-toolchain +### Programming -./configure -sudo make # compila e instala -``` - -### Icarus Verilog - -La instalación necesita privilegios de root. - -``` -cd ~/workspace/ -git clone git://github.com/steveicarus/iverilog.git -cd iverilog -sh autoconf.sh -./configure -make -sudo make install -``` - -### IceStorm - -La instalación necesita privilegios de root. - -``` -cd ~/workspace/ -git clone https://github.com/YosysHQ/icestorm.git icestorm -cd icestorm -make -j$(nproc) -sudo make install -``` - -### NextPNR - -La instalación necesita privilegios de root. - -``` -cd ~/workspace/ -git clone https://github.com/YosysHQ/nextpnr nextpnr --recursive -cd nextpnr -cmake -DARCH=ice40 -DCMAKE_INSTALL_PREFIX=/usr/local . -make -j$(nproc) -sudo make install -``` - -### Yosys - -La instalación necesita privilegios de root. - -``` -cd ~/workspace/ -git clone https://github.com/YosysHQ/yosys.git yosys -cd yosys -make config-gcc -make -j$(nproc) -sudo make install -``` - -## Permisos - -Para que `iceprog` pueda acceder a la placa, puede hacer falta: - -``` -echo 'ACTION=="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE:="666"' |\ -sudo tee -a /etc/udev/rules.d/70-lattice.rules 1>/dev/null -sudo service udev restart -``` -## Conexión en Virtual Box - -No te olvides de conectar a la virtual: - -Devices -> USB -> FTDI Dual RS232-HS[0700] - -## Generación del bitstream - - -- Clonar repositorio, construir y grabar memoria SPI de la EDU-FPGA: -``` -cd ~/workspace/ -git clone https://github.com/cpantel/XXX.git -cd XXX -make BOARD=edufpga -# antes de ejecutar el siguiente comando, conectar la EDU-FPGA a la PC -make BOARD=edufpga flash -``` - -Así se ve la salida típica de estos comandos: - -``` -$ make BOARD=edufpga -riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=36000000 -Os -ffreestanding -nostartfiles -g -Iprograms/hello -c -o programs/hello/main.o programs/hello/main.c -riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=36000000 -Os -ffreestanding -nostartfiles -g -Iprograms/hello -Wl,-Tprogmem.lds -o progmem programs/hello/main.o start.o -riscv64-unknown-elf-objcopy -O binary progmem progmem.bin -xxd -p -c 4 < progmem.bin > progmem.hex -yosys -q ice40.ys -arachne-pnr -q -d 8k -P tq144:4k -o top_syn.asc -p boards/edufpga.pcf top.blif -icebram progmem_syn.hex progmem.hex < top_syn.asc > top.asc -icepack top.asc top.bin -``` -``` -$ make BOARD=edufpga flash -icetime -t -m -d hx8k -P tq144:4k -p boards/edufpga.pcf -c 36 -r top.rpt top_syn.asc -// Reading input .pcf file.. -// Reading input .asc file.. -// Reading 8k chipdb file.. -// Creating timing netlist.. -// Timing estimate: 27.43 ns (36.45 MHz) -// Checking 27.78 ns (36.00 MHz) clock constraint: PASSED. -iceprog top.bin -init.. -cdone: high -reset.. -cdone: low -flash ID: 0xEF 0x30 0x13 0x00 -file size: 135100 -erase 64kB sector at 0x000000.. -erase 64kB sector at 0x010000.. -erase 64kB sector at 0x020000.. -programming.. -reading.. -VERIFY OK -cdone: high -Bye. -``` - -¡Listo! Deberías ver destellar los LEDs de la EDU-FPGA y por la UART (`/dev/ttyUSB1`) deberías observar el mensaje `Hello, world!`. - -``` -$ cat /dev/ttyUSB1 -Hello, world! - -Hello, world! - -Hello, world! -``` +#### BlackIce II +* Configure jumper on board for [DFU Mode][dfu-mode] and connect both USB1 and + USB2 on the board to host USB ports. +* Run `make BOARD=blackice-ii dfu-flash` to flash the bitstream. +#### ECP5 evaluation board + +* Remove R22, R23 and R24 to disconnect the channel B of the FTDI chip from the + I2C bus. +* Populate R34 and R35 with zero-ohm resistors to connect channel B of the FTDI + chip to the UART RX and TX pins. +* Optionally populate R21 with a zero-ohm resistor to enable the UART TX + indicator LED. + +#### EDU-FPGA + +* Run `make BOARD=edufpga flash` to flash the bitstream. + +#### iCE40-HX8K breakout board + +* Configure the jumpers for flash programming. +* Run `make BOARD=ice40hx8k-b-evn flash` to flash the bitstream. + +### Testing + +* If your chosen board has built-in LEDs, some of the LEDs should turn on and blink. +* Run `picocom -b 9600 /dev/ttyUSBn` (replacing `ttyUSBn` with the name of the + serial port) to connect to the serial port. `Hello, world!` should be printed + once per second. + +### Other targets + +The `make BOARD= stat` target runs `icebox_stat` and the +`make BOARD= time` target prints the `icetime` report. + +The `Makefile` runs the [IceStorm][icestorm] toolchain in quiet mode. Unset the +`QUIET` variable to run the toolchain in verbose mode - e.g. +`make BOARD= QUIET= ...`. + +Set the `PNR` variable to `arachne-pnr` to use [arachne-pnr][arachne-pnr] +instead of [nextpnr][nextpnr] (the default) - e.g. `make PNR=arachne-pnr`. + +## Formal verification + +Icicle supports the RISC-V Formal Interface (RVFI), allowing it to be formally +verified with [SymbiYosys][symbiyosys] and [riscv-formal][riscv-formal]: + +* Run `git clone https://github.com/SymbioticEDA/riscv-formal` to clone + riscv-formal. +* Run `cd riscv-formal/cores && git clone https://github.com/grahamedgecombe/icicle` + to clone Icicle in the `cores` subdirectory. +* Run ``cd icicle && python ../../checks/genchecks.py && make -C checks -j `nproc``` + to verify the core. + +## Planned features + +* Use remaining block RAM tiles to eke out as much memory as possible. +* Use the SPRAM tiles on UP5K devices. +* Implement remaining bits of the user ISA. +* Implement machine mode from the privileged ISA. +* Interrupts/exceptions. +* Unaligned memory access support. +* Memory-mapped GPIOs. +* Add XIP, DDR, DSPI and QSPI support to the SPI flash controller. +* Improved reset support (a reset signal + boot ROM to zero all the registers). +* Automated tests. +* Multiply/divide support. +* Compressed instruction support. +* Add flags to disable certain features (e.g. privileged mode) to save LUTs on + smaller devices (e.g. the UP5K). +* Investigate using DSP tiles on the UP5K. + +## Size and performance + +The entire system on chip currently occupies around 3,000 LUTs on an iCE40 when +synthesized with [Yosys][yosys]. + +If bypassing and branch prediction are disabled [nextpnr][nextpnr] estimates it +can be clocked at around 50 MHz on a HX series device and 20 MHz on a UP series +device. + +The core is capable of issuing and retiring one instruction per clock cycle, +although the actual number of instructions per cycle will be slightly less than +this in practice due to interlocking, branch mispredictions and the shared +memory bus. + +## License + +This project is available under the terms of the ISC license, which is similar +to the 2-clause BSD license. See the `LICENSE` file for the copyright +information and licensing terms. + +[arachne-pnr]: https://github.com/cseed/arachne-pnr#readme +[blackice-ii-board]: https://github.com/mystorm-org/BlackIce-II#readme +[classic-risc]: https://en.wikipedia.org/wiki/Classic_RISC_pipeline +[dfu-mode]: https://github.com/mystorm-org/BlackIce-II/wiki/DFU-operations-on-the-BlackIce-II +[ecp5-evn]: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard.aspx +[ecp5]: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx +[ice40-hx8k-breakout]: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx +[ice40-up5k]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx +[ice40]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx +[icebreaker]: https://github.com/icebreaker-fpga/ +[icestorm]: http://www.clifford.at/icestorm/ +[iverilog]: http://iverilog.icarus.com/ +[make]: https://www.gnu.org/software/make/ +[nextpnr]: https://github.com/YosysHQ/nextpnr#readme +[riscv-formal]: https://github.com/SymbioticEDA/riscv-formal +[riscv-gnu]: https://github.com/riscv/riscv-gnu-toolchain#readme +[riscv-priv]: https://riscv.org/specifications/privileged-isa/ +[riscv-user]: https://riscv.org/specifications/ +[riscv]: https://riscv.org/risc-v-isa/ +[symbiflow]: https://symbiflow.github.io/ +[symbiyosys]: https://symbiyosys.readthedocs.io/ +[trellis]: https://github.com/SymbiFlow/prjtrellis#readme +[upduino]: http://gnarlygrey.atspace.cc/development-platform.html#upduino +[vim]: https://www.vim.org/ +[yosys]: http://www.clifford.at/yosys/ diff --git a/README_grahamedgecombe.md b/README_grahamedgecombe.md deleted file mode 100644 index 8a7c3f2..0000000 --- a/README_grahamedgecombe.md +++ /dev/null @@ -1,174 +0,0 @@ -# Icicle - -## Introduction - -Icicle is a 32-bit [RISC-V][riscv] system on chip for [iCE40 HX8K][ice40], -[iCE40 UP5K][ice40-up5k] and [ECP5][ecp5] FPGAs. It can be built with the -open-source [SymbiFlow][symbiflow] toolchain and currently targets several -development boards. - -## Current features - -* RV32I core with a [classic 5-stage RISC pipeline][classic-risc], static branch - prediction, bypassing and interlocking. It currently implements the entire - [user ISA][riscv-user] parts of the [privileged ISA][riscv-priv]. -* Shared instruction and data memory (8 KiB, implemented with FPGA block RAM). -* Memory-mapped UART and LEDs. -* Memory-mapped SPI flash. - -## Dependencies - -* [GNU Make][make] -* [GNU RISC-V toolchain][riscv-gnu] -* [Icarus Verilog][iverilog] (`master` branch) -* [nextpnr][nextpnr] or [arachne-pnr][arachne-pnr] -* [Project IceStorm][icestorm] or [Project Trellis][trellis] -* [vim][vim] (for `xxd`) -* [Yosys][yosys] (`master` branch) - -## Building and testing - -### Supported boards - -Icicle supports several development boards: - -* `blackice-ii`: [BlackIce II][blackice-ii-board] -* `ecp5-evn`: [ECP5 evaluation board][ecp5-evn] -* `edufpga`: [EDU-CIAA-FPGA iCE40-HX4k board](./EDU-FPGA.md) -* `ice40hx8k-b-evn`: [iCE40-HX8K breakout board][ice40-hx8k-breakout] -* `icebreaker`: [iCEBreaker][icebreaker] -* `upduino`: [UPduino][upduino] - -`` should be replaced with the internal name of your development board in -the rest of the instructions (e.g. `ice40hx8k-b-evn` for the iCE40-HX8K breakout -board). - -### Building - -* Run `make BOARD= syntax` to check the syntax with [Icarus][iverilog], - which has a stricter parser than [Yosys][yosys]. At the time of writing the - `master` branch of Icarus is required as there isn't a stable release with - `always_comb`/`always_ff` support yet. -* Run `make BOARD=` to synthesize the design, place and route, compile - the demo program in `progmem.c` and create the bitstream. - -### Programming - -#### BlackIce II - -* Configure jumper on board for [DFU Mode][dfu-mode] and connect both USB1 and - USB2 on the board to host USB ports. -* Run `make BOARD=blackice-ii dfu-flash` to flash the bitstream. - -#### ECP5 evaluation board - -* Remove R22, R23 and R24 to disconnect the channel B of the FTDI chip from the - I2C bus. -* Populate R34 and R35 with zero-ohm resistors to connect channel B of the FTDI - chip to the UART RX and TX pins. -* Optionally populate R21 with a zero-ohm resistor to enable the UART TX - indicator LED. - -#### EDU-FPGA - -* Run `make BOARD=edufpga flash` to flash the bitstream. - -#### iCE40-HX8K breakout board - -* Configure the jumpers for flash programming. -* Run `make BOARD=ice40hx8k-b-evn flash` to flash the bitstream. - -### Testing - -* If your chosen board has built-in LEDs, some of the LEDs should turn on and blink. -* Run `picocom -b 9600 /dev/ttyUSBn` (replacing `ttyUSBn` with the name of the - serial port) to connect to the serial port. `Hello, world!` should be printed - once per second. - -### Other targets - -The `make BOARD= stat` target runs `icebox_stat` and the -`make BOARD= time` target prints the `icetime` report. - -The `Makefile` runs the [IceStorm][icestorm] toolchain in quiet mode. Unset the -`QUIET` variable to run the toolchain in verbose mode - e.g. -`make BOARD= QUIET= ...`. - -Set the `PNR` variable to `arachne-pnr` to use [arachne-pnr][arachne-pnr] -instead of [nextpnr][nextpnr] (the default) - e.g. `make PNR=arachne-pnr`. - -## Formal verification - -Icicle supports the RISC-V Formal Interface (RVFI), allowing it to be formally -verified with [SymbiYosys][symbiyosys] and [riscv-formal][riscv-formal]: - -* Run `git clone https://github.com/SymbioticEDA/riscv-formal` to clone - riscv-formal. -* Run `cd riscv-formal/cores && git clone https://github.com/grahamedgecombe/icicle` - to clone Icicle in the `cores` subdirectory. -* Run ``cd icicle && python ../../checks/genchecks.py && make -C checks -j `nproc``` - to verify the core. - -## Planned features - -* Use remaining block RAM tiles to eke out as much memory as possible. -* Use the SPRAM tiles on UP5K devices. -* Implement remaining bits of the user ISA. -* Implement machine mode from the privileged ISA. -* Interrupts/exceptions. -* Unaligned memory access support. -* Memory-mapped GPIOs. -* Add XIP, DDR, DSPI and QSPI support to the SPI flash controller. -* Improved reset support (a reset signal + boot ROM to zero all the registers). -* Automated tests. -* Multiply/divide support. -* Compressed instruction support. -* Add flags to disable certain features (e.g. privileged mode) to save LUTs on - smaller devices (e.g. the UP5K). -* Investigate using DSP tiles on the UP5K. - -## Size and performance - -The entire system on chip currently occupies around 3,000 LUTs on an iCE40 when -synthesized with [Yosys][yosys]. - -If bypassing and branch prediction are disabled [nextpnr][nextpnr] estimates it -can be clocked at around 50 MHz on a HX series device and 20 MHz on a UP series -device. - -The core is capable of issuing and retiring one instruction per clock cycle, -although the actual number of instructions per cycle will be slightly less than -this in practice due to interlocking, branch mispredictions and the shared -memory bus. - -## License - -This project is available under the terms of the ISC license, which is similar -to the 2-clause BSD license. See the `LICENSE` file for the copyright -information and licensing terms. - -[arachne-pnr]: https://github.com/cseed/arachne-pnr#readme -[blackice-ii-board]: https://github.com/mystorm-org/BlackIce-II#readme -[classic-risc]: https://en.wikipedia.org/wiki/Classic_RISC_pipeline -[dfu-mode]: https://github.com/mystorm-org/BlackIce-II/wiki/DFU-operations-on-the-BlackIce-II -[ecp5-evn]: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard.aspx -[ecp5]: https://www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx -[ice40-hx8k-breakout]: https://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx -[ice40-up5k]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40Ultra.aspx -[ice40]: https://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx -[icebreaker]: https://github.com/icebreaker-fpga/ -[icestorm]: http://www.clifford.at/icestorm/ -[iverilog]: http://iverilog.icarus.com/ -[make]: https://www.gnu.org/software/make/ -[nextpnr]: https://github.com/YosysHQ/nextpnr#readme -[riscv-formal]: https://github.com/SymbioticEDA/riscv-formal -[riscv-gnu]: https://github.com/riscv/riscv-gnu-toolchain#readme -[riscv-priv]: https://riscv.org/specifications/privileged-isa/ -[riscv-user]: https://riscv.org/specifications/ -[riscv]: https://riscv.org/risc-v-isa/ -[symbiflow]: https://symbiflow.github.io/ -[symbiyosys]: https://symbiyosys.readthedocs.io/ -[trellis]: https://github.com/SymbiFlow/prjtrellis#readme -[upduino]: http://gnarlygrey.atspace.cc/development-platform.html#upduino -[vim]: https://www.vim.org/ -[yosys]: http://www.clifford.at/yosys/