fix format of doc in backend

Author: paulzfm

src/main/scala/decaf/backend/asm/AsmEmitter.scala

@@ -22,7 +22,7 @@ abstract class AsmEmitter(val platformName: String, val allocatableRegs: Array[R
 
   /**
     * Instruction selection for a TAC function.
-    * <p>
+    *
     * Since no register allocation is done, the generated instructions may still contain pseudo registers (temps).
     *
     * @param func TAC function

src/main/scala/decaf/backend/asm/mips/MipsAsmEmitter.scala

@@ -15,7 +15,7 @@ import scala.collection.mutable
   */
 final class MipsAsmEmitter extends AsmEmitter("mips", Mips.allocatableRegs, Mips.callerSaved) {
 
-  override def emitVTable(vtbl: VTable): Unit = { // vtable begin
+  override def emitVTable(vtbl: VTable): Unit = {
     printer.println(".data")
     printer.println(".align 2")
     printer.printLabel(vtbl.label, "virtual table for " + vtbl.className)
@@ -32,7 +32,6 @@ final class MipsAsmEmitter extends AsmEmitter("mips", Mips.allocatableRegs, Mips
       printer.println(".word %s    # member method", entry.name)
     }
     printer.println()
-    // vtable end
   }
 
   override def selectInstr(func: TacFunc): (List[PseudoInstr], SubroutineInfo) = {
@@ -49,13 +48,13 @@ final class MipsAsmEmitter extends AsmEmitter("mips", Mips.allocatableRegs, Mips
   override def emitSubroutine(info: SubroutineInfo) = new MipsSubroutineEmitter(this, info)
 
   override def emitEnd(): String = {
-    if (!usedIntrinsics.isEmpty) {
+    if (usedIntrinsics.nonEmpty) {
       printer.println("# start of intrinsics")
       if (usedIntrinsics.contains(Intrinsic.READ_LINE.entry)) loadReadLine()
       if (usedIntrinsics.contains(Intrinsic.STRING_EQUAL.entry)) loadStringEqual()
       if (usedIntrinsics.contains(Intrinsic.PRINT_BOOL.entry)) loadPrintBool()
       printer.println("# end of intrinsics")
-      printer.println
+      printer.println()
     }
     printer.println("# start of constant strings")
     printer.println(".data")

src/main/scala/decaf/backend/dataflow/LivenessAnalyzer.scala

@@ -4,6 +4,11 @@ import decaf.lowlevel.instr.{PseudoInstr, Temp}
 
 import scala.collection.mutable
 
+/**
+  * Perform liveness analysis.
+  *
+  * @tparam I type of instructions
+  */
 class LivenessAnalyzer[I <: PseudoInstr] extends Function[CFG[I], Unit] {
 
   override def apply(graph: CFG[I]): Unit = {
@@ -37,17 +42,18 @@ class LivenessAnalyzer[I <: PseudoInstr] extends Function[CFG[I], Unit] {
   }
 
   /**
-    * Compute the {@code def} and {@code liveUse} set for basic block {@code bb}.
-    * <p>
+    * Compute the `def and `liveUse` set for basic block `bb`.
+    *
     * Recall the definition:
-    * - {@code def}: set of all variables (i.e. temps) that are assigned to a value. Thus, we simply union all the
+    *
+    *    - `def`: set of all variables (i.e. temps) that are assigned to a value. Thus, we simply union all the
     * written temps of every instruction.
-    * - {@code liveUse}: set of all variables (i.e. temps) that are used before they are assigned to a value in this
+    *    - `liveUse`: set of all variables (i.e. temps) that are used before they are assigned to a value in this
     * basic block. Note this is NOT simply equal to the union set all read temps, but only those are not yet
     * assigned/reassigned.
     *
     * @param bb basic block
-    */
+    **/
   private def computeDefAndLiveUseFor(bb: BasicBlock[I]): Unit = {
     bb.`def` = new mutable.TreeSet[Temp]
     bb.liveUse = new mutable.TreeSet[Temp]
@@ -65,12 +71,13 @@ class LivenessAnalyzer[I <: PseudoInstr] extends Function[CFG[I], Unit] {
   /**
     * Perform liveness analysis for every single location in a basic block, so that we know at each program location,
     * which variables stay alive.
-    * <p>
+    *
     * Idea: realizing that every location loc can be regarded as a "mini" basic block -- a block containing that
     * instruction solely, then the data flow equations also hold, and the situation becomes much simpler:
-    * - loc.liveOut = loc.next.liveIn
-    * - loc.def is simply the set of written temps
-    * - loc.liveUse is simply the set of read temps, since it is impossible to read and write a same temp
+    *
+    *     - `loc.liveOut = loc.next.liveIn`
+    *     - `loc.def` is simply the set of written temps
+    *     - `loc.liveUse` is simply the set of read temps, since it is impossible to read and write a same temp
     * simultaneously
     * So you see, to back propagate every location solves the problem.
     *

src/main/scala/decaf/backend/reg/BruteRegAlloc.scala

@@ -9,7 +9,6 @@ import scala.util.Random
 
 /**
   * Brute force greedy register allocation algorithm.
-  * <p>
   * To make our life easier, don't consider any special registers that may be used during call.
   */
 final class BruteRegAlloc(emitter: AsmEmitter) extends RegAlloc(emitter) {
@@ -32,6 +31,7 @@ final class BruteRegAlloc(emitter: AsmEmitter) extends RegAlloc(emitter) {
     val used = new mutable.TreeSet[Reg]
   }
 
+  /** Bind a temp with a register. */
   private def bind(temp: Temp, reg: Reg)(implicit ctx: Context): Unit = {
     ctx.used += reg
     ctx.occupied += reg
@@ -40,6 +40,7 @@ final class BruteRegAlloc(emitter: AsmEmitter) extends RegAlloc(emitter) {
     ctx.tempOf(reg) = temp
   }
 
+  /** Unbind a temp with its register. */
   private def unbind(temp: Temp)(implicit ctx: Context): Unit = {
     if (ctx.regOf.contains(temp)) {
       ctx.occupied.remove(ctx.regOf(temp))
@@ -49,24 +50,21 @@ final class BruteRegAlloc(emitter: AsmEmitter) extends RegAlloc(emitter) {
 
   /**
     * Main algorithm of local register allocation à la brute-force. Basic idea:
-    * <ul>
-    * <li>Allocation is preformed block-by-block.</li>
-    * <li>Assume that every allocatable register is unoccupied before entering every basic block.</li>
-    * <li>For every read (src) and written (dst) temp {@code t} in every pseudo instruction, attempt the following
-    * in order:</li>
-    * <li><ol>
-    * <li>{@code t} is already bound to a register: keep on using it.</li>
-    * <li>If there exists an available (unoccupied, or the occupied temp is no longer alive) register,
-    * then bind to it.</li>
-    * <li>Arbitrarily pick a general register, spill its value to stack, and then bind to it.</li>
-    * </ol></li>
-    * </ul>
-    * <p>
-    * The output assembly code is maintained by {@code emitter}.
+    *
+    *   - Allocation is preformed block-by-block.
+    *   - Assume that every allocatable register is unoccupied before entering every basic block.
+    *   - For every read (src) and written (dst) temp `t` in every pseudo instruction, attempt the following in order:
+    *
+    *       1. `t` is already bound to a register: keep on using it.
+    *       1. If there exists an available (unoccupied, or the occupied temp is no longer alive) register,
+    * then bind to it.
+    *       1. Arbitrarily pick a general register, spill its value to stack, and then bind to it.</li>
+    *
+    * The output assembly code is maintained by `ctx.emitter`.
     *
     * @param bb  the basic block which the algorithm performs on
     * @param ctx context
-    * @see #allocRegFor
+    * @see [[allocRegFor]]
     */
   private def localAlloc(bb: BasicBlock[PseudoInstr])(implicit ctx: Context): Unit = {
     ctx.regOf.clear()