How to widen the render area in schematic?

[CacahueteNC]

I've been using Wavedrom for a while in my docs and I stumbled upon a case where I thought that a logic diagram would convey more meaning than a written expression. And I was correct and was able to render the function in no time.

The problem was that my signal names are not single letters and they overflow the rendering area. I thought that it was just a render issue and exported the PNG but it was the same.

Here is the sample in the browser and here is the PNG result:

{ assign:[
  ["Out Signal",
    ["|",
      ["&", ["~", "First Input"], "Good signal"],
      ["&", ["~", "Second Input"], "Great signal"]
    ]
  ]
]}

I wanted to export it as SVG and have it scale correctly in Microsoft Visio, but the later does not seem to be happy with it, here's what I see :

Is there a way to enlarge the rendering area, something like config: { hscale: 2 }?

Thanks a lot for your time!

[drom]

related to #30

[drom]

It should be done automatically. I have the facility to measure test block with for specific font/size. But will require a bit more thinking.