diff --git a/cmake/Agent.cmake b/cmake/Agent.cmake index 75c33f3e43cd6..1dee951aa63bb 100644 --- a/cmake/Agent.cmake +++ b/cmake/Agent.cmake @@ -162,6 +162,7 @@ target_link_libraries(utils meru800bia_platform_mapping meru800bfa_platform_mapping janga800bic_platform_mapping + j4sim_platform_mapping icecube800banw_platform_mapping icecube800bc_platform_mapping icetea800bc_platform_mapping diff --git a/cmake/AgentPlatformsCommon.cmake b/cmake/AgentPlatformsCommon.cmake index d3e3c50a0d246..b14f66a83208a 100644 --- a/cmake/AgentPlatformsCommon.cmake +++ b/cmake/AgentPlatformsCommon.cmake @@ -56,6 +56,7 @@ target_link_libraries(platform_mapping_utils ladakh800bcls_platform_mapping minipack3bta_platform_mapping icecube800banw_platform_mapping + j4sim_platform_mapping platform_mode ${RE2} ) diff --git a/cmake/AgentPlatformsCommonJ4Sim.cmake b/cmake/AgentPlatformsCommonJ4Sim.cmake new file mode 100644 index 0000000000000..4c8932655e804 --- /dev/null +++ b/cmake/AgentPlatformsCommonJ4Sim.cmake @@ -0,0 +1,12 @@ +# CMake to build libraries and binaries in fboss/agent/platforms/common/j4sim + +# In general, libraries and binaries in fboss/foo/bar are built by +# cmake/FooBar.cmake + +add_library(j4sim_platform_mapping + fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +) + +target_link_libraries(j4sim_platform_mapping + platform_mapping +) diff --git a/cmake/AgentPlatformsSai.cmake b/cmake/AgentPlatformsSai.cmake index 2d6424595ea0c..3190d2b68cde3 100644 --- a/cmake/AgentPlatformsSai.cmake +++ b/cmake/AgentPlatformsSai.cmake @@ -58,6 +58,8 @@ set(SAI_PLATFORM_SRC fboss/agent/platforms/sai/SaiYangraPlatformPort.cpp fboss/agent/platforms/sai/SaiMinipack3NPlatformPort.cpp # platform oss srcs (== fake_srcs) + fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp + fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp fboss/agent/platforms/sai/oss/SaiBcmMinipackPlatform.cpp fboss/agent/platforms/sai/oss/SaiBcmPlatform.cpp fboss/agent/platforms/sai/oss/SaiBcmMinipackPlatformPort.cpp @@ -131,6 +133,7 @@ target_link_libraries(sai_platform icecube800banw_platform_mapping icecube800bc_platform_mapping icetea800bc_platform_mapping + j4sim_platform_mapping led_structs_types_cpp2 led_mapping_cpp2 wedge800bact_platform_mapping diff --git a/fboss/agent/ApplyThriftConfig.cpp b/fboss/agent/ApplyThriftConfig.cpp index ec0ed70bb3e31..5dee92226a6df 100644 --- a/fboss/agent/ApplyThriftConfig.cpp +++ b/fboss/agent/ApplyThriftConfig.cpp @@ -1175,6 +1175,7 @@ void ThriftConfigApplier::processUpdatedDsfNodes() { asicCore = 1; break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: if (isDualStage3Q2QMode()) { asicCore = 447; } else { diff --git a/fboss/agent/AsicUtils.cpp b/fboss/agent/AsicUtils.cpp index 31261bdabcd90..ea4594c8dfbc8 100644 --- a/fboss/agent/AsicUtils.cpp +++ b/fboss/agent/AsicUtils.cpp @@ -10,6 +10,7 @@ #include "fboss/agent/AsicUtils.h" #include "fboss/agent/hw/switch_asics/Jericho2Asic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/hw/switch_asics/Ramon3Asic.h" #include "fboss/agent/hw/switch_asics/RamonAsic.h" @@ -39,6 +40,11 @@ const HwAsic& getHwAsicForAsicType(const cfg::AsicType& asicType) { static Jericho3Asic jericho3Asic{switchId, switchInfo}; return jericho3Asic; } + case cfg::AsicType::ASIC_TYPE_JERICHO4: { + switchInfo.switchType() = cfg::SwitchType::VOQ; + static Jericho4Asic jericho4Asic{switchId, switchInfo}; + return jericho4Asic; + } case cfg::AsicType::ASIC_TYPE_RAMON: { switchInfo.switchType() = cfg::SwitchType::FABRIC; static RamonAsic ramonAsic{switchId, switchInfo}; @@ -82,6 +88,8 @@ uint32_t getFabricPortsPerVirtualDevice(const cfg::AsicType asicType) { return 192; case cfg::AsicType::ASIC_TYPE_JERICHO3: return 160; + case cfg::AsicType::ASIC_TYPE_JERICHO4: + return 160; case cfg::AsicType::ASIC_TYPE_RAMON3: return 256; case cfg::AsicType::ASIC_TYPE_FAKE: diff --git a/fboss/agent/hw/bcm/BcmPlatform.cpp b/fboss/agent/hw/bcm/BcmPlatform.cpp index bb6be42a59d29..ee3efd20db383 100644 --- a/fboss/agent/hw/bcm/BcmPlatform.cpp +++ b/fboss/agent/hw/bcm/BcmPlatform.cpp @@ -114,6 +114,7 @@ phy::VCOFrequency BcmPlatform::getVCOFrequency( case cfg::PortSpeed::GIGE: [[fallthrough]]; case cfg::PortSpeed::EIGHTHUNDREDG: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: case cfg::PortSpeed::DEFAULT: return phy::VCOFrequency::UNKNOWN; diff --git a/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp b/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp index 3629cf64fd3db..40be498126700 100644 --- a/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp +++ b/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp @@ -141,6 +141,7 @@ void triggerParityError(HwSwitchEnsemble* ensemble) { triggerBcmJericho2ParityError(ensemble); break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: triggerBcmJericho3ParityError(ensemble); break; case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp b/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp index 357d8f02d4806..6c41183f7cd18 100644 --- a/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp +++ b/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp @@ -236,6 +236,7 @@ void HwTestThriftHandler::triggerParityError() { triggerBcmJericho2ParityError(hwSwitch_); break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: triggerBcmJericho3ParityError(hwSwitch_); break; case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp b/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp index 30ceb503f6f29..ac3fa7d9a9e45 100644 --- a/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp @@ -1682,8 +1682,9 @@ std::set SaiAclTableManager::getSupportedQualifierSet( platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_TRIDENT2; bool isJericho2 = platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO2; - bool isJericho3 = - platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3; + bool isJericho3 = platform_->getAsic()->getAsicType() == + cfg::AsicType::ASIC_TYPE_JERICHO3 || + platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4; bool isTomahawk5 = platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_TOMAHAWK5; bool isChenab = diff --git a/fboss/agent/hw/sai/switch/SaiBufferManager.cpp b/fboss/agent/hw/sai/switch/SaiBufferManager.cpp index 31742f7d3af7a..8f9a359d0394c 100644 --- a/fboss/agent/hw/sai/switch/SaiBufferManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiBufferManager.cpp @@ -109,6 +109,7 @@ void assertMaxBufferPoolSize(const SaiPlatform* platform) { break; case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_TRIDENT2: CHECK_EQ(maxEgressPoolSize, availableBuffer); break; @@ -201,6 +202,7 @@ uint64_t SaiBufferManager::getMaxEgressPoolBytes(const SaiPlatform* platform) { } case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: /* * XXX: TODO: Need to check if there is a way to compute the * buffers available for use in Jericho2 without using the diff --git a/fboss/agent/hw/sai/switch/SaiPortManager.cpp b/fboss/agent/hw/sai/switch/SaiPortManager.cpp index 30897e2a51805..ccf1d3eecb26e 100644 --- a/fboss/agent/hw/sai/switch/SaiPortManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiPortManager.cpp @@ -611,6 +611,7 @@ int getWorstCaseAssumedOpticsDelayNS( case cfg::AsicType::ASIC_TYPE_G202X: break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: if (portType == cfg::PortType::FABRIC_PORT) { return 110; } else { diff --git a/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp b/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp index 93d52d0ad656c..86dfa0a7b14bc 100644 --- a/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp @@ -110,6 +110,7 @@ SaiVirtualRouterManager::createMplsRouterInterface(VirtualRouterSaiId vrId) { case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp b/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp index 8c081fe283c39..d8e9d746e2391 100644 --- a/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp +++ b/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp @@ -253,8 +253,9 @@ std::shared_ptr ManagerTestBase::makePort( swPort->setProfileId(cfg::PortProfileID::PROFILE_DEFAULT); break; case cfg::PortSpeed::GIGE: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: - throw FbossError("profile gig and 3.2T ethernet is not available"); + throw FbossError("profile gig, 1.6T and 3.2T ethernet is not available"); case cfg::PortSpeed::XG: swPort->setProfileId(cfg::PortProfileID::PROFILE_10G_1_NRZ_NOFEC_OPTICAL); break; diff --git a/fboss/agent/hw/switch_asics/HwAsic.cpp b/fboss/agent/hw/switch_asics/HwAsic.cpp index 676391b85d34d..5ba57db8c1f8b 100644 --- a/fboss/agent/hw/switch_asics/HwAsic.cpp +++ b/fboss/agent/hw/switch_asics/HwAsic.cpp @@ -18,6 +18,7 @@ #include "fboss/agent/hw/switch_asics/G202xAsic.h" #include "fboss/agent/hw/switch_asics/Jericho2Asic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/hw/switch_asics/MockAsic.h" #include "fboss/agent/hw/switch_asics/Ramon3Asic.h" #include "fboss/agent/hw/switch_asics/RamonAsic.h" @@ -120,6 +121,8 @@ std::unique_ptr HwAsic::makeAsic( return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_JERICHO3: return std::make_unique(switchId, switchInfo, sdkVersion); + case cfg::AsicType::ASIC_TYPE_JERICHO4: + return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_RAMON: return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_RAMON3: diff --git a/fboss/agent/hw/switch_asics/Jericho3Asic.cpp b/fboss/agent/hw/switch_asics/Jericho3Asic.cpp index 51600870bdaf4..a826ae851d1f8 100644 --- a/fboss/agent/hw/switch_asics/Jericho3Asic.cpp +++ b/fboss/agent/hw/switch_asics/Jericho3Asic.cpp @@ -74,7 +74,6 @@ bool Jericho3Asic::isSupported(Feature feature) const { case HwAsic::Feature::WARMBOOT: case HwAsic::Feature::PQP_ERROR_EGRESS_DROP_COUNTER: case HwAsic::Feature::FABRIC_LINK_DOWN_CELL_DROP_COUNTER: - case HwAsic::Feature::SAI_FEC_CODEWORDS_STATS: case HwAsic::Feature::CRC_ERROR_DETECT: case HwAsic::Feature::ACL_METADATA_QUALIFER: case HwAsic::Feature::EVENTOR_PORT_FOR_SFLOW: @@ -250,6 +249,12 @@ bool Jericho3Asic::isSupported(Feature feature) const { case HwAsic::Feature::VIRTUAL_ARS_GROUP: case HwAsic::Feature::ECN_PROBABILISTIC_MARKING: case HwAsic::Feature::SWITCH_DROP_DEBUG_COUNTER: + // Disabling some counters for the time being. + // This will result in an early return in + // SaiDebugCounterManager::setupTrapDropCounter(), which is currently + // failing with SAI 14.x + case HwAsic::Feature::ANY_TRAP_DROP_COUNTER: + case HwAsic::Feature::SAI_FEC_CODEWORDS_STATS: return false; } return false; diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h new file mode 100644 index 0000000000000..d4b4e477e5c05 --- /dev/null +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -0,0 +1,39 @@ +// Copyright 2004-present Facebook. All Rights Reserved. + +#pragma once + +#include +#include "fboss/agent/hw/switch_asics/Jericho3Asic.h" + +namespace facebook::fboss { + +class Jericho4Asic : public Jericho3Asic { + public: + Jericho4Asic( + std::optional switchId, + cfg::SwitchInfo switchInfo, + std::optional sdkVersion = std::nullopt) + : Jericho3Asic(switchId, switchInfo, sdkVersion) {} + + cfg::AsicType getAsicType() const override { + return cfg::AsicType::ASIC_TYPE_JERICHO4; + } + + cfg::PortSpeed getMaxPortSpeed() const override { + return cfg::PortSpeed::ONEPOINTSIXT; + } + + bool isSupported(Feature feature) const override { + // TBD if necessary + if (feature == HwAsic::Feature::SWITCH_ISOLATE) { + return false; + } + return Jericho3Asic::isSupported(feature); + + // Jericho4 cModel bringup is using Jericho4L (99410) which only has 4 cores + uint32_t getNumCores() const override { + return 4; + } +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp b/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp index bc48f906f5c64..0a4247b41bc84 100644 --- a/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp +++ b/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp @@ -57,6 +57,7 @@ std::unique_ptr> getFullHashedPackets( case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_G202X: @@ -88,6 +89,7 @@ std::unique_ptr> getFullHashedPackets( case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_G202X: diff --git a/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp b/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp index efc3ee16d28c7..75eb1fef91893 100644 --- a/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp +++ b/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp @@ -174,6 +174,7 @@ void HwProdInvariantHelper::verifySafeDiagCmds() { case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/agent/platforms/common/BUCK b/fboss/agent/platforms/common/BUCK index f276e13891feb..041ab6aef37fd 100644 --- a/fboss/agent/platforms/common/BUCK +++ b/fboss/agent/platforms/common/BUCK @@ -34,6 +34,7 @@ cpp_library( exported_deps = [ ":platform_mapping", "//fboss/agent:fboss-error", + "//fboss/agent/platforms/common/j4sim:j4sim_platform_mapping", "//fboss/agent/platforms/common/darwin:darwin_platform_mapping", "//fboss/agent/platforms/common/elbert:elbert_platform_mapping", "//fboss/agent/platforms/common/fake_test:fake_test_platform_mapping", diff --git a/fboss/agent/platforms/common/PlatformMappingUtils.cpp b/fboss/agent/platforms/common/PlatformMappingUtils.cpp index a8eade0a1ef65..7b396bf14ec70 100644 --- a/fboss/agent/platforms/common/PlatformMappingUtils.cpp +++ b/fboss/agent/platforms/common/PlatformMappingUtils.cpp @@ -23,6 +23,7 @@ #include "fboss/agent/platforms/common/icecube800banw/Icecube800banwPlatformMapping.h" #include "fboss/agent/platforms/common/icecube800bc/Icecube800bcPlatformMapping.h" #include "fboss/agent/platforms/common/icetea800bc/Icetea800bcPlatformMapping.h" +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" #include "fboss/agent/platforms/common/janga800bic/Janga800bicPlatformMapping.h" #include "fboss/agent/platforms/common/ladakh800bcls/Ladakh800bclsPlatformMapping.h" #include "fboss/agent/platforms/common/meru400bfu/Meru400bfuPlatformMapping.h" @@ -219,6 +220,10 @@ std::unique_ptr initPlatformMapping(PlatformType type) { return platformMappingStr.empty() ? std::make_unique() : std::make_unique(platformMappingStr); + case PlatformType::PLATFORM_J4SIM: + return platformMappingStr.empty() + ? std::make_unique() + : std::make_unique(platformMappingStr); case PlatformType::PLATFORM_FAKE_SAI: { std::vector controllingPorts = getFakeSaiControllingPortIDs(); return std::make_unique(controllingPorts); diff --git a/fboss/agent/platforms/common/j4sim/BUCK b/fboss/agent/platforms/common/j4sim/BUCK new file mode 100644 index 0000000000000..9882f6cca57a6 --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/BUCK @@ -0,0 +1,16 @@ +load("@fbcode_macros//build_defs:cpp_library.bzl", "cpp_library") + +oncall("fboss_agent_push") + +cpp_library( + name = "j4sim_platform_mapping", + srcs = [ + "J4SimPlatformMapping.cpp", + ], + headers = [ + "J4SimPlatformMapping.h", + ], + exported_deps = [ + "//fboss/agent/platforms/common:platform_mapping", + ], +) diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp new file mode 100644 index 0000000000000..5dd4210e3dfdb --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -0,0 +1,5532 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ + +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" + +namespace facebook::fboss { +namespace { +constexpr auto kJsonPlatformMappingStr = R"( +{ + "ports": { + "1": { + "mapping": { + "id": 1, + "name": "eth1/1/1", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + }, + { + "id": { + "chip": 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"NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + }, + "39": { + "subsumedPorts": [ + 58, + 59, + 60, + 61, + 62, + 63, + 64 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + } + ] + } + } + } + }, + "58": { + "mapping": { + "id": 58, + "name": "eth1/8/2", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + } + ] + } + } + } + }, + "59": { + "mapping": { + "id": 59, + "name": "eth1/8/3", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + } + ] + } + } + } + }, + "60": { + "mapping": { + "id": 60, + "name": "eth1/8/4", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + } + ] + } + } + } + }, + "61": { + "mapping": { + "id": 61, + "name": "eth1/8/5", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + } + ] + } + } + } + }, + "62": { + "mapping": { + "id": 62, + "name": "eth1/8/6", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + ] + } + } + } + }, + "63": { + "mapping": { + "id": 63, + "name": "eth1/8/7", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + ] + } + } + } + }, + "64": { + "mapping": { + "id": 64, + "name": "eth1/8/8", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + } + } + } + }, + "chips": [ + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core0", + "type": 1, + "physicalID": 0 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core1", + "type": 1, + "physicalID": 1 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core2", + "type": 1, + "physicalID": 2 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core3", + "type": 1, + "physicalID": 3 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core4", + "type": 1, + "physicalID": 4 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core5", + "type": 1, + "physicalID": 5 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core6", + "type": 1, + "physicalID": 6 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core7", + "type": 1, + "physicalID": 7 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip1", + "type": 3, + "physicalID": 0 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip2", + "type": 3, + "physicalID": 1 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip3", + "type": 3, + "physicalID": 2 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip4", + "type": 3, + "physicalID": 3 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip5", + "type": 3, + "physicalID": 4 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip6", + "type": 3, + "physicalID": 5 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip7", + "type": 3, + "physicalID": 6 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip8", + "type": 3, + "physicalID": 7 + } + ], + "platformSupportedProfiles": [ + { + "factor": { + "profileID": 49 + }, + "profile": { + "speed": 100000, + "iphy": { + "numLanes": 1, + "modulation": 2, + "fec": 1, + "medium": 1, + "interfaceType": 10 + } + } + }, + { + "factor": { + "profileID": 50 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 1, + "interfaceType": 13 + } + } + }, + { + "factor": { + "profileID": 39 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 23 + } + } + } + ] +} +)"; +} // namespace + +J4SimPlatformMapping::J4SimPlatformMapping() + : PlatformMapping(kJsonPlatformMappingStr) {} + +J4SimPlatformMapping::J4SimPlatformMapping( + const std::string& platformMappingStr) + : PlatformMapping(platformMappingStr) {} + +std::map> +J4SimPlatformMapping::getCpuPortsCoreAndPortIdx() const { + static const std::map> + kSingleStageCpuPortsCoreAndPortIdx = { + // {CPU System Port, {Core ID, Port ID/PP_DSP}} + {0, {0, 0}}, + {1, {1, 200}}, + {2, {2, 202}}, + {3, {3, 203}}, + }; + return kSingleStageCpuPortsCoreAndPortIdx; +} + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h new file mode 100644 index 0000000000000..628c540cdfef4 --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/common/PlatformMapping.h" + +namespace facebook::fboss { + +class J4SimPlatformMapping : public PlatformMapping { + public: + J4SimPlatformMapping(); + explicit J4SimPlatformMapping(const std::string& platformMappingStr); + // For CPU system port number as key, get the core for CPU port and + // the port ID within the core. + std::map> getCpuPortsCoreAndPortIdx() + const override; + + private: + // Forbidden copy constructor and assignment operator + J4SimPlatformMapping(J4SimPlatformMapping const&) = delete; + J4SimPlatformMapping& operator=(J4SimPlatformMapping const&) = delete; +}; +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp new file mode 100644 index 0000000000000..be70889d35754 --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ + +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h" + +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" + +namespace { +constexpr auto kCpuPortSpeed = 10000; +constexpr auto kSingleStageCpuPortNumVoqs = 8; +constexpr auto kDualStageCpuPortNumVoqs = 3; +} // namespace + +namespace facebook::fboss { + +SaiBcmJ4SimPlatform::SaiBcmJ4SimPlatform( + std::unique_ptr productInfo, + folly::MacAddress localMac, + const std::string& platformMappingStr) + : SaiBcmPlatform( + std::move(productInfo), + platformMappingStr.empty() + ? std::make_unique() + : std::make_unique(platformMappingStr), + localMac) {} + +void SaiBcmJ4SimPlatform::setupAsic( + std::optional switchId, + const cfg::SwitchInfo& switchInfo, + std::optional fabricNodeRole) { + CHECK(!fabricNodeRole.has_value()); + asic_ = std::make_unique(switchId, switchInfo); +} + +HwAsic* SaiBcmJ4SimPlatform::getAsic() const { + return asic_.get(); +} + +std::vector +SaiBcmJ4SimPlatform::getInternalSystemPortConfig() const { + CHECK(asic_) << " Asic must be set before getting sys port info"; + CHECK(asic_->getSwitchId()) << " Switch Id must be set before sys port info"; + + const uint32_t switchId = static_cast(*asic_->getSwitchId()); + const uint32_t speed = kCpuPortSpeed; + const uint32_t numVoqs = isDualStage3Q2QMode() ? kDualStageCpuPortNumVoqs + : kSingleStageCpuPortNumVoqs; + auto cpuPortsCoreAndPortIdx = + getPlatformMapping()->getCpuPortsCoreAndPortIdx(); + + CHECK( + cpuPortsCoreAndPortIdx.size() == 1 || + cpuPortsCoreAndPortIdx.size() == 4 || cpuPortsCoreAndPortIdx.size() == 8) + << "Create one CPU port for the ASIC or one CPU port for each core"; + + std::vector sysPortConfig; + for (auto [cpuPortID, coreAndPortIdx] : cpuPortsCoreAndPortIdx) { + auto [core, port] = coreAndPortIdx; + sysPortConfig.push_back({cpuPortID, switchId, core, port, speed, numVoqs}); + } + return sysPortConfig; +} +SaiBcmJ4SimPlatform::~SaiBcmJ4SimPlatform() = default; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h new file mode 100644 index 0000000000000..aa1c11d956c6b --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/sai/SaiBcmPlatform.h" + +namespace facebook::fboss { + +class Jericho4Asic; + +class SaiBcmJ4SimPlatform : public SaiBcmPlatform { + public: + SaiBcmJ4SimPlatform( + std::unique_ptr productInfo, + folly::MacAddress localMac, + const std::string& platformMappingStr); + ~SaiBcmJ4SimPlatform() override; + HwAsic* getAsic() const override; + + uint32_t numLanesPerCore() const override { + return 8; + } + + uint32_t numCellsAvailable() const override { + return 130665; + } + + bool isSerdesApiSupported() const override { + return true; + } + + void initLEDs() override {} + + std::vector getAllPortsInGroup(PortID /*portID*/) const override { + return {}; + } + + std::vector getSupportedFlexPortModes() const override { + return {}; + } + + bool supportInterfaceType() const override { + return true; + } + + std::optional getInterfaceType( + TransmitterTechnology /*transmitterTech*/, + cfg::PortSpeed /*speed*/) const override { + return std::nullopt; + } + std::vector getInternalSystemPortConfig() + const override; + + private: + void setupAsic( + std::optional switchId, + const cfg::SwitchInfo& switchInfo, + std::optional fabricNodeRole) override; + + std::unique_ptr asic_; +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp new file mode 100644 index 0000000000000..e9ad9bde82d6c --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h" + +namespace facebook::fboss { + +void SaiBcmJ4SimPlatformPort::linkStatusChanged( + bool /* up */, + bool /* adminUp */) {} + +void SaiBcmJ4SimPlatformPort::externalState(PortLedExternalState /*lfs*/) {} + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h new file mode 100644 index 0000000000000..27bba97d9294d --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/sai/SaiBcmPlatformPort.h" + +namespace facebook::fboss { + +class SaiBcmJ4SimPlatformPort : public SaiBcmPlatformPort { + public: + SaiBcmJ4SimPlatformPort(PortID id, SaiPlatform* platform) + : SaiBcmPlatformPort(id, platform) {} + void linkStatusChanged(bool up, bool adminUp) override; + void externalState(PortLedExternalState lfs) override; + + private: + uint32_t currentLedState_{0}; +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmPlatform.cpp index b402ea8db8b6e..ac259067668ad 100644 --- a/fboss/agent/platforms/sai/SaiBcmPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiBcmPlatform.cpp @@ -227,6 +227,7 @@ phy::VCOFrequency SaiBcmPlatform::getPortVcoFrequency( case cfg::PortSpeed::GIGE: [[fallthrough]]; case cfg::PortSpeed::EIGHTHUNDREDG: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: case cfg::PortSpeed::DEFAULT: return phy::VCOFrequency::UNKNOWN; diff --git a/fboss/agent/platforms/sai/SaiPlatform.cpp b/fboss/agent/platforms/sai/SaiPlatform.cpp index b0e0ba95d1352..3135624996b11 100644 --- a/fboss/agent/platforms/sai/SaiPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiPlatform.cpp @@ -17,12 +17,14 @@ #include "fboss/agent/hw/sai/switch/SaiSwitch.h" #include "fboss/agent/hw/switch_asics/HwAsic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/platforms/sai/SaiBcmDarwinPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmElbertPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmFujiPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmIcecube800banwPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmIcecube800bcPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmIcetea800bcPlatformPort.h" +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmLadakh800bclsPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmMinipack3BTAPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmMinipackPlatformPort.h" @@ -420,6 +422,8 @@ void SaiPlatform::initPorts() { saiPort = std::make_unique(portId, this); } else if (platformMode == PlatformType::PLATFORM_TAHANSB800BC) { saiPort = std::make_unique(portId, this); + } else if (platformMode == PlatformType::PLATFORM_J4SIM) { + saiPort = std::make_unique(portId, this); } else if (platformMode == PlatformType::PLATFORM_ICECUBE800BANW) { saiPort = std::make_unique(portId, this); @@ -556,6 +560,7 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( swInfo.switchType() = cfg::SwitchType::VOQ; swInfo.switchMac() = localMac.toString(); const Jericho3Asic j3(0, swInfo); + const Jericho4Asic j4(0, swInfo); for (const auto& [id, dsfNode] : *agentCfg->thrift.sw()->dsfNodes()) { if (dsfNode.type() != cfg::DsfNodeType::INTERFACE_NODE) { continue; @@ -568,6 +573,11 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( maxSystemCoreCount = std::max(maxSystemCoreCount, uint32_t(id + j3.getNumCores())); break; + case cfg::AsicType::ASIC_TYPE_JERICHO4: + maxCoreCount = std::max(j4.getNumCores(), maxCoreCount); + maxSystemCoreCount = + std::max(maxSystemCoreCount, uint32_t(id + j4.getNumCores())); + break; default: throw FbossError("Unexpected asic type: ", *dsfNode.asicType()); } @@ -910,6 +920,13 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( mapToValueList}; } #endif + maxSystemPorts = 1024; + maxVoqs = 8 * 1024; + maxSystemPortId = 1024 - 1; + maxSwitchId = 2048; +#if defined(BRCM_SAI_SDK_XGS_AND_DNX) + localSystemPortIdRangeList = std::vector{{0, 53}}; +#endif return { initSwitch, @@ -956,7 +973,7 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( #endif dllPath, std::nullopt, // Restart Issu - switchIsolate, + std::nullopt, // switchIsolate, #if SAI_API_VERSION >= SAI_VERSION(1, 12, 0) creditWd, // Credit Watchdog creditWdMs, // Credit Watchdog Timer diff --git a/fboss/agent/platforms/sai/SaiPlatformInit.cpp b/fboss/agent/platforms/sai/SaiPlatformInit.cpp index 1a8f20c2a8b54..2e5570cf5a34f 100644 --- a/fboss/agent/platforms/sai/SaiPlatformInit.cpp +++ b/fboss/agent/platforms/sai/SaiPlatformInit.cpp @@ -21,6 +21,7 @@ #include "fboss/agent/platforms/sai/SaiBcmIcecube800banwPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmIcecube800bcPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmIcetea800bcPlatform.h" +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmLadakh800bclsPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmMinipack3BTAPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmMinipackPlatform.h" @@ -142,6 +143,9 @@ std::unique_ptr chooseSaiPlatform( } else if (productInfo->getType() == PlatformType::PLATFORM_TAHANSB800BC) { return std::make_unique( std::move(productInfo), localMac, platformMappingStr); + } else if (productInfo->getType() == PlatformType::PLATFORM_J4SIM) { + return std::make_unique( + std::move(productInfo), localMac, platformMappingStr); } else if (productInfo->getType() == PlatformType::PLATFORM_FAKE_SAI) { return std::make_unique(std::move(productInfo)); } diff --git a/fboss/agent/switch_config.thrift b/fboss/agent/switch_config.thrift index 0c8916c688ada..4e7a7703abbce 100644 --- a/fboss/agent/switch_config.thrift +++ b/fboss/agent/switch_config.thrift @@ -121,6 +121,7 @@ enum PortSpeed { TWOHUNDREDG = 200000, // 200G FOURHUNDREDG = 400000, // 400G EIGHTHUNDREDG = 800000, // 800G + ONEPOINTSIXT = 1600000, // 1.6T THREEPOINTTWOT = 3200000, // 3.2T } @@ -1543,6 +1544,7 @@ enum AsicType { ASIC_TYPE_G202X = 20, ASIC_TYPE_FAKE_NO_WARMBOOT = 21, ASIC_TYPE_TOMAHAWKULTRA1 = 22, + ASIC_TYPE_JERICHO4 = 23, } /** * The configuration for an interface diff --git a/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp b/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp index 827e2b709e2b7..000613f3b7eb0 100644 --- a/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp +++ b/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp @@ -33,6 +33,7 @@ class AgentDiagShellStressTest : public AgentHwTest { // No diag shell to test for these ASICs break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: runBcmDnxCmds(switchId); break; case cfg::AsicType::ASIC_TYPE_EBRO: diff --git a/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp b/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp index 3a83d95bfbb9f..f94027e8f9b14 100644 --- a/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp +++ b/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp @@ -373,6 +373,7 @@ void ProdInvariantTest::verifySafeDiagCommands() { case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/agent/test/utils/ConfigUtils.cpp b/fboss/agent/test/utils/ConfigUtils.cpp index 4913f667a9998..bfad452a09b73 100644 --- a/fboss/agent/test/utils/ConfigUtils.cpp +++ b/fboss/agent/test/utils/ConfigUtils.cpp @@ -87,7 +87,9 @@ int getSysPortIdsAllocated( std::optional platformType = std::nullopt) { auto portsConsumed = firstSwitchIdMin; auto deviceIndex = remoteSwitchId / asic.getNumCores(); - CHECK(asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3); + CHECK( + asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4); if (deviceIndex < getMaxRdsw(platformType)) { portsConsumed += deviceIndex * getRdswSysPortBlockSize(platformType) - 1; } else { @@ -275,7 +277,8 @@ std::unordered_map getSafeProfileIDs( auto bestSpeed = cfg::PortSpeed::DEFAULT; auto bestProfile = cfg::PortProfileID::PROFILE_DEFAULT; - if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 && + if ((asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) && FLAGS_dual_stage_rdsw_3q_2q) { // When using dual_stage_rdsw_3q_2q mapping. Pick NIF port // speed to be 400G, since that's what we have in chip config @@ -481,6 +484,7 @@ cfg::DsfNode dsfNodeConfig( case cfg::AsicType::ASIC_TYPE_JERICHO2: return PlatformType::PLATFORM_MERU400BIU; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: return PlatformType::PLATFORM_MERU800BIA; case cfg::AsicType::ASIC_TYPE_RAMON: return PlatformType::PLATFORM_MERU400BFU; @@ -871,7 +875,8 @@ cfg::SwitchConfig genPortVlanCfg( connectionHandle = "0c:00"; } else if ( asicType == cfg::AsicType::ASIC_TYPE_RAMON3 || - asicType == cfg::AsicType::ASIC_TYPE_JERICHO3) { + asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) { connectionHandle = "15:00"; } else if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO2) { connectionHandle = "68:00"; @@ -1104,7 +1109,8 @@ cfg::SwitchInfo generateSwitchInfo( switchInfo.asicType() = asicType; if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO2 || - asicType == cfg::AsicType::ASIC_TYPE_JERICHO3) { + asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) { switchInfo.switchMac() = "02:00:00:00:00:01"; } switchInfo.systemPortRanges() = asic->getSystemPortRanges(); diff --git a/fboss/agent/test/utils/CoppTestUtils.cpp b/fboss/agent/test/utils/CoppTestUtils.cpp index 3335aec4ce3cb..711f73bfafbc6 100644 --- a/fboss/agent/test/utils/CoppTestUtils.cpp +++ b/fboss/agent/test/utils/CoppTestUtils.cpp @@ -119,6 +119,7 @@ uint16_t getCoppHighPriQueueId(const HwAsic* hwAsic) { case cfg::AsicType::ASIC_TYPE_YUBA: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_G202X: return 7; case cfg::AsicType::ASIC_TYPE_CHENAB: @@ -166,6 +167,11 @@ cfg::ToCpuAction getCpuActionType(const HwAsic* hwAsic) { return cfg::ToCpuAction::COPY; case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: +<<<<<<< HEAD +======= + case cfg::AsicType::ASIC_TYPE_Q4D: + case cfg::AsicType::ASIC_TYPE_JERICHO4: +>>>>>>> 5504971436 (Address comments, and make changes to get build working for J4Sim/Jericho4) case cfg::AsicType::ASIC_TYPE_CHENAB: return cfg::ToCpuAction::TRAP; case cfg::AsicType::ASIC_TYPE_ELBERT_8DD: @@ -246,7 +252,8 @@ cfg::PortQueueRate getPortQueueRate(const HwAsic* hwAsic, uint16_t queueId) { portQueueRate.pktsPerSec() = getRange(0, pps); } else { uint32_t kbps; - if (hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3) { + if (hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3 || + hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4) { kbps = kCoppDnxLowPriKbitsPerSec; } else { kbps = getCoppQueueKbpsFromPps(hwAsic, pps); diff --git a/fboss/agent/test/utils/InvariantTestUtils.cpp b/fboss/agent/test/utils/InvariantTestUtils.cpp index cbcbe8039dc31..0cf0fbe804f68 100644 --- a/fboss/agent/test/utils/InvariantTestUtils.cpp +++ b/fboss/agent/test/utils/InvariantTestUtils.cpp @@ -46,6 +46,7 @@ void verifySafeDiagCmds(TestEnsembleIf* ensemble) { case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/lib/if/fboss_common.thrift b/fboss/lib/if/fboss_common.thrift index 9a5cbf5509ec3..10189c83ab593 100644 --- a/fboss/lib/if/fboss_common.thrift +++ b/fboss/lib/if/fboss_common.thrift @@ -58,6 +58,7 @@ enum PlatformType { PLATFORM_LADAKH800BCLS = 45, PLATFORM_MINIPACK3BTA = 46, PLATFORM_ICECUBE800BANW = 47, + PLATFORM_J4SIM = 48, # Placeholder for unknown platform type PLATFORM_UNKNOWN = 1000, } diff --git a/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json new file mode 100644 index 0000000000000..454ec80958e8f --- /dev/null +++ b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json @@ -0,0 +1,5493 @@ +{ + "ports": { + "1": { + "mapping": { + "id": 1, + "name": "eth1/1/1", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + ] + } + }, + "39": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + ] + } + } + } + }, + "2": { + "mapping": { + "id": 2, + "name": "eth1/1/2", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + ] + } + } + } + }, + "3": { + "mapping": { + "id": 3, + "name": "eth1/1/3", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + ] + } + } + } + }, + "4": { + "mapping": { + "id": 4, + "name": "eth1/1/4", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": 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"NPU-J4SIM_NIF-slot1/chip1/core4", + "type": 1, + "physicalID": 4 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core5", + "type": 1, + "physicalID": 5 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core6", + "type": 1, + "physicalID": 6 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core7", + "type": 1, + "physicalID": 7 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip1", + "type": 3, + "physicalID": 0 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip2", + "type": 3, + "physicalID": 1 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip3", + "type": 3, + "physicalID": 2 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip4", + "type": 3, + "physicalID": 3 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip5", + "type": 3, + "physicalID": 4 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip6", + "type": 3, + "physicalID": 5 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip7", + "type": 3, + "physicalID": 6 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip8", + "type": 3, + "physicalID": 7 + } + ], + "platformSupportedProfiles": [ + { + "factor": { + "profileID": 49 + }, + "profile": { + "speed": 100000, + "iphy": { + "numLanes": 1, + "modulation": 2, + "fec": 1, + "medium": 1, + "interfaceType": 10 + } + } + }, + { + "factor": { + "profileID": 50 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 1, + "interfaceType": 13 + } + } + }, + { + "factor": { + "profileID": 39 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 23 + } + } + } + ] +} diff --git a/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift b/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift index e97a65d4ede66..0fb848cd8bfd0 100644 --- a/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift +++ b/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift @@ -34,6 +34,7 @@ enum CoreType { J3_EVT = 7, // J3 Eventor Port CHENAB_NIF = 8, TH6_NIF = 9, // TH6 + J4SIM_NIF = 11, // J4Sim // Transceivers OSFP = 100, diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv new file mode 100644 index 0000000000000..0e743858d3792 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv @@ -0,0 +1,65 @@ +Global_PortID,Logical_PortID,Port_Name,Supported_Port_Profiles,Attached_CoreID,Attached_Core_PortID,Virtual_Device_ID,Port_Type,Scope,Parent_Port,Controlling_Port +1,1,eth1/1/1,50-39-49,,,,0,0,,1 +2,2,eth1/1/2,49,,,,0,0,,1 +3,3,eth1/1/3,49,,,,0,0,,1 +4,4,eth1/1/4,49,,,,0,0,,1 +5,5,eth1/1/5,49,,,,0,0,,1 +6,6,eth1/1/6,49,,,,0,0,,1 +7,7,eth1/1/7,49,,,,0,0,,1 +8,8,eth1/1/8,49,,,,0,0,,1 +9,9,eth1/2/1,50-39-49,,,,0,0,,9 +10,10,eth1/2/2,49,,,,0,0,,9 +11,11,eth1/2/3,49,,,,0,0,,9 +12,12,eth1/2/4,49,,,,0,0,,9 +13,13,eth1/2/5,49,,,,0,0,,9 +14,14,eth1/2/6,49,,,,0,0,,9 +15,15,eth1/2/7,49,,,,0,0,,9 +16,16,eth1/2/8,49,,,,0,0,,9 +17,17,eth1/3/1,50-39-49,,,,0,0,,17 +18,18,eth1/3/2,49,,,,0,0,,17 +19,19,eth1/3/3,49,,,,0,0,,17 +20,20,eth1/3/4,49,,,,0,0,,17 +21,21,eth1/3/5,49,,,,0,0,,17 +22,22,eth1/3/6,49,,,,0,0,,17 +23,23,eth1/3/7,49,,,,0,0,,17 +24,24,eth1/3/8,49,,,,0,0,,17 +25,25,eth1/4/1,50-39-49,,,,0,0,,25 +26,26,eth1/4/2,49,,,,0,0,,25 +27,27,eth1/4/3,49,,,,0,0,,25 +28,28,eth1/4/4,49,,,,0,0,,25 +29,29,eth1/4/5,49,,,,0,0,,25 +30,30,eth1/4/6,49,,,,0,0,,25 +31,31,eth1/4/7,49,,,,0,0,,25 +32,32,eth1/4/8,49,,,,0,0,,25 +33,33,eth1/5/1,50-39-49,,,,0,0,,33 +34,34,eth1/5/2,49,,,,0,0,,33 +35,35,eth1/5/3,49,,,,0,0,,33 +36,36,eth1/5/4,49,,,,0,0,,33 +37,37,eth1/5/5,49,,,,0,0,,33 +38,38,eth1/5/6,49,,,,0,0,,33 +39,39,eth1/5/7,49,,,,0,0,,33 +40,40,eth1/5/8,49,,,,0,0,,33 +41,41,eth1/6/1,50-39-49,,,,0,0,,41 +42,42,eth1/6/2,49,,,,0,0,,41 +43,43,eth1/6/3,49,,,,0,0,,41 +44,44,eth1/6/4,49,,,,0,0,,41 +45,45,eth1/6/5,49,,,,0,0,,41 +46,46,eth1/6/6,49,,,,0,0,,41 +47,47,eth1/6/7,49,,,,0,0,,41 +48,48,eth1/6/8,49,,,,0,0,,41 +49,49,eth1/7/1,50-39-49,,,,0,0,,49 +50,50,eth1/7/2,49,,,,0,0,,49 +51,51,eth1/7/3,49,,,,0,0,,49 +52,52,eth1/7/4,49,,,,0,0,,49 +53,53,eth1/7/5,49,,,,0,0,,49 +54,54,eth1/7/6,49,,,,0,0,,49 +55,55,eth1/7/7,49,,,,0,0,,49 +56,56,eth1/7/8,49,,,,0,0,,49 +57,57,eth1/8/1,50-39-49,,,,0,0,,57 +58,58,eth1/8/2,49,,,,0,0,,57 +59,59,eth1/8/3,49,,,,0,0,,57 +60,60,eth1/8/4,49,,,,0,0,,57 +61,61,eth1/8/5,49,,,,0,0,,57 +62,62,eth1/8/6,49,,,,0,0,,57 +63,63,eth1/8/7,49,,,,0,0,,57 +64,64,eth1/8/8,49,,,,0,0,,57 diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv new file mode 100644 index 0000000000000..21e1941b33437 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv @@ -0,0 +1,4 @@ +Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,A_FEC,Z_FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type +100000,NPU,TRANSCEIVER,1,PAM4,NONE,,COPPER,CR, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,OPTICAL,SR8, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv new file mode 100644 index 0000000000000..22e73c1e8cfb0 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv @@ -0,0 +1 @@ +SLOT_ID,CHIP_ID,CHIP_TYPE,CORE_ID,CORE_TYPE,CORE_LANE,LANE_SPEED(mbps),MEDIA_TYPE,TCVR_VENDOR,TCVR_PART_NUM,TCVR_MEDIA,NIC_VENDOR,CABLE_LENGTH(m),TX_PRE3,TX_PRE2,TX_PRE1,TX_MAIN,TX_POST1,TX_POST2,TX_POST3,RX_CTLE_CODE,RX_DSP_MODE,RX_AFE_TRIM diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv new file mode 100644 index 0000000000000..c5e42320a4bba --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv @@ -0,0 +1,65 @@ +A_SLOT_ID,A_CHIP_ID,A_CHIP_TYPE,A_CORE_ID,A_CORE_TYPE,A_CORE_LANE,A_PHYSICAL_TX_LANE,A_PHYSICAL_RX_LANE,A_TX_POLARITY_SWAP,A_RX_POLARITY_SWAP,Z_SLOT_ID,Z_CHIP_ID,Z_CHIP_TYPE,Z_CORE_ID,Z_CORE_TYPE,Z_CORE_LANE,Z_PHYSICAL_TX_LANE,Z_PHYSICAL_RX_LANE,Z_TX_POLARITY_SWAP,Z_RX_POLARITY_SWAP +1,1,NPU,0,J4SIM_NIF,0,0,0,N,N,1,1,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,0,J4SIM_NIF,1,1,1,N,N,1,1,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,0,J4SIM_NIF,2,2,2,N,N,1,1,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,0,J4SIM_NIF,3,3,3,N,N,1,1,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,0,J4SIM_NIF,4,4,4,N,N,1,1,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,0,J4SIM_NIF,5,5,5,N,N,1,1,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,0,J4SIM_NIF,6,6,6,N,N,1,1,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,0,J4SIM_NIF,7,7,7,N,N,1,1,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,1,J4SIM_NIF,0,0,0,N,N,1,2,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,1,J4SIM_NIF,1,1,1,N,N,1,2,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,1,J4SIM_NIF,2,2,2,N,N,1,2,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,1,J4SIM_NIF,3,3,3,N,N,1,2,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,1,J4SIM_NIF,4,4,4,N,N,1,2,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,1,J4SIM_NIF,5,5,5,N,N,1,2,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,1,J4SIM_NIF,6,6,6,N,N,1,2,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,1,J4SIM_NIF,7,7,7,N,N,1,2,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,2,J4SIM_NIF,0,0,0,N,N,1,3,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,2,J4SIM_NIF,1,1,1,N,N,1,3,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,2,J4SIM_NIF,2,2,2,N,N,1,3,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,2,J4SIM_NIF,3,3,3,N,N,1,3,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,2,J4SIM_NIF,4,4,4,N,N,1,3,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,2,J4SIM_NIF,5,5,5,N,N,1,3,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,2,J4SIM_NIF,6,6,6,N,N,1,3,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,2,J4SIM_NIF,7,7,7,N,N,1,3,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,3,J4SIM_NIF,0,0,0,N,N,1,4,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,3,J4SIM_NIF,1,1,1,N,N,1,4,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,3,J4SIM_NIF,2,2,2,N,N,1,4,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,3,J4SIM_NIF,3,3,3,N,N,1,4,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,3,J4SIM_NIF,4,4,4,N,N,1,4,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,3,J4SIM_NIF,5,5,5,N,N,1,4,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,3,J4SIM_NIF,6,6,6,N,N,1,4,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,3,J4SIM_NIF,7,7,7,N,N,1,4,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,4,J4SIM_NIF,0,0,0,N,N,1,5,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,4,J4SIM_NIF,1,1,1,N,N,1,5,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,4,J4SIM_NIF,2,2,2,N,N,1,5,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,4,J4SIM_NIF,3,3,3,N,N,1,5,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,4,J4SIM_NIF,4,4,4,N,N,1,5,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,4,J4SIM_NIF,5,5,5,N,N,1,5,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,4,J4SIM_NIF,6,6,6,N,N,1,5,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,4,J4SIM_NIF,7,7,7,N,N,1,5,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,5,J4SIM_NIF,0,0,0,N,N,1,6,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,5,J4SIM_NIF,1,1,1,N,N,1,6,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,5,J4SIM_NIF,2,2,2,N,N,1,6,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,5,J4SIM_NIF,3,3,3,N,N,1,6,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,5,J4SIM_NIF,4,4,4,N,N,1,6,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,5,J4SIM_NIF,5,5,5,N,N,1,6,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,5,J4SIM_NIF,6,6,6,N,N,1,6,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,5,J4SIM_NIF,7,7,7,N,N,1,6,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,6,J4SIM_NIF,0,0,0,N,N,1,7,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,6,J4SIM_NIF,1,1,1,N,N,1,7,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,6,J4SIM_NIF,2,2,2,N,N,1,7,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,6,J4SIM_NIF,3,3,3,N,N,1,7,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,6,J4SIM_NIF,4,4,4,N,N,1,7,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,6,J4SIM_NIF,5,5,5,N,N,1,7,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,6,J4SIM_NIF,6,6,6,N,N,1,7,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,6,J4SIM_NIF,7,7,7,N,N,1,7,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,7,J4SIM_NIF,0,0,0,N,N,1,8,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,7,J4SIM_NIF,1,1,1,N,N,1,8,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,7,J4SIM_NIF,2,2,2,N,N,1,8,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,7,J4SIM_NIF,3,3,3,N,N,1,8,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,7,J4SIM_NIF,4,4,4,N,N,1,8,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,7,J4SIM_NIF,5,5,5,N,N,1,8,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,7,J4SIM_NIF,6,6,6,N,N,1,8,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,7,J4SIM_NIF,7,7,7,N,N,1,8,TRANSCEIVER,0,OSFP,7,7,7,N,N diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json new file mode 100644 index 0000000000000..e1a2b5762eaf0 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json @@ -0,0 +1,22 @@ +{ + "config" : { + "common_config" : { + + }, + "prod_config_only" : { + + }, + "hw_test_config_only" : { + + }, + "link_test_config_only" : { + + }, + "benchmark_config_only" : { + + }, + "port_map_config" : { + + } + } +} diff --git a/fboss/lib/platform_mapping_v2/test/verify_generated_files.py b/fboss/lib/platform_mapping_v2/test/verify_generated_files.py index c7a315e6d536c..7675e639588a1 100644 --- a/fboss/lib/platform_mapping_v2/test/verify_generated_files.py +++ b/fboss/lib/platform_mapping_v2/test/verify_generated_files.py @@ -47,6 +47,7 @@ class TestVerifyPlatformMappingGeneratedFiles(unittest.TestCase): "tahansb800bc", "wedge800bact", "wedge800cact", + "j4sim", ], True: [ "meru800bfa", diff --git a/fboss/lib/platforms/PlatformMode.h b/fboss/lib/platforms/PlatformMode.h index f09eea8619ec0..93c8d05e56eb2 100644 --- a/fboss/lib/platforms/PlatformMode.h +++ b/fboss/lib/platforms/PlatformMode.h @@ -114,6 +114,8 @@ inline std::string toString(PlatformType mode) { return "LADAKH800BCLS"; case PlatformType::PLATFORM_ICECUBE800BANW: return "ICECUBE800BANW"; + case PlatformType::PLATFORM_J4SIM: + return "J4SIM"; case PlatformType::PLATFORM_UNKNOWN: return "UNKNOWN"; } diff --git a/fboss/lib/platforms/PlatformProductInfo.cpp b/fboss/lib/platforms/PlatformProductInfo.cpp index f02568a18e046..60aaf97a43d6f 100644 --- a/fboss/lib/platforms/PlatformProductInfo.cpp +++ b/fboss/lib/platforms/PlatformProductInfo.cpp @@ -210,6 +210,8 @@ void PlatformProductInfo::initMode() { modelName.find("Icecube800banw") == 0 || modelName.find("ICECUBE800BANW") == 0) { type_ = PlatformType::PLATFORM_ICECUBE800BANW; + } else if (modelName.find("J4Sim") == 0 || modelName.find("J4SIM") == 0) { + type_ = PlatformType::PLATFORM_J4SIM; } else { throw FbossError("invalid model name " + modelName); } @@ -290,6 +292,8 @@ void PlatformProductInfo::initMode() { type_ = PlatformType::PLATFORM_LADAKH800BCLS; } else if (FLAGS_mode == "icecube800banw") { type_ = PlatformType::PLATFORM_ICECUBE800BANW; + } else if (FLAGS_mode == "j4sim") { + type_ = PlatformType::PLATFORM_J4SIM; } else { throw std::runtime_error("invalid mode " + FLAGS_mode); } diff --git a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON new file mode 100644 index 0000000000000..8ee601067c320 --- /dev/null +++ b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON @@ -0,0 +1,525 @@ +{ + "defaultCommandLineArgs": { + "check_wb_handles": "true", + "classid_for_unresolved_routes": "true", + "counter_refresh_interval": "0", + "enable_acl_table_group": "true", + "intf_nbr_tables": "true", + "log_variable_name": "true", + "mode": "j4sim", + "sai_configure_six_tap": "true", + "set_classid_for_my_subnet_and_ip_routes": "true", + "skip_transceiver_programming": "true", + "use_full_dlb_scale": "true" + }, + "sw": { + "version": 0, + "ports": [], + "vlans": [], + "vlanPorts": [], + "defaultVlan": 0, + "interfaces": [ + { + "intfID": 11, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 1 + }, + { + "intfID": 17, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 1 + }, + { + "intfID": 16, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 0 + } + ], + "arpTimeoutSeconds": 60, + "arpRefreshSeconds": 20, + "arpAgerInterval": 5, + "proactiveArp": false, + "staticRoutesWithNhops": [], + "staticRoutesToNull": [], + "staticRoutesToCPU": [], + "acls": [], + "maxNeighborProbes": 300, + "staleEntryInterval": 10, + "aggregatePorts": [], + "clientIdToAdminDistance": { + "0": 20, + "1": 1, + "2": 0, + "3": 0, + "4": 0, + "700": 255, + "786": 10 + }, + "sFlowCollectors": [], + "cpuQueues": [], + "loadBalancers": [], + "mirrors": [], + "trafficCounters": [], + "qosPolicies": [], + "defaultPortQueues": [], + "staticMplsRoutesWithNhops": [], + "staticMplsRoutesToNull": [], + "staticMplsRoutesToCPU": [], + "staticIp2MplsRoutes": [], + "portQueueConfigs": {}, + "switchSettings": { + "l2LearningMode": 0, + "qcmEnable": false, + "ptpTcEnable": false, + "l2AgeTimerSeconds": 300, + "maxRouteCounterIDs": 0, + "blockNeighbors": [], + "macAddrsToBlock": [], + "switchType": 2, + "switchId": 0, + "exactMatchTableConfigs": [], + "switchIdToSwitchType_DEPRECATED": {}, + "switchDrainState": 0, + "switchIdToSwitchInfo": { + "0": { + "switchType": 2, + "asicType": 23, + "switchIndex": 0, + "portIdRange": { + "minimum": 0, + "maximum": 2047 + }, + "switchMac": "02:00:00:00:00:01", + "connectionHandle": "15:00", + "systemPortRanges": { + "systemPortRanges": [ + { + "minimum": 10, + "maximum": 53 + } + ] + }, + "localSystemPortOffset": 10, + "globalSystemPortOffset": 10, + "inbandPortId": 1 + } + }, + "vendorMacOuis": [], + "metaMacOuis": [], + "needL2EntryForNeighbor": true + }, + "aclTableGroup": { + "name": "acl-table-group-ingress", + "aclTables": [ + { + "name": "AclTable1", + "priority": 0, + "aclEntries": [], + "actionTypes": [], + "qualifiers": [], + "udfGroups": [] + } + ], + "stage": 0 + }, + "sdkVersion": { + "asicSdk": "sdk", + "saiSdk": "sai" + }, + "dsfNodes": { + "0": { + "name": "intfNode0", + "switchId": 0, + "type": 2, + "loopbackIps": [], + "nodeMac": "02:00:00:00:0F:0B", + "asicType": 23, + "platformType": 51, + "localSystemPortOffset": 10, + "globalSystemPortOffset": 10, + "systemPortRanges": { + "systemPortRanges": [ + { + "minimum": 10, + "maximum": 53 + } + ] + }, + "inbandPortId": 1, + "scheduling": 1000 + } + }, + "defaultVoqConfig": [], + "aclTableGroups": [ + { + "name": "acl-table-group-ingress", + "aclTables": [ + { + "name": "AclTable1", + "priority": 0, + "aclEntries": [], + "actionTypes": [], + "qualifiers": [], + "udfGroups": [] + } + ], + "stage": 0 + } + ], + "mirrorOnDropReports": [] + }, + "platform": { + "chip": { + "asicConfig": { + "common": { + "config": { + "programmability_image_name.BCM9941X": "AI23", + "programmability_ucode_relative_path.BCM9941X": "pemla/ucode/AI23/jr3native/u_code_db2pem.txt", + "custom_feature_programmability_standard_image_name.BCM9941X": "AI23", + "appl_param_rcy_mirror_ports_range.BCM9941X": "100-139", + "custom_feature_stop_on_access_init_error.BCM9941X": "0", + "port_priorities": "8", + "port_priorities_cpu.BCM9941X": "2", + "port_priorities_rcy": "2", + "port_priorities_sch.BCM9941X": "8", + "ucode_port_0.BCM9941X": "CPU.0:core_0.0", + "ucode_port_200.BCM9941X": "CPU.8:core_1.200", + "ucode_port_201.BCM9941X": "CPU.16:core_0.201", + "ucode_port_202.BCM9941X": "CPU.24:core_2.202", + "ucode_port_203.BCM9941X": "CPU.32:core_3.203", + "ucode_port_204.BCM9941X": "CPU.10:core_1.204:datapath_1", + "ucode_port_205.BCM9941X": "CPU.18:core_0.205:datapath_1", + "ucode_port_206.BCM9941X": "CPU.26:core_2.206:datapath_1", + "ucode_port_207.BCM9941X": "CPU.34:core_3.207:datapath_1", + "ucode_port_1.BCM9941X": "D3CE1:core_0.1:datapath_0", + "ucode_port_13.BCM9941X": "XE128:core_3.13:datapath_0", + "ucode_port_14.BCM9941X": "XE129:core_0.14:datapath_0", + "ucode_port_15.BCM9941X": "XE130:core_1.15:datapath_0", + "ucode_port_16.BCM9941X": "XE131:core_1.16:datapath_0", + "ucode_port_17.BCM9941X": "CGE18:core_2.17", + "ucode_port_19.BCM9941X": "CCGE10:core_1.19", + "ucode_port_20.BCM9941X": "CDGE4_26:core_3.20", + "port_init_cl72_1.BCM9941X": "0", + "port_init_cl72_17.BCM9941X": "0", + "ucode_port_230.BCM9941X": "EVENTOR:core_0.230", + "ucode_port_240.BCM9941X": "OLP0:core_0.240", + "ucode_port_241.BCM9941X": "OLP1:core_0.241", + "ucode_port_221.BCM9941X": "RCY.21:core_0.221", + "ucode_port_222.BCM9941X": "RCY.22:core_1.222", + "ucode_port_223.BCM9941X": "RCY.23:core_2.223", + "ucode_port_224.BCM9941X": "RCY.24:core_3.224", + "tm_port_header_type_in_221.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_222.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_223.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_224.BCM9941X": "IBCH1_MODE", + "ucode_port_225.BCM9941X": "RCY.33:core_0.244:datapath_1", + "ucode_port_226.BCM9941X": "RCY.34:core_1.244:datapath_1", + "ucode_port_227.BCM9941X": "RCY.35:core_2.244:datapath_1", + "ucode_port_228.BCM9941X": "RCY.36:core_3.244:datapath_1", + "tm_port_header_type_in_225.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_226.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_227.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_228.BCM9941X": "IBCH1_MODE", + "ucode_port_216.BCM9941X": "SAT:core_2.216", + "ucode_port_217.BCM9941X": "SAT:core_3.217", + "ucode_port_218.BCM9941X": "SAT:core_0.218", + "ucode_port_219.BCM9941X": "SAT:core_1.219", + "tm_port_header_type_in_216.BCM9941X": "INJECTED", + "tm_port_header_type_in_217.BCM9941X": "INJECTED", + "tm_port_header_type_in_218.BCM9941X": "INJECTED", + "tm_port_header_type_in_219.BCM9941X": "INJECTED", + "tm_port_header_type_out_216.BCM9941X": "CPU", + "tm_port_header_type_out_217.BCM9941X": "CPU", + "tm_port_header_type_out_218.BCM9941X": "CPU", + "tm_port_header_type_out_219.BCM9941X": "CPU", + "port_init_speed_sat.BCM9941X": "400000", + "warmboot_support.BCM9941X": "on", + "warmboot_support.BCM9941X_ADAPTER": "on", + "sw_state_max_size.BCM9941X": "1400000000", + "sw_state_max_size.BCM9941X_ADAPTER": "1400000000", + "stable_location.BCM9941X": "4", + "stable_location.BCM9941X_ADAPTER": "3", + "stable_filename.BCM9941X_ADAPTER": "warmboot_data_0", + "stable_filename.BCM9941X": "/dev/shm/warmboot_data_0", + "stable_filename.1.BCM9941X": "/dev/shm/warmboot_data_1", + "stable_filename.2.BCM9941X": "/dev/shm/warmboot_data_2", + "stable_size.BCM9941X": "1450000000", + "stable_size.BCM9941X_ADAPTER": "1450000000", + "dma_desc_aggregator_chain_length_max.BCM9941X": "256", + "dma_desc_aggregator_buff_size_kb.BCM9941X": "32", + "dma_desc_aggregator_enable_specific_MDB_LPM.BCM9941X": "1", + "dma_desc_aggregator_enable_specific_MDB_FEC.BCM9941X": "1", + "outlif_physical_phase_data_granularity_1.BCM9941X": "60", + "outlif_physical_phase_data_granularity_2.BCM9941X": "60", + "outlif_physical_phase_data_granularity_3.BCM9941X": "60", + "outlif_physical_phase_data_granularity_4.BCM9941X": "60", + "outlif_physical_phase_data_granularity_5.BCM9941X": "60", + "outlif_physical_phase_data_granularity_6.BCM9941X": "60", + "outlif_physical_phase_data_granularity_7.BCM9941X": "60", + "outlif_physical_phase_data_granularity_8.BCM9941X": "60", + "pmf_maps_payload_size.BCM9941X": "30", + "pmf_nexem2_stage.BCM9941X": "IPMF3", + "tm_port_header_type_in_0.BCM9941X": "INJECTED", + "tm_port_header_type_out_0.BCM9941X": "CPU", + "tm_port_header_type_in_200.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_200.BCM9941X": "ETH", + "tm_port_header_type_in_201.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_201.BCM9941X": "ETH", + "tm_port_header_type_in_202.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_202.BCM9941X": "ETH", + "tm_port_header_type_in_203.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_203.BCM9941X": "ETH", + "tm_port_header_type_in_204.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_204.BCM9941X": "ETH", + "tm_port_header_type_in_205.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_205.BCM9941X": "ETH", + "tm_port_header_type_in_206.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_206.BCM9941X": "ETH", + "tm_port_header_type_in_207.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_207.BCM9941X": "ETH", + "tm_port_header_type_in_230.BCM9941X": "INJECTED", + "tm_port_header_type_in_240.BCM9941X": "TM", + "tm_port_header_type_out_240.BCM9941X": "ETH", + "tm_port_header_type_in_241.BCM9941X": "TM", + "tm_port_header_type_out_241.BCM9941X": "ETH", + "fabric_connect_mode.BCM9941X": "SINGLE_FAP", + "fabric_distributed_system_enable.BCM9941X": "0", + "port_init_speed_fabric.BCM9941X": "212500", + "port_init_speed_xe13.BCM9941X": "10000", + "port_init_speed_xe14.BCM9941X": "10000", + "port_init_speed_xe15.BCM9941X": "10000", + "port_init_speed_xe16.BCM9941X": "10000", + "port_init_speed_xe.BCM9941X": "25000", + "port_init_speed_xl.BCM9941X": "40000", + "port_init_speed_le.BCM9941X": "50000", + "port_init_speed_ce.BCM9941X": "100000", + "port_init_speed_cc.BCM9941X": "200000", + "port_init_speed_cd.BCM9941X": "400000", + "port_init_speed_d3c.BCM9941X": "800000", + "port_init_speed_mdc.BCM9941X": "1600000", + "custom_feature_adapter_do_collect_enable.BCM9941X_ADAPTER": "1", + "mem_cache_enable_all.BCM9941X_ADAPTER": "1", + "custom_feature_use_new_access.BCM9941X": "1", + "custom_feature_use_new_access.BCM9941X_ADAPTER": "1", + "maximal_port_bandwidth.BCM9941X": "1800000", + "dtm_flow_mapping_mode_region_97.BCM9941X": "3", + "dtm_flow_mapping_mode_region_98.BCM9941X": "3", + "dtm_flow_mapping_mode_region_99.BCM9941X": "3", + "dtm_flow_mapping_mode_region_100.BCM9941X": "3", + "dtm_flow_mapping_mode_region_101.BCM9941X": "3", + "dtm_flow_mapping_mode_region_102.BCM9941X": "3", + "dtm_flow_mapping_mode_region_103.BCM9941X": "3", + "dtm_flow_mapping_mode_region_104.BCM9941X": "3", + "dtm_flow_mapping_mode_region_105.BCM9941X": "3", + "dtm_flow_mapping_mode_region_106.BCM9941X": "7", + "dtm_flow_mapping_mode_region_107.BCM9941X": "3", + "dtm_flow_mapping_mode_region_108.BCM9941X": "3", + "dtm_flow_mapping_mode_region_109.BCM9941X": "3", + "dtm_flow_mapping_mode_region_110.BCM9941X": "3", + "dtm_flow_mapping_mode_region_111.BCM9941X": "3", + "dtm_flow_mapping_mode_region_112.BCM9941X": "3", + "dtm_flow_mapping_mode_region_113.BCM9941X": "3", + "dtm_flow_mapping_mode_region_114.BCM9941X": "3", + "dtm_flow_mapping_mode_region_115.BCM9941X": "3", + "dtm_flow_mapping_mode_region_116.BCM9941X": "3", + "dtm_flow_mapping_mode_region_117.BCM9941X": "3", + "dtm_flow_mapping_mode_region_118.BCM9941X": "3", + "dtm_flow_mapping_mode_region_119.BCM9941X": "3", + "dtm_flow_mapping_mode_region_120.BCM9941X": "3", + "dtm_flow_nof_remote_cores_region.BCM9941X": "4", + "polled_irq_mode.BCM9941X_ADAPTER": "1", + "polled_irq_delay.BCM9941X_ADAPTER": "200000", + "dram_temperature_monitor_enable.BCM9941X_ADAPTER": "0", + "custom_feature_statdma_enable.BCM9941X_ADAPTER": "0", + "bcm_stat_interval.BCM9941X_ADAPTER": "0", + "bcm_stat_interval.BCM9941X": "0", + "pktio_driver_type.BCM9941X": "1", + "pktio_driver_type.BCM9941X_ADAPTER": "1", + "pci_override_dev": "0x9410", + "fail_on_unsupported_attribute": "1", + "sai_dis_ctr_incr_on_port_ln_dn": "0", + "sai_disable_srcmacqedstmac_ctrl": "0x1", + "sai_eventor_port_lane_base": "1000", + "sai_global_scoped_rcy_port": "8", + "sai_l3_max_ecmp_paths": "512", + "sai_ocb_fc_config": "2", + "sai_pfc_defaults_disable": "0x1", + "sai_recycle_port_lane_base": "512", + "sai_tc_mirror_buffer_size_bytes": "1", + "sai_trigger_linkscan_remote_local_faults": "1", + "sai_uncached_port_stats": "0x1", + "sai_voq_wm_latency_enable": "1", + "dpp_db_path": "/root/brcmsim/tools/sand/db", + "lane_to_serdes_map_nif_lane0.BCM9941X": "rx0:tx0", + "lane_to_serdes_map_nif_lane1.BCM9941X": "rx1:tx1", + "lane_to_serdes_map_nif_lane2.BCM9941X": "rx2:tx2", + "lane_to_serdes_map_nif_lane3.BCM9941X": "rx3:tx3", + "lane_to_serdes_map_nif_lane4.BCM9941X": "rx4:tx4", + "lane_to_serdes_map_nif_lane5.BCM9941X": "rx5:tx5", + "lane_to_serdes_map_nif_lane6.BCM9941X": "rx6:tx6", + "lane_to_serdes_map_nif_lane7.BCM9941X": "rx7:tx7", + "lane_to_serdes_map_nif_lane8.BCM9941X": "rx8:tx8", + "lane_to_serdes_map_nif_lane9.BCM9941X": "rx9:tx9", + "lane_to_serdes_map_nif_lane10.BCM9941X": "rx10:tx10", + "lane_to_serdes_map_nif_lane11.BCM9941X": "rx11:tx11", + "lane_to_serdes_map_nif_lane12.BCM9941X": "rx12:tx12", + "lane_to_serdes_map_nif_lane13.BCM9941X": "rx13:tx13", + "lane_to_serdes_map_nif_lane14.BCM9941X": "rx14:tx14", + "lane_to_serdes_map_nif_lane15.BCM9941X": "rx15:tx15", + "lane_to_serdes_map_nif_lane16.BCM9941X": "rx16:tx16", + "lane_to_serdes_map_nif_lane17.BCM9941X": "rx17:tx17", + "lane_to_serdes_map_nif_lane18.BCM9941X": "rx18:tx18", + "lane_to_serdes_map_nif_lane19.BCM9941X": "rx19:tx19", + "lane_to_serdes_map_nif_lane20.BCM9941X": "rx20:tx20", + "lane_to_serdes_map_nif_lane21.BCM9941X": "rx21:tx21", + "lane_to_serdes_map_nif_lane22.BCM9941X": "rx22:tx22", + "lane_to_serdes_map_nif_lane23.BCM9941X": "rx23:tx23", + "lane_to_serdes_map_nif_lane24.BCM9941X": "rx24:tx24", + "lane_to_serdes_map_nif_lane25.BCM9941X": "rx25:tx25", + "lane_to_serdes_map_nif_lane26.BCM9941X": "rx26:tx26", + "lane_to_serdes_map_nif_lane27.BCM9941X": "rx27:tx27", + "lane_to_serdes_map_nif_lane28.BCM9941X": "rx28:tx28", + "lane_to_serdes_map_nif_lane29.BCM9941X": "rx29:tx29", + "lane_to_serdes_map_nif_lane30.BCM9941X": "rx30:tx30", + "lane_to_serdes_map_nif_lane31.BCM9941X": "rx31:tx31", + "lane_to_serdes_map_nif_lane32.BCM9941X": "rx32:tx32", + "lane_to_serdes_map_nif_lane33.BCM9941X": "rx33:tx33", + "lane_to_serdes_map_nif_lane34.BCM9941X": "rx34:tx34", + "lane_to_serdes_map_nif_lane35.BCM9941X": "rx35:tx35", + "lane_to_serdes_map_nif_lane36.BCM9941X": "rx36:tx36", + "lane_to_serdes_map_nif_lane37.BCM9941X": "rx37:tx37", + "lane_to_serdes_map_nif_lane38.BCM9941X": "rx38:tx38", + "lane_to_serdes_map_nif_lane39.BCM9941X": "rx39:tx39", + "lane_to_serdes_map_nif_lane40.BCM9941X": "rx40:tx40", + "lane_to_serdes_map_nif_lane41.BCM9941X": "rx41:tx41", + "lane_to_serdes_map_nif_lane42.BCM9941X": "rx42:tx42", + "lane_to_serdes_map_nif_lane43.BCM9941X": "rx43:tx43", + "lane_to_serdes_map_nif_lane44.BCM9941X": "rx44:tx44", + "lane_to_serdes_map_nif_lane45.BCM9941X": "rx45:tx45", + "lane_to_serdes_map_nif_lane46.BCM9941X": "rx46:tx46", + "lane_to_serdes_map_nif_lane47.BCM9941X": "rx47:tx47", + "lane_to_serdes_map_nif_lane48.BCM9941X": "rx48:tx48", + "lane_to_serdes_map_nif_lane49.BCM9941X": "rx49:tx49", + "lane_to_serdes_map_nif_lane50.BCM9941X": "rx50:tx50", + "lane_to_serdes_map_nif_lane51.BCM9941X": "rx51:tx51", + "lane_to_serdes_map_nif_lane52.BCM9941X": "rx52:tx52", + "lane_to_serdes_map_nif_lane53.BCM9941X": "rx53:tx53", + "lane_to_serdes_map_nif_lane54.BCM9941X": "rx54:tx54", + "lane_to_serdes_map_nif_lane55.BCM9941X": "rx55:tx55", + "lane_to_serdes_map_nif_lane56.BCM9941X": "rx56:tx56", + "lane_to_serdes_map_nif_lane57.BCM9941X": "rx57:tx57", + "lane_to_serdes_map_nif_lane58.BCM9941X": "rx58:tx58", + "lane_to_serdes_map_nif_lane59.BCM9941X": "rx59:tx59", + "lane_to_serdes_map_nif_lane60.BCM9941X": "rx60:tx60", + "lane_to_serdes_map_nif_lane61.BCM9941X": "rx61:tx61", + "lane_to_serdes_map_nif_lane62.BCM9941X": "rx62:tx62", + "lane_to_serdes_map_nif_lane63.BCM9941X": "rx63:tx63", + "lane_to_serdes_map_nif_lane64.BCM9941X": "rx64:tx64", + "lane_to_serdes_map_nif_lane65.BCM9941X": "rx65:tx65", + "lane_to_serdes_map_nif_lane66.BCM9941X": "rx66:tx66", + "lane_to_serdes_map_nif_lane67.BCM9941X": "rx67:tx67", + "lane_to_serdes_map_nif_lane68.BCM9941X": "rx68:tx68", + "lane_to_serdes_map_nif_lane69.BCM9941X": "rx69:tx69", + "lane_to_serdes_map_nif_lane70.BCM9941X": "rx70:tx70", + "lane_to_serdes_map_nif_lane71.BCM9941X": "rx71:tx71", + "lane_to_serdes_map_nif_lane72.BCM9941X": "rx72:tx72", + "lane_to_serdes_map_nif_lane73.BCM9941X": "rx73:tx73", + "lane_to_serdes_map_nif_lane74.BCM9941X": "rx74:tx74", + "lane_to_serdes_map_nif_lane75.BCM9941X": "rx75:tx75", + "lane_to_serdes_map_nif_lane76.BCM9941X": "rx76:tx76", + "lane_to_serdes_map_nif_lane77.BCM9941X": "rx77:tx77", + "lane_to_serdes_map_nif_lane78.BCM9941X": "rx78:tx78", + "lane_to_serdes_map_nif_lane79.BCM9941X": "rx79:tx79", + "lane_to_serdes_map_nif_lane80.BCM9941X": "rx80:tx80", + "lane_to_serdes_map_nif_lane81.BCM9941X": "rx81:tx81", + "lane_to_serdes_map_nif_lane82.BCM9941X": "rx82:tx82", + "lane_to_serdes_map_nif_lane83.BCM9941X": "rx83:tx83", + "lane_to_serdes_map_nif_lane84.BCM9941X": "rx84:tx84", + "lane_to_serdes_map_nif_lane85.BCM9941X": "rx85:tx85", + "lane_to_serdes_map_nif_lane86.BCM9941X": "rx86:tx86", + "lane_to_serdes_map_nif_lane87.BCM9941X": "rx87:tx87", + "lane_to_serdes_map_nif_lane88.BCM9941X": "rx88:tx88", + "lane_to_serdes_map_nif_lane89.BCM9941X": "rx89:tx89", + "lane_to_serdes_map_nif_lane90.BCM9941X": "rx90:tx90", + "lane_to_serdes_map_nif_lane91.BCM9941X": "rx91:tx91", + "lane_to_serdes_map_nif_lane92.BCM9941X": "rx92:tx92", + "lane_to_serdes_map_nif_lane93.BCM9941X": "rx93:tx93", + "lane_to_serdes_map_nif_lane94.BCM9941X": "rx94:tx94", + "lane_to_serdes_map_nif_lane95.BCM9941X": "rx95:tx95", + "lane_to_serdes_map_nif_lane96.BCM9941X": "rx96:tx96", + "lane_to_serdes_map_nif_lane97.BCM9941X": "rx97:tx97", + "lane_to_serdes_map_nif_lane98.BCM9941X": "rx98:tx98", + "lane_to_serdes_map_nif_lane99.BCM9941X": "rx99:tx99", + "lane_to_serdes_map_nif_lane100.BCM9941X": "rx100:tx100", + "lane_to_serdes_map_nif_lane101.BCM9941X": "rx101:tx101", + "lane_to_serdes_map_nif_lane102.BCM9941X": "rx102:tx102", + "lane_to_serdes_map_nif_lane103.BCM9941X": "rx103:tx103", + "lane_to_serdes_map_nif_lane104.BCM9941X": "rx104:tx104", + "lane_to_serdes_map_nif_lane105.BCM9941X": "rx105:tx105", + "lane_to_serdes_map_nif_lane106.BCM9941X": "rx106:tx106", + "lane_to_serdes_map_nif_lane107.BCM9941X": "rx107:tx107", + "lane_to_serdes_map_nif_lane108.BCM9941X": "rx108:tx108", + "lane_to_serdes_map_nif_lane109.BCM9941X": "rx109:tx109", + "lane_to_serdes_map_nif_lane110.BCM9941X": "rx110:tx110", + "lane_to_serdes_map_nif_lane111.BCM9941X": "rx111:tx111", + "lane_to_serdes_map_nif_lane112.BCM9941X": "rx112:tx112", + "lane_to_serdes_map_nif_lane113.BCM9941X": "rx113:tx113", + "lane_to_serdes_map_nif_lane114.BCM9941X": "rx114:tx114", + "lane_to_serdes_map_nif_lane115.BCM9941X": "rx115:tx115", + "lane_to_serdes_map_nif_lane116.BCM9941X": "rx116:tx116", + "lane_to_serdes_map_nif_lane117.BCM9941X": "rx117:tx117", + "lane_to_serdes_map_nif_lane118.BCM9941X": "rx118:tx118", + "lane_to_serdes_map_nif_lane119.BCM9941X": "rx119:tx119", + "lane_to_serdes_map_nif_lane120.BCM9941X": "rx120:tx120", + "lane_to_serdes_map_nif_lane121.BCM9941X": "rx121:tx121", + "lane_to_serdes_map_nif_lane122.BCM9941X": "rx122:tx122", + "lane_to_serdes_map_nif_lane123.BCM9941X": "rx123:tx123", + "lane_to_serdes_map_nif_lane124.BCM9941X": "rx124:tx124", + "lane_to_serdes_map_nif_lane125.BCM9941X": "rx125:tx125", + "lane_to_serdes_map_nif_lane126.BCM9941X": "rx126:tx126", + "lane_to_serdes_map_nif_lane127.BCM9941X": "rx127:tx127", + "lane_to_serdes_map_nif_lane128.BCM9941X": "rx128:tx128", + "lane_to_serdes_map_nif_lane129.BCM9941X": "rx129:tx129", + "lane_to_serdes_map_nif_lane130.BCM9941X": "rx130:tx130", + "lane_to_serdes_map_nif_lane131.BCM9941X": "rx131:tx131", + "lane_to_serdes_map_nif_lane132.BCM9941X": "rx132:tx132", + "lane_to_serdes_map_nif_lane133.BCM9941X": "rx133:tx133", + "lane_to_serdes_map_nif_lane134.BCM9941X": "rx134:tx134", + "lane_to_serdes_map_nif_lane135.BCM9941X": "rx135:tx135", + "lane_to_serdes_map_nif_lane136.BCM9941X": "rx136:tx136", + "lane_to_serdes_map_nif_lane137.BCM9941X": "rx137:tx137", + "lane_to_serdes_map_nif_lane138.BCM9941X": "rx138:tx138", + "lane_to_serdes_map_nif_lane139.BCM9941X": "rx139:tx139", + "lane_to_serdes_map_nif_lane140.BCM9941X": "rx140:tx140", + "lane_to_serdes_map_nif_lane141.BCM9941X": "rx141:tx141", + "lane_to_serdes_map_nif_lane142.BCM9941X": "rx142:tx142", + "lane_to_serdes_map_nif_lane143.BCM9941X": "rx143:tx143", + "lane_to_serdes_map_nif_lane144.BCM9941X": "rx144:tx144", + "lane_to_serdes_map_nif_lane145.BCM9941X": "rx145:tx145", + "lane_to_serdes_map_nif_lane146.BCM9941X": "rx146:tx146", + "lane_to_serdes_map_nif_lane147.BCM9941X": "rx147:tx147" + } + } + } + } + }, + "thriftApiToRateLimitInQps": {} +} diff --git a/fboss/platform/configs/j4sim/platform_manager.json b/fboss/platform/configs/j4sim/platform_manager.json new file mode 100644 index 0000000000000..eb6d3f97dbf1a --- /dev/null +++ b/fboss/platform/configs/j4sim/platform_manager.json @@ -0,0 +1,452 @@ +{ + "platformName": "J4SIM", + "rootPmUnitName": "SCM", + "rootSlotType": "SCM_SLOT", + "slotTypeConfigs": { + "SCM_SLOT": { + "numOutgoingI2cBuses": 0, + "idpromConfig": { + "busName": "SMBus I801 adapter at 1000", + "address": "0x50", + "kernelDeviceName": "24c512", + "offset": 15360 + }, + "pmUnitName": "SCM" + }, + "SMB_SLOT": { + "numOutgoingI2cBuses": 5, + "idpromConfig": { + "busName": "INCOMING@1", + "address": "0x50", + "kernelDeviceName": "24c512", + "offset": 15360 + }, + "pmUnitName": "SMB" + }, + "PSU_SLOT": { + "numOutgoingI2cBuses": 1, + "pmUnitName": "PSU" + }, + "FAN_SLOT": { + "numOutgoingI2cBuses": 0, + "pmUnitName": "FAN" + } + }, + "pmUnitConfigs": { + "SCM": { + "pluggedInSlotType": "SCM_SLOT", + "i2cDeviceConfigs": [ + { + "busName": "SCM_I2C_MASTER_0@0", + "address": "0x40", + "kernelDeviceName": "pmbus", + "pmUnitScopedName": "SCM_MPS_PMBUS" + } + ], + "outgoingSlotConfigs": { + "SMB_SLOT@0": { + "slotType": "SMB_SLOT", + "outgoingI2cBusNames": [ + "SCM_I2C_MASTER_0@0", + "SCM_I2C_MASTER_1@0", + "SCM_I2C_MASTER_1@1", + "SCM_I2C_MASTER_1@2", + "SCM_I2C_MASTER_1@3" + ] + } + }, + "pciDeviceConfigs": [ + { + "pmUnitScopedName": "SCM_FPGA", + "vendorId": "0x3475", + "deviceId": "0x0001", + "subSystemVendorId": "0x3475", + "subSystemDeviceId": "0x0008", + "i2cAdapterBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "SCM_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8000 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 0, + "numAdapters": 2, + "numBusesPerAdapter": 8 + } + ], + "spiMasterConfigs": [], + "infoRomConfigs": [ + { + "pmUnitScopedName": "SCM_FPGA_INFO_ROM", + "deviceName": "fpga_info_iob", + "csrOffset": "0x100" + } + ], + "miscCtrlConfigs": [ + { + "pmUnitScopedName": "SCM_ADC", + "deviceName": "adc", + "csrOffset": "0x7300" + } + ] + } + ], + "embeddedSensorConfigs": [ + { + "pmUnitScopedName": "CPU_CORE_TEMP", + "sysfsPath": "/sys/bus/platform/devices/coretemp.0" + }, + { + "pmUnitScopedName": "NVME_TEMP", + "sysfsPath": "/sys/class/nvme/nvme0" + } + ] + }, + "SMB": { + "pluggedInSlotType": "SMB_SLOT", + "i2cDeviceConfigs": [ + { + "busName": "INCOMING@1", + "address": "0x50", + "kernelDeviceName": "24c512", + "pmUnitScopedName": "CHASSIS_EEPROM", + "isEeprom": true, + "eepromOffset": 15360 + } + ], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [ + { + "pmUnitScopedName": "SMB_FPGA", + "vendorId": "0x3475", + "deviceId": "0x0001", + "subSystemVendorId": "0x3475", + "subSystemDeviceId": "0x0015", + "i2cAdapterBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "SMB_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8000 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 0, + "numAdapters": 2, + "numBusesPerAdapter": 6 + }, + { + "pmUnitScopedNamePrefix": "SMB_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8100 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 2, + "numAdapters": 8, + "numBusesPerAdapter": 8 + } + ], + "spiMasterConfigs": [], + "ledCtrlBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "OSFP", + "deviceName": "port_led", + "csrOffsetCalc": "0x6100 + ({portNum} - {startPort})*0x20 + ({ledNum} - 1)*0x10", + "numPorts": 64, + "ledPerPort": 2, + "startPort": 1 + }, + { + "pmUnitScopedNamePrefix": "QSFP", + "deviceName": "port_led", + "csrOffsetCalc": "0x6900 + ({portNum} - {startPort})*0x10 + ({ledNum} - 1)*0x10", + "numPorts": 4, + "ledPerPort": 1, + "startPort": 65 + } + ], + "xcvrCtrlBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "OSFP", + "deviceName": "xcvr_ctrl", + "csrOffsetCalc": "0xa010 + ({portNum} - {startPort})*0x10", + "numPorts": 64, + "startPort": 1 + }, + { + "pmUnitScopedNamePrefix": "QSFP", + "deviceName": "xcvr_ctrl", + "csrOffsetCalc": "0xa410 + ({portNum} - {startPort})*0x10", + "numPorts": 4, + "startPort": 65 + } + ], + "infoRomConfigs": [] + } + ] + }, + "PSU": { + "pluggedInSlotType": "PSU_SLOT", + "i2cDeviceConfigs": [ + { + "busName": "INCOMING@0", + "address": "0x58", + "kernelDeviceName": "pmbus", + "pmUnitScopedName": "PSU_PMBUS" + } + ], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [] + }, + "FAN": { + "pluggedInSlotType": "FAN_SLOT", + "i2cDeviceConfigs": [], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [] + } + }, + "i2cAdaptersFromCpu": [ + "SMBus I801 adapter at 1000" + ], + "symbolicLinkToDevicePath": { + "/run/devmap/fpgas/MERU_SCM_CPLD": "/[SCM_FPGA]", + "/run/devmap/fpgas/MERU_SCM_CPLD_INFO_ROM": "/[SCM_FPGA_INFO_ROM]", + "/run/devmap/inforoms/MERU_SCM_CPLD_INFO_ROM": "/[SCM_FPGA_INFO_ROM]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH0": "/[SCM_I2C_MASTER_0@0]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH1": "/[SCM_I2C_MASTER_0@1]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH2": "/[SCM_I2C_MASTER_0@2]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH3": "/[SCM_I2C_MASTER_0@3]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH4": "/[SCM_I2C_MASTER_0@4]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH5": "/[SCM_I2C_MASTER_0@5]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH6": "/[SCM_I2C_MASTER_0@6]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH7": "/[SCM_I2C_MASTER_0@7]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH0": "/[SCM_I2C_MASTER_1@0]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH1": "/[SCM_I2C_MASTER_1@1]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH2": "/[SCM_I2C_MASTER_1@2]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH3": "/[SCM_I2C_MASTER_1@3]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH4": "/[SCM_I2C_MASTER_1@4]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH5": "/[SCM_I2C_MASTER_1@5]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH6": "/[SCM_I2C_MASTER_1@6]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH7": "/[SCM_I2C_MASTER_1@7]", + "/run/devmap/eeproms/SMB_EEPROM": "/SMB_SLOT@0/[IDPROM]", + "/run/devmap/sensors/CPU_MPS_PMBUS": "/[SCM_MPS_PMBUS]", + "/run/devmap/sensors/CPU_CORE_TEMP": "/[CPU_CORE_TEMP]", + "/run/devmap/sensors/NVME_TEMP": "/[NVME_TEMP]", + "/run/devmap/fpgas/SMB_FPGA": "/SMB_SLOT@0/[SMB_FPGA]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@7]", + "/run/devmap/eeproms/CHASSIS_EEPROM": "/SMB_SLOT@0/[CHASSIS_EEPROM]", + "/run/devmap/xcvrs/xcvr_io_1": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@0]", + "/run/devmap/xcvrs/xcvr_ctrl_1": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_1]", + "/run/devmap/xcvrs/xcvr_io_2": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@1]", + "/run/devmap/xcvrs/xcvr_ctrl_2": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_2]", + "/run/devmap/xcvrs/xcvr_io_3": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@2]", + "/run/devmap/xcvrs/xcvr_ctrl_3": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_3]", + "/run/devmap/xcvrs/xcvr_io_4": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@3]", + "/run/devmap/xcvrs/xcvr_ctrl_4": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_4]", + "/run/devmap/xcvrs/xcvr_io_5": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@4]", + "/run/devmap/xcvrs/xcvr_ctrl_5": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_5]", + "/run/devmap/xcvrs/xcvr_io_6": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@5]", + "/run/devmap/xcvrs/xcvr_ctrl_6": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_6]", + "/run/devmap/xcvrs/xcvr_io_7": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@6]", + "/run/devmap/xcvrs/xcvr_ctrl_7": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_7]", + "/run/devmap/xcvrs/xcvr_io_8": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@7]", + "/run/devmap/xcvrs/xcvr_ctrl_8": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_8]", + "/run/devmap/xcvrs/xcvr_io_9": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@0]", + "/run/devmap/xcvrs/xcvr_ctrl_9": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_9]", + "/run/devmap/xcvrs/xcvr_io_10": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@1]", + "/run/devmap/xcvrs/xcvr_ctrl_10": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_10]", + "/run/devmap/xcvrs/xcvr_io_11": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@2]", + "/run/devmap/xcvrs/xcvr_ctrl_11": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_11]", + "/run/devmap/xcvrs/xcvr_io_12": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@3]", + "/run/devmap/xcvrs/xcvr_ctrl_12": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_12]", + "/run/devmap/xcvrs/xcvr_io_13": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@4]", + "/run/devmap/xcvrs/xcvr_ctrl_13": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_13]", + "/run/devmap/xcvrs/xcvr_io_14": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@5]", + "/run/devmap/xcvrs/xcvr_ctrl_14": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_14]", + "/run/devmap/xcvrs/xcvr_io_15": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@6]", + "/run/devmap/xcvrs/xcvr_ctrl_15": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_15]", + "/run/devmap/xcvrs/xcvr_io_16": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@7]", + "/run/devmap/xcvrs/xcvr_ctrl_16": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_16]", + "/run/devmap/xcvrs/xcvr_io_17": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@0]", + "/run/devmap/xcvrs/xcvr_ctrl_17": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_17]", + "/run/devmap/xcvrs/xcvr_io_18": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@1]", + "/run/devmap/xcvrs/xcvr_ctrl_18": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_18]", + "/run/devmap/xcvrs/xcvr_io_19": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@2]", + "/run/devmap/xcvrs/xcvr_ctrl_19": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_19]", + "/run/devmap/xcvrs/xcvr_io_20": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@3]", + "/run/devmap/xcvrs/xcvr_ctrl_20": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_20]", + "/run/devmap/xcvrs/xcvr_io_21": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@4]", + "/run/devmap/xcvrs/xcvr_ctrl_21": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_21]", + "/run/devmap/xcvrs/xcvr_io_22": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@5]", + "/run/devmap/xcvrs/xcvr_ctrl_22": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_22]", + "/run/devmap/xcvrs/xcvr_io_23": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@6]", + "/run/devmap/xcvrs/xcvr_ctrl_23": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_23]", + "/run/devmap/xcvrs/xcvr_io_24": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@7]", + "/run/devmap/xcvrs/xcvr_ctrl_24": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_24]", + "/run/devmap/xcvrs/xcvr_io_25": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@0]", + "/run/devmap/xcvrs/xcvr_ctrl_25": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_25]", + "/run/devmap/xcvrs/xcvr_io_26": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@1]", + "/run/devmap/xcvrs/xcvr_ctrl_26": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_26]", + "/run/devmap/xcvrs/xcvr_io_27": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@2]", + "/run/devmap/xcvrs/xcvr_ctrl_27": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_27]", + "/run/devmap/xcvrs/xcvr_io_28": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@3]", + "/run/devmap/xcvrs/xcvr_ctrl_28": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_28]", + "/run/devmap/xcvrs/xcvr_io_29": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@4]", + "/run/devmap/xcvrs/xcvr_ctrl_29": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_29]", + "/run/devmap/xcvrs/xcvr_io_30": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@5]", + "/run/devmap/xcvrs/xcvr_ctrl_30": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_30]", + "/run/devmap/xcvrs/xcvr_io_31": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@6]", + "/run/devmap/xcvrs/xcvr_ctrl_31": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_31]", + "/run/devmap/xcvrs/xcvr_io_32": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@7]", + "/run/devmap/xcvrs/xcvr_ctrl_32": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_32]", + "/run/devmap/xcvrs/xcvr_io_33": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@0]", + "/run/devmap/xcvrs/xcvr_ctrl_33": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_33]", + "/run/devmap/xcvrs/xcvr_io_34": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@1]", + "/run/devmap/xcvrs/xcvr_ctrl_34": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_34]", + "/run/devmap/xcvrs/xcvr_io_35": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@2]", + "/run/devmap/xcvrs/xcvr_ctrl_35": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_35]", + "/run/devmap/xcvrs/xcvr_io_36": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@3]", + "/run/devmap/xcvrs/xcvr_ctrl_36": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_36]", + "/run/devmap/xcvrs/xcvr_io_37": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@4]", + "/run/devmap/xcvrs/xcvr_ctrl_37": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_37]", + "/run/devmap/xcvrs/xcvr_io_38": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@5]", + "/run/devmap/xcvrs/xcvr_ctrl_38": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_38]", + "/run/devmap/xcvrs/xcvr_io_39": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@6]", + "/run/devmap/xcvrs/xcvr_ctrl_39": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_39]", + "/run/devmap/xcvrs/xcvr_io_40": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@7]", + "/run/devmap/xcvrs/xcvr_ctrl_40": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_40]", + "/run/devmap/xcvrs/xcvr_io_41": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@0]", + "/run/devmap/xcvrs/xcvr_ctrl_41": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_41]", + "/run/devmap/xcvrs/xcvr_io_42": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@1]", + "/run/devmap/xcvrs/xcvr_ctrl_42": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_42]", + "/run/devmap/xcvrs/xcvr_io_43": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@2]", + "/run/devmap/xcvrs/xcvr_ctrl_43": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_43]", + "/run/devmap/xcvrs/xcvr_io_44": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@3]", + "/run/devmap/xcvrs/xcvr_ctrl_44": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_44]", + "/run/devmap/xcvrs/xcvr_io_45": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@4]", + "/run/devmap/xcvrs/xcvr_ctrl_45": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_45]", + "/run/devmap/xcvrs/xcvr_io_46": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@5]", + "/run/devmap/xcvrs/xcvr_ctrl_46": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_46]", + "/run/devmap/xcvrs/xcvr_io_47": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@6]", + "/run/devmap/xcvrs/xcvr_ctrl_47": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_47]", + "/run/devmap/xcvrs/xcvr_io_48": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@7]", + "/run/devmap/xcvrs/xcvr_ctrl_48": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_48]", + "/run/devmap/xcvrs/xcvr_io_49": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@0]", + "/run/devmap/xcvrs/xcvr_ctrl_49": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_49]", + "/run/devmap/xcvrs/xcvr_io_50": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@1]", + "/run/devmap/xcvrs/xcvr_ctrl_50": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_50]", + "/run/devmap/xcvrs/xcvr_io_51": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@2]", + "/run/devmap/xcvrs/xcvr_ctrl_51": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_51]", + "/run/devmap/xcvrs/xcvr_io_52": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@3]", + "/run/devmap/xcvrs/xcvr_ctrl_52": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_52]", + "/run/devmap/xcvrs/xcvr_io_53": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@4]", + "/run/devmap/xcvrs/xcvr_ctrl_53": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_53]", + "/run/devmap/xcvrs/xcvr_io_54": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@5]", + "/run/devmap/xcvrs/xcvr_ctrl_54": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_54]", + "/run/devmap/xcvrs/xcvr_io_55": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@6]", + "/run/devmap/xcvrs/xcvr_ctrl_55": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_55]", + "/run/devmap/xcvrs/xcvr_io_56": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@7]", + "/run/devmap/xcvrs/xcvr_ctrl_56": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_56]", + "/run/devmap/xcvrs/xcvr_io_57": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@0]", + "/run/devmap/xcvrs/xcvr_ctrl_57": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_57]", + "/run/devmap/xcvrs/xcvr_io_58": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@1]", + "/run/devmap/xcvrs/xcvr_ctrl_58": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_58]", + "/run/devmap/xcvrs/xcvr_io_59": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@2]", + "/run/devmap/xcvrs/xcvr_ctrl_59": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_59]", + "/run/devmap/xcvrs/xcvr_io_60": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@3]", + "/run/devmap/xcvrs/xcvr_ctrl_60": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_60]", + "/run/devmap/xcvrs/xcvr_io_61": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@4]", + "/run/devmap/xcvrs/xcvr_ctrl_61": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_61]", + "/run/devmap/xcvrs/xcvr_io_62": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@5]", + "/run/devmap/xcvrs/xcvr_ctrl_62": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_62]", + "/run/devmap/xcvrs/xcvr_io_63": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@6]", + "/run/devmap/xcvrs/xcvr_ctrl_63": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_63]", + "/run/devmap/xcvrs/xcvr_io_64": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@7]", + "/run/devmap/xcvrs/xcvr_ctrl_64": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_64]", + "/run/devmap/xcvrs/xcvr_io_65": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@2]", + "/run/devmap/xcvrs/xcvr_ctrl_65": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_65]", + "/run/devmap/xcvrs/xcvr_io_66": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@3]", + "/run/devmap/xcvrs/xcvr_ctrl_66": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_66]", + "/run/devmap/xcvrs/xcvr_io_67": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@4]", + "/run/devmap/xcvrs/xcvr_ctrl_67": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_67]", + "/run/devmap/xcvrs/xcvr_io_68": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@5]", + "/run/devmap/xcvrs/xcvr_ctrl_68": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_68]" + }, + "chassisEepromDevicePath": "/SMB_SLOT@0/[CHASSIS_EEPROM]", + "numXcvrs": 68, + "bspKmodsRpmName": "arista_bsp_kmods", + "bspKmodsRpmVersion": "0.7.17-1", + "requiredKmodsToLoad": [ + "spidev", + "i2c_i801", + "scd", + "ledtrig_timer" + ] +}