From 8bb0245d39e688c68b53050853355253115efa4f Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 13:38:10 -0800 Subject: [PATCH 01/16] Add dummy Trace.csv for j4sim --- .../l1lib/platform-csvs/j4sim/Trace.csv | 257 ++++++++++++++++++ 1 file changed, 257 insertions(+) create mode 100644 arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv diff --git a/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv b/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv new file mode 100644 index 0000000000000..fe0381a8525c4 --- /dev/null +++ b/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv @@ -0,0 +1,257 @@ +SystemComponentId,SystemSerdesId,LineComponentId,LineSerdesId,TraceLoss,ConnectionType,PolaritySwap +0,0,1,0,0,rx,No +0,0,1,0,0,tx,No +0,1,1,1,0,rx,No +0,1,1,1,0,tx,No +0,2,1,2,0,rx,No +0,2,1,2,0,tx,No +0,3,1,3,0,rx,No +0,3,1,3,0,tx,No +0,4,1,4,0,rx,No +0,4,1,4,0,tx,No +0,5,1,5,0,rx,No +0,5,1,5,0,tx,No +0,6,1,6,0,rx,No +0,6,1,6,0,tx,No +0,7,1,7,0,rx,No +0,7,1,7,0,tx,No +1,0,2,0,0,rx,No +1,0,2,0,0,tx,No +1,1,2,1,0,rx,No +1,1,2,1,0,tx,No +1,2,2,2,0,rx,No +1,2,2,2,0,tx,No +1,3,2,3,0,rx,No +1,3,2,3,0,tx,No +1,4,2,4,0,rx,No +1,4,2,4,0,tx,No +1,5,2,5,0,rx,No +1,5,2,5,0,tx,No +1,6,2,6,0,rx,No +1,6,2,6,0,tx,No +1,7,2,7,0,rx,No +1,7,2,7,0,tx,No +2,0,3,0,0,rx,No +2,0,3,0,0,tx,No +2,1,3,1,0,rx,No +2,1,3,1,0,tx,No +2,2,3,2,0,rx,No +2,2,3,2,0,tx,No +2,3,3,3,0,rx,No +2,3,3,3,0,tx,No +2,4,3,4,0,rx,No +2,4,3,4,0,tx,No +2,5,3,5,0,rx,No +2,5,3,5,0,tx,No +2,6,3,6,0,rx,No +2,6,3,6,0,tx,No +2,7,3,7,0,rx,No +2,7,3,7,0,tx,No +3,0,4,0,0,rx,No +3,0,4,0,0,tx,No +3,1,4,1,0,rx,No +3,1,4,1,0,tx,No +3,2,4,2,0,rx,No +3,2,4,2,0,tx,No +3,3,4,3,0,rx,No +3,3,4,3,0,tx,No +3,4,4,4,0,rx,No +3,4,4,4,0,tx,No +3,5,4,5,0,rx,No +3,5,4,5,0,tx,No +3,6,4,6,0,rx,No +3,6,4,6,0,tx,No +3,7,4,7,0,rx,No +3,7,4,7,0,tx,No +4,0,5,0,0,rx,No +4,0,5,0,0,tx,No +4,1,5,1,0,rx,No +4,1,5,1,0,tx,No +4,2,5,2,0,rx,No +4,2,5,2,0,tx,No +4,3,5,3,0,rx,No +4,3,5,3,0,tx,No +4,4,5,4,0,rx,No +4,4,5,4,0,tx,No +4,5,5,5,0,rx,No +4,5,5,5,0,tx,No +4,6,5,6,0,rx,No +4,6,5,6,0,tx,No +4,7,5,7,0,rx,No +4,7,5,7,0,tx,No +5,0,6,0,0,rx,No +5,0,6,0,0,tx,No +5,1,6,1,0,rx,No +5,1,6,1,0,tx,No +5,2,6,2,0,rx,No +5,2,6,2,0,tx,No +5,3,6,3,0,rx,No +5,3,6,3,0,tx,No +5,4,6,4,0,rx,No +5,4,6,4,0,tx,No +5,5,6,5,0,rx,No +5,5,6,5,0,tx,No +5,6,6,6,0,rx,No +5,6,6,6,0,tx,No +5,7,6,7,0,rx,No +5,7,6,7,0,tx,No +6,0,7,0,0,rx,No +6,0,7,0,0,tx,No +6,1,7,1,0,rx,No +6,1,7,1,0,tx,No +6,2,7,2,0,rx,No +6,2,7,2,0,tx,No +6,3,7,3,0,rx,No +6,3,7,3,0,tx,No +6,4,7,4,0,rx,No +6,4,7,4,0,tx,No +6,5,7,5,0,rx,No +6,5,7,5,0,tx,No +6,6,7,6,0,rx,No +6,6,7,6,0,tx,No +6,7,7,7,0,rx,No +6,7,7,7,0,tx,No +7,0,8,0,0,rx,No +7,0,8,0,0,tx,No +7,1,8,1,0,rx,No +7,1,8,1,0,tx,No +7,2,8,2,0,rx,No +7,2,8,2,0,tx,No +7,3,8,3,0,rx,No +7,3,8,3,0,tx,No +7,4,8,4,0,rx,No +7,4,8,4,0,tx,No +7,5,8,5,0,rx,No +7,5,8,5,0,tx,No +7,6,8,6,0,rx,No +7,6,8,6,0,tx,No +7,7,8,7,0,rx,No +7,7,8,7,0,tx,No +8,0,9,0,0,rx,No +8,0,9,0,0,tx,No +8,1,9,1,0,rx,No +8,1,9,1,0,tx,No +8,2,9,2,0,rx,No +8,2,9,2,0,tx,No +8,3,9,3,0,rx,No +8,3,9,3,0,tx,No +8,4,9,4,0,rx,No +8,4,9,4,0,tx,No +8,5,9,5,0,rx,No +8,5,9,5,0,tx,No +8,6,9,6,0,rx,No +8,6,9,6,0,tx,No +8,7,9,7,0,rx,No +8,7,9,7,0,tx,No +9,0,10,0,0,rx,No +9,0,10,0,0,tx,No +9,1,10,1,0,rx,No +9,1,10,1,0,tx,No +9,2,10,2,0,rx,No +9,2,10,2,0,tx,No +9,3,10,3,0,rx,No +9,3,10,3,0,tx,No +9,4,10,4,0,rx,No +9,4,10,4,0,tx,No +9,5,10,5,0,rx,No +9,5,10,5,0,tx,No +9,6,10,6,0,rx,No +9,6,10,6,0,tx,No +9,7,10,7,0,rx,No +9,7,10,7,0,tx,No +10,0,11,0,0,rx,No +10,0,11,0,0,tx,No +10,1,11,1,0,rx,No +10,1,11,1,0,tx,No +10,2,11,2,0,rx,No +10,2,11,2,0,tx,No +10,3,11,3,0,rx,No +10,3,11,3,0,tx,No +10,4,11,4,0,rx,No +10,4,11,4,0,tx,No +10,5,11,5,0,rx,No +10,5,11,5,0,tx,No +10,6,11,6,0,rx,No +10,6,11,6,0,tx,No +10,7,11,7,0,rx,No +10,7,11,7,0,tx,No +11,0,12,0,0,rx,No +11,0,12,0,0,tx,No +11,1,12,1,0,rx,No +11,1,12,1,0,tx,No +11,2,12,2,0,rx,No +11,2,12,2,0,tx,No +11,3,12,3,0,rx,No +11,3,12,3,0,tx,No +11,4,12,4,0,rx,No +11,4,12,4,0,tx,No +11,5,12,5,0,rx,No +11,5,12,5,0,tx,No +11,6,12,6,0,rx,No +11,6,12,6,0,tx,No +11,7,12,7,0,rx,No +11,7,12,7,0,tx,No +12,0,13,0,0,rx,No +12,0,13,0,0,tx,No +12,1,13,1,0,rx,No +12,1,13,1,0,tx,No +12,2,13,2,0,rx,No +12,2,13,2,0,tx,No +12,3,13,3,0,rx,No +12,3,13,3,0,tx,No +12,4,13,4,0,rx,No +12,4,13,4,0,tx,No +12,5,13,5,0,rx,No +12,5,13,5,0,tx,No +12,6,13,6,0,rx,No +12,6,13,6,0,tx,No +12,7,13,7,0,rx,No +12,7,13,7,0,tx,No +13,0,14,0,0,rx,No +13,0,14,0,0,tx,No +13,1,14,1,0,rx,No +13,1,14,1,0,tx,No +13,2,14,2,0,rx,No +13,2,14,2,0,tx,No +13,3,14,3,0,rx,No +13,3,14,3,0,tx,No +13,4,14,4,0,rx,No +13,4,14,4,0,tx,No +13,5,14,5,0,rx,No +13,5,14,5,0,tx,No +13,6,14,6,0,rx,No +13,6,14,6,0,tx,No +13,7,14,7,0,rx,No +13,7,14,7,0,tx,No +14,0,15,0,0,rx,No +14,0,15,0,0,tx,No +14,1,15,1,0,rx,No +14,1,15,1,0,tx,No +14,2,15,2,0,rx,No +14,2,15,2,0,tx,No +14,3,15,3,0,rx,No +14,3,15,3,0,tx,No +14,4,15,4,0,rx,No +14,4,15,4,0,tx,No +14,5,15,5,0,rx,No +14,5,15,5,0,tx,No +14,6,15,6,0,rx,No +14,6,15,6,0,tx,No +14,7,15,7,0,rx,No +14,7,15,7,0,tx,No +15,0,16,0,0,rx,No +15,0,16,0,0,tx,No +15,1,16,1,0,rx,No +15,1,16,1,0,tx,No +15,2,16,2,0,rx,No +15,2,16,2,0,tx,No +15,3,16,3,0,rx,No +15,3,16,3,0,tx,No +15,4,16,4,0,rx,No +15,4,16,4,0,tx,No +15,5,16,5,0,rx,No +15,5,16,5,0,tx,No +15,6,16,6,0,rx,No +15,6,16,6,0,tx,No +15,7,16,7,0,rx,No +15,7,16,7,0,tx,No From 6d37a773ebd95dbb5bc428f7b202be4738914122 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 14:31:47 -0800 Subject: [PATCH 02/16] Making some platform changes to get vendor mappings later --- .../l1lib/platform-csvs/j4sim/Trace.csv | 257 ------------------ .../test/verify_generated_files.py | 1 + 2 files changed, 1 insertion(+), 257 deletions(-) delete mode 100644 arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv diff --git a/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv b/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv deleted file mode 100644 index fe0381a8525c4..0000000000000 --- a/arista/util/configs-and-diagrams/l1lib/platform-csvs/j4sim/Trace.csv +++ /dev/null @@ -1,257 +0,0 @@ -SystemComponentId,SystemSerdesId,LineComponentId,LineSerdesId,TraceLoss,ConnectionType,PolaritySwap -0,0,1,0,0,rx,No -0,0,1,0,0,tx,No -0,1,1,1,0,rx,No -0,1,1,1,0,tx,No -0,2,1,2,0,rx,No -0,2,1,2,0,tx,No -0,3,1,3,0,rx,No -0,3,1,3,0,tx,No -0,4,1,4,0,rx,No -0,4,1,4,0,tx,No -0,5,1,5,0,rx,No -0,5,1,5,0,tx,No -0,6,1,6,0,rx,No -0,6,1,6,0,tx,No -0,7,1,7,0,rx,No -0,7,1,7,0,tx,No -1,0,2,0,0,rx,No -1,0,2,0,0,tx,No -1,1,2,1,0,rx,No -1,1,2,1,0,tx,No -1,2,2,2,0,rx,No -1,2,2,2,0,tx,No -1,3,2,3,0,rx,No -1,3,2,3,0,tx,No -1,4,2,4,0,rx,No -1,4,2,4,0,tx,No -1,5,2,5,0,rx,No -1,5,2,5,0,tx,No -1,6,2,6,0,rx,No -1,6,2,6,0,tx,No -1,7,2,7,0,rx,No -1,7,2,7,0,tx,No -2,0,3,0,0,rx,No -2,0,3,0,0,tx,No -2,1,3,1,0,rx,No -2,1,3,1,0,tx,No -2,2,3,2,0,rx,No -2,2,3,2,0,tx,No -2,3,3,3,0,rx,No -2,3,3,3,0,tx,No -2,4,3,4,0,rx,No -2,4,3,4,0,tx,No -2,5,3,5,0,rx,No -2,5,3,5,0,tx,No -2,6,3,6,0,rx,No -2,6,3,6,0,tx,No -2,7,3,7,0,rx,No -2,7,3,7,0,tx,No -3,0,4,0,0,rx,No -3,0,4,0,0,tx,No -3,1,4,1,0,rx,No -3,1,4,1,0,tx,No -3,2,4,2,0,rx,No -3,2,4,2,0,tx,No -3,3,4,3,0,rx,No -3,3,4,3,0,tx,No -3,4,4,4,0,rx,No -3,4,4,4,0,tx,No -3,5,4,5,0,rx,No -3,5,4,5,0,tx,No -3,6,4,6,0,rx,No -3,6,4,6,0,tx,No -3,7,4,7,0,rx,No -3,7,4,7,0,tx,No -4,0,5,0,0,rx,No -4,0,5,0,0,tx,No -4,1,5,1,0,rx,No -4,1,5,1,0,tx,No -4,2,5,2,0,rx,No -4,2,5,2,0,tx,No -4,3,5,3,0,rx,No -4,3,5,3,0,tx,No -4,4,5,4,0,rx,No -4,4,5,4,0,tx,No -4,5,5,5,0,rx,No -4,5,5,5,0,tx,No -4,6,5,6,0,rx,No -4,6,5,6,0,tx,No -4,7,5,7,0,rx,No -4,7,5,7,0,tx,No -5,0,6,0,0,rx,No -5,0,6,0,0,tx,No -5,1,6,1,0,rx,No -5,1,6,1,0,tx,No -5,2,6,2,0,rx,No -5,2,6,2,0,tx,No -5,3,6,3,0,rx,No -5,3,6,3,0,tx,No -5,4,6,4,0,rx,No -5,4,6,4,0,tx,No -5,5,6,5,0,rx,No -5,5,6,5,0,tx,No -5,6,6,6,0,rx,No -5,6,6,6,0,tx,No -5,7,6,7,0,rx,No -5,7,6,7,0,tx,No -6,0,7,0,0,rx,No -6,0,7,0,0,tx,No -6,1,7,1,0,rx,No -6,1,7,1,0,tx,No -6,2,7,2,0,rx,No -6,2,7,2,0,tx,No -6,3,7,3,0,rx,No -6,3,7,3,0,tx,No -6,4,7,4,0,rx,No -6,4,7,4,0,tx,No -6,5,7,5,0,rx,No -6,5,7,5,0,tx,No -6,6,7,6,0,rx,No -6,6,7,6,0,tx,No -6,7,7,7,0,rx,No -6,7,7,7,0,tx,No -7,0,8,0,0,rx,No -7,0,8,0,0,tx,No -7,1,8,1,0,rx,No -7,1,8,1,0,tx,No -7,2,8,2,0,rx,No -7,2,8,2,0,tx,No -7,3,8,3,0,rx,No -7,3,8,3,0,tx,No -7,4,8,4,0,rx,No -7,4,8,4,0,tx,No -7,5,8,5,0,rx,No -7,5,8,5,0,tx,No -7,6,8,6,0,rx,No -7,6,8,6,0,tx,No -7,7,8,7,0,rx,No -7,7,8,7,0,tx,No -8,0,9,0,0,rx,No -8,0,9,0,0,tx,No -8,1,9,1,0,rx,No -8,1,9,1,0,tx,No -8,2,9,2,0,rx,No -8,2,9,2,0,tx,No -8,3,9,3,0,rx,No -8,3,9,3,0,tx,No -8,4,9,4,0,rx,No -8,4,9,4,0,tx,No -8,5,9,5,0,rx,No -8,5,9,5,0,tx,No -8,6,9,6,0,rx,No -8,6,9,6,0,tx,No -8,7,9,7,0,rx,No -8,7,9,7,0,tx,No -9,0,10,0,0,rx,No -9,0,10,0,0,tx,No -9,1,10,1,0,rx,No -9,1,10,1,0,tx,No -9,2,10,2,0,rx,No -9,2,10,2,0,tx,No -9,3,10,3,0,rx,No -9,3,10,3,0,tx,No -9,4,10,4,0,rx,No -9,4,10,4,0,tx,No -9,5,10,5,0,rx,No -9,5,10,5,0,tx,No -9,6,10,6,0,rx,No -9,6,10,6,0,tx,No -9,7,10,7,0,rx,No -9,7,10,7,0,tx,No -10,0,11,0,0,rx,No -10,0,11,0,0,tx,No -10,1,11,1,0,rx,No -10,1,11,1,0,tx,No -10,2,11,2,0,rx,No -10,2,11,2,0,tx,No -10,3,11,3,0,rx,No -10,3,11,3,0,tx,No -10,4,11,4,0,rx,No -10,4,11,4,0,tx,No -10,5,11,5,0,rx,No -10,5,11,5,0,tx,No -10,6,11,6,0,rx,No -10,6,11,6,0,tx,No -10,7,11,7,0,rx,No -10,7,11,7,0,tx,No -11,0,12,0,0,rx,No -11,0,12,0,0,tx,No -11,1,12,1,0,rx,No -11,1,12,1,0,tx,No -11,2,12,2,0,rx,No -11,2,12,2,0,tx,No -11,3,12,3,0,rx,No -11,3,12,3,0,tx,No -11,4,12,4,0,rx,No -11,4,12,4,0,tx,No -11,5,12,5,0,rx,No -11,5,12,5,0,tx,No -11,6,12,6,0,rx,No -11,6,12,6,0,tx,No -11,7,12,7,0,rx,No -11,7,12,7,0,tx,No -12,0,13,0,0,rx,No -12,0,13,0,0,tx,No -12,1,13,1,0,rx,No -12,1,13,1,0,tx,No -12,2,13,2,0,rx,No -12,2,13,2,0,tx,No -12,3,13,3,0,rx,No -12,3,13,3,0,tx,No -12,4,13,4,0,rx,No -12,4,13,4,0,tx,No -12,5,13,5,0,rx,No -12,5,13,5,0,tx,No -12,6,13,6,0,rx,No -12,6,13,6,0,tx,No -12,7,13,7,0,rx,No -12,7,13,7,0,tx,No -13,0,14,0,0,rx,No -13,0,14,0,0,tx,No -13,1,14,1,0,rx,No -13,1,14,1,0,tx,No -13,2,14,2,0,rx,No -13,2,14,2,0,tx,No -13,3,14,3,0,rx,No -13,3,14,3,0,tx,No -13,4,14,4,0,rx,No -13,4,14,4,0,tx,No -13,5,14,5,0,rx,No -13,5,14,5,0,tx,No -13,6,14,6,0,rx,No -13,6,14,6,0,tx,No -13,7,14,7,0,rx,No -13,7,14,7,0,tx,No -14,0,15,0,0,rx,No -14,0,15,0,0,tx,No -14,1,15,1,0,rx,No -14,1,15,1,0,tx,No -14,2,15,2,0,rx,No -14,2,15,2,0,tx,No -14,3,15,3,0,rx,No -14,3,15,3,0,tx,No -14,4,15,4,0,rx,No -14,4,15,4,0,tx,No -14,5,15,5,0,rx,No -14,5,15,5,0,tx,No -14,6,15,6,0,rx,No -14,6,15,6,0,tx,No -14,7,15,7,0,rx,No -14,7,15,7,0,tx,No -15,0,16,0,0,rx,No -15,0,16,0,0,tx,No -15,1,16,1,0,rx,No -15,1,16,1,0,tx,No -15,2,16,2,0,rx,No -15,2,16,2,0,tx,No -15,3,16,3,0,rx,No -15,3,16,3,0,tx,No -15,4,16,4,0,rx,No -15,4,16,4,0,tx,No -15,5,16,5,0,rx,No -15,5,16,5,0,tx,No -15,6,16,6,0,rx,No -15,6,16,6,0,tx,No -15,7,16,7,0,rx,No -15,7,16,7,0,tx,No diff --git a/fboss/lib/platform_mapping_v2/test/verify_generated_files.py b/fboss/lib/platform_mapping_v2/test/verify_generated_files.py index c7a315e6d536c..7675e639588a1 100644 --- a/fboss/lib/platform_mapping_v2/test/verify_generated_files.py +++ b/fboss/lib/platform_mapping_v2/test/verify_generated_files.py @@ -47,6 +47,7 @@ class TestVerifyPlatformMappingGeneratedFiles(unittest.TestCase): "tahansb800bc", "wedge800bact", "wedge800cact", + "j4sim", ], True: [ "meru800bfa", From 4b11e73b83c7fdb27bcf37b2704a98dc3800bbf7 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 14:36:29 -0800 Subject: [PATCH 03/16] Generated vendor mappings --- .../j4sim/j4sim_port_profile_mapping.csv | 129 ++++++++++++++++++ .../j4sim/j4sim_profile_settings.csv | 15 ++ .../platforms/j4sim/j4sim_si_settings.csv | 1 + .../platforms/j4sim/j4sim_static_mapping.csv | 129 ++++++++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv create mode 100644 fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv create mode 100644 fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv create mode 100644 fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv new file mode 100644 index 0000000000000..846ee56c8080b --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv @@ -0,0 +1,129 @@ +Global_PortID,Logical_PortID,Port_Name,Supported_Port_Profiles,Attached_CoreID,Attached_Core_PortID,Virtual_Device_ID,Port_Type,Scope +1,1,eth1/1/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/1/2,56-47-49-43,,,,0,0 +3,3,eth1/1/3,54-56-47-49-43,,,,0,0 +4,4,eth1/1/4,56-47-49-43,,,,0,0 +5,5,eth1/1/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/1/6,56-47-49-43,,,,0,0 +7,7,eth1/1/7,54-56-47-49-43,,,,0,0 +8,8,eth1/1/8,56-47-49-43,,,,0,0 +1,1,eth1/2/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/2/2,56-47-49-43,,,,0,0 +3,3,eth1/2/3,54-56-47-49-43,,,,0,0 +4,4,eth1/2/4,56-47-49-43,,,,0,0 +5,5,eth1/2/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/2/6,56-47-49-43,,,,0,0 +7,7,eth1/2/7,54-56-47-49-43,,,,0,0 +8,8,eth1/2/8,56-47-49-43,,,,0,0 +1,1,eth1/3/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/3/2,56-47-49-43,,,,0,0 +3,3,eth1/3/3,54-56-47-49-43,,,,0,0 +4,4,eth1/3/4,56-47-49-43,,,,0,0 +5,5,eth1/3/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/3/6,56-47-49-43,,,,0,0 +7,7,eth1/3/7,54-56-47-49-43,,,,0,0 +8,8,eth1/3/8,56-47-49-43,,,,0,0 +1,1,eth1/4/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/4/2,56-47-49-43,,,,0,0 +3,3,eth1/4/3,54-56-47-49-43,,,,0,0 +4,4,eth1/4/4,56-47-49-43,,,,0,0 +5,5,eth1/4/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/4/6,56-47-49-43,,,,0,0 +7,7,eth1/4/7,54-56-47-49-43,,,,0,0 +8,8,eth1/4/8,56-47-49-43,,,,0,0 +1,1,eth1/5/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/5/2,56-47-49-43,,,,0,0 +3,3,eth1/5/3,54-56-47-49-43,,,,0,0 +4,4,eth1/5/4,56-47-49-43,,,,0,0 +5,5,eth1/5/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/5/6,56-47-49-43,,,,0,0 +7,7,eth1/5/7,54-56-47-49-43,,,,0,0 +8,8,eth1/5/8,56-47-49-43,,,,0,0 +1,1,eth1/6/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/6/2,56-47-49-43,,,,0,0 +3,3,eth1/6/3,54-56-47-49-43,,,,0,0 +4,4,eth1/6/4,56-47-49-43,,,,0,0 +5,5,eth1/6/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/6/6,56-47-49-43,,,,0,0 +7,7,eth1/6/7,54-56-47-49-43,,,,0,0 +8,8,eth1/6/8,56-47-49-43,,,,0,0 +1,1,eth1/7/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/7/2,56-47-49-43,,,,0,0 +3,3,eth1/7/3,54-56-47-49-43,,,,0,0 +4,4,eth1/7/4,56-47-49-43,,,,0,0 +5,5,eth1/7/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/7/6,56-47-49-43,,,,0,0 +7,7,eth1/7/7,54-56-47-49-43,,,,0,0 +8,8,eth1/7/8,56-47-49-43,,,,0,0 +1,1,eth1/8/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/8/2,56-47-49-43,,,,0,0 +3,3,eth1/8/3,54-56-47-49-43,,,,0,0 +4,4,eth1/8/4,56-47-49-43,,,,0,0 +5,5,eth1/8/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/8/6,56-47-49-43,,,,0,0 +7,7,eth1/8/7,54-56-47-49-43,,,,0,0 +8,8,eth1/8/8,56-47-49-43,,,,0,0 +1,1,eth1/9/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/9/2,56-47-49-43,,,,0,0 +3,3,eth1/9/3,54-56-47-49-43,,,,0,0 +4,4,eth1/9/4,56-47-49-43,,,,0,0 +5,5,eth1/9/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/9/6,56-47-49-43,,,,0,0 +7,7,eth1/9/7,54-56-47-49-43,,,,0,0 +8,8,eth1/9/8,56-47-49-43,,,,0,0 +1,1,eth1/10/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/10/2,56-47-49-43,,,,0,0 +3,3,eth1/10/3,54-56-47-49-43,,,,0,0 +4,4,eth1/10/4,56-47-49-43,,,,0,0 +5,5,eth1/10/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/10/6,56-47-49-43,,,,0,0 +7,7,eth1/10/7,54-56-47-49-43,,,,0,0 +8,8,eth1/10/8,56-47-49-43,,,,0,0 +1,1,eth1/11/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/11/2,56-47-49-43,,,,0,0 +3,3,eth1/11/3,54-56-47-49-43,,,,0,0 +4,4,eth1/11/4,56-47-49-43,,,,0,0 +5,5,eth1/11/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/11/6,56-47-49-43,,,,0,0 +7,7,eth1/11/7,54-56-47-49-43,,,,0,0 +8,8,eth1/11/8,56-47-49-43,,,,0,0 +1,1,eth1/12/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/12/2,56-47-49-43,,,,0,0 +3,3,eth1/12/3,54-56-47-49-43,,,,0,0 +4,4,eth1/12/4,56-47-49-43,,,,0,0 +5,5,eth1/12/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/12/6,56-47-49-43,,,,0,0 +7,7,eth1/12/7,54-56-47-49-43,,,,0,0 +8,8,eth1/12/8,56-47-49-43,,,,0,0 +1,1,eth1/13/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/13/2,56-47-49-43,,,,0,0 +3,3,eth1/13/3,54-56-47-49-43,,,,0,0 +4,4,eth1/13/4,56-47-49-43,,,,0,0 +5,5,eth1/13/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/13/6,56-47-49-43,,,,0,0 +7,7,eth1/13/7,54-56-47-49-43,,,,0,0 +8,8,eth1/13/8,56-47-49-43,,,,0,0 +1,1,eth1/14/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/14/2,56-47-49-43,,,,0,0 +3,3,eth1/14/3,54-56-47-49-43,,,,0,0 +4,4,eth1/14/4,56-47-49-43,,,,0,0 +5,5,eth1/14/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/14/6,56-47-49-43,,,,0,0 +7,7,eth1/14/7,54-56-47-49-43,,,,0,0 +8,8,eth1/14/8,56-47-49-43,,,,0,0 +1,1,eth1/15/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/15/2,56-47-49-43,,,,0,0 +3,3,eth1/15/3,54-56-47-49-43,,,,0,0 +4,4,eth1/15/4,56-47-49-43,,,,0,0 +5,5,eth1/15/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/15/6,56-47-49-43,,,,0,0 +7,7,eth1/15/7,54-56-47-49-43,,,,0,0 +8,8,eth1/15/8,56-47-49-43,,,,0,0 +1,1,eth1/16/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +2,2,eth1/16/2,56-47-49-43,,,,0,0 +3,3,eth1/16/3,54-56-47-49-43,,,,0,0 +4,4,eth1/16/4,56-47-49-43,,,,0,0 +5,5,eth1/16/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 +6,6,eth1/16/6,56-47-49-43,,,,0,0 +7,7,eth1/16/7,54-56-47-49-43,,,,0,0 +8,8,eth1/16/8,56-47-49-43,,,,0,0 diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv new file mode 100644 index 0000000000000..d146eb222eecb --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv @@ -0,0 +1,15 @@ +Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type +100000,NPU,TRANSCEIVER,1,PAM4,RS544,OPTICAL,SR, +100000,NPU,TRANSCEIVER,1,PAM4,NONE,COPPER,CR, +100000,NPU,TRANSCEIVER,1,PAM4,RS544,COPPER,CR, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,COPPER,CR4, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,OPTICAL,SR4, +200000,NPU,TRANSCEIVER,2,PAM4,RS544,COPPER,CR2, +200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,COPPER,CR4, +200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,OPTICAL,SR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,OPTICAL,SR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,COPPER,CR4, +400000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,COPPER,CR8, +50000,NPU,TRANSCEIVER,1,PAM4,RS544,COPPER,CR, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,OPTICAL,SR8, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,COPPER,CR8, diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv new file mode 100644 index 0000000000000..22e73c1e8cfb0 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_si_settings.csv @@ -0,0 +1 @@ +SLOT_ID,CHIP_ID,CHIP_TYPE,CORE_ID,CORE_TYPE,CORE_LANE,LANE_SPEED(mbps),MEDIA_TYPE,TCVR_VENDOR,TCVR_PART_NUM,TCVR_MEDIA,NIC_VENDOR,CABLE_LENGTH(m),TX_PRE3,TX_PRE2,TX_PRE1,TX_MAIN,TX_POST1,TX_POST2,TX_POST3,RX_CTLE_CODE,RX_DSP_MODE,RX_AFE_TRIM diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv new file mode 100644 index 0000000000000..287ba3edf0df7 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv @@ -0,0 +1,129 @@ +A_SLOT_ID,A_CHIP_ID,A_CHIP_TYPE,A_CORE_ID,A_CORE_TYPE,A_CORE_LANE,A_PHYSICAL_TX_LANE,A_PHYSICAL_RX_LANE,A_TX_POLARITY_SWAP,A_RX_POLARITY_SWAP,Z_SLOT_ID,Z_CHIP_ID,Z_CHIP_TYPE,Z_CORE_ID,Z_CORE_TYPE,Z_CORE_LANE,Z_PHYSICAL_TX_LANE,Z_PHYSICAL_RX_LANE,Z_TX_POLARITY_SWAP,Z_RX_POLARITY_SWAP +1,1,NPU,0,J4SIM_NIF,0,0,0,N,N,1,1,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,0,J4SIM_NIF,1,1,1,N,N,1,1,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,0,J4SIM_NIF,2,2,2,N,N,1,1,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,1,NPU,0,J4SIM_NIF,3,3,3,N,N,1,1,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,1,NPU,0,J4SIM_NIF,4,4,4,N,N,1,1,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,1,NPU,0,J4SIM_NIF,5,5,5,N,N,1,1,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,1,NPU,0,J4SIM_NIF,6,6,6,N,N,1,1,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,1,NPU,0,J4SIM_NIF,7,7,7,N,N,1,1,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,2,NPU,0,J4SIM_NIF,0,0,0,N,N,1,2,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,2,NPU,0,J4SIM_NIF,1,1,1,N,N,1,2,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,2,NPU,0,J4SIM_NIF,2,2,2,N,N,1,2,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,2,NPU,0,J4SIM_NIF,3,3,3,N,N,1,2,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,2,NPU,0,J4SIM_NIF,4,4,4,N,N,1,2,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,2,NPU,0,J4SIM_NIF,5,5,5,N,N,1,2,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,2,NPU,0,J4SIM_NIF,6,6,6,N,N,1,2,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,2,NPU,0,J4SIM_NIF,7,7,7,N,N,1,2,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,3,NPU,0,J4SIM_NIF,0,0,0,N,N,1,3,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,3,NPU,0,J4SIM_NIF,1,1,1,N,N,1,3,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,3,NPU,0,J4SIM_NIF,2,2,2,N,N,1,3,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,3,NPU,0,J4SIM_NIF,3,3,3,N,N,1,3,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,3,NPU,0,J4SIM_NIF,4,4,4,N,N,1,3,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,3,NPU,0,J4SIM_NIF,5,5,5,N,N,1,3,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,3,NPU,0,J4SIM_NIF,6,6,6,N,N,1,3,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,3,NPU,0,J4SIM_NIF,7,7,7,N,N,1,3,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,4,NPU,0,J4SIM_NIF,0,0,0,N,N,1,4,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,4,NPU,0,J4SIM_NIF,1,1,1,N,N,1,4,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,4,NPU,0,J4SIM_NIF,2,2,2,N,N,1,4,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,4,NPU,0,J4SIM_NIF,3,3,3,N,N,1,4,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,4,NPU,0,J4SIM_NIF,4,4,4,N,N,1,4,TRANSCEIVER,0,OSFP,4,4,4,N,N +1,4,NPU,0,J4SIM_NIF,5,5,5,N,N,1,4,TRANSCEIVER,0,OSFP,5,5,5,N,N +1,4,NPU,0,J4SIM_NIF,6,6,6,N,N,1,4,TRANSCEIVER,0,OSFP,6,6,6,N,N +1,4,NPU,0,J4SIM_NIF,7,7,7,N,N,1,4,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,5,NPU,0,J4SIM_NIF,0,0,0,N,N,1,5,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,5,NPU,0,J4SIM_NIF,1,1,1,N,N,1,5,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,5,NPU,0,J4SIM_NIF,2,2,2,N,N,1,5,TRANSCEIVER,0,OSFP,2,2,2,N,N +1,5,NPU,0,J4SIM_NIF,3,3,3,N,N,1,5,TRANSCEIVER,0,OSFP,3,3,3,N,N +1,5,NPU,0,J4SIM_NIF,4,4,4,N,N,1,5,TRANSCEIVER,0,OSFP,4,4,4,N,N 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+1,16,NPU,0,J4SIM_NIF,7,7,7,N,N,1,16,TRANSCEIVER,0,OSFP,7,7,7,N,N From 8cdd595f99aaecd447b46213a4912019add4bba9 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 15:21:33 -0800 Subject: [PATCH 04/16] Platform mapping changes following PR1496, needs creation still --- cmake/Agent.cmake | 1 + cmake/AgentPlatformsCommon.cmake | 1 + cmake/AgentPlatformsCommonJ4Sim.cmake | 12 ++++ cmake/AgentPlatformsSai.cmake | 3 + fboss/agent/platforms/common/BUCK | 1 + .../platforms/common/PlatformMappingUtils.cpp | 5 ++ fboss/agent/platforms/common/j4sim/BUCK | 16 +++++ .../common/j4sim/J4SimPlatformMapping.cpp | 21 ++++++ .../common/j4sim/J4SimPlatformMapping.h | 26 +++++++ .../platforms/sai/SaiBcmJ4SimPlatform.cpp | 72 +++++++++++++++++++ .../agent/platforms/sai/SaiBcmJ4SimPlatform.h | 70 ++++++++++++++++++ .../platforms/sai/SaiBcmJ4SimPlatformPort.cpp | 20 ++++++ .../platforms/sai/SaiBcmJ4SimPlatformPort.h | 27 +++++++ fboss/agent/platforms/sai/SaiPlatform.cpp | 3 + fboss/agent/platforms/sai/SaiPlatformInit.cpp | 4 ++ fboss/lib/if/fboss_common.thrift | 1 + .../platform_mapping_config.thrift | 1 + .../platforms/j4sim/j4sim_vendor_config.json | 22 ++++++ fboss/lib/platforms/PlatformMode.h | 2 + fboss/lib/platforms/PlatformProductInfo.cpp | 4 ++ 20 files changed, 312 insertions(+) create mode 100644 cmake/AgentPlatformsCommonJ4Sim.cmake create mode 100644 fboss/agent/platforms/common/j4sim/BUCK create mode 100644 fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp create mode 100644 fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h create mode 100644 fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp create mode 100644 fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h create mode 100644 fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp create mode 100644 fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h create mode 100644 fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json diff --git a/cmake/Agent.cmake b/cmake/Agent.cmake index 75c33f3e43cd6..1dee951aa63bb 100644 --- a/cmake/Agent.cmake +++ b/cmake/Agent.cmake @@ -162,6 +162,7 @@ target_link_libraries(utils meru800bia_platform_mapping meru800bfa_platform_mapping janga800bic_platform_mapping + j4sim_platform_mapping icecube800banw_platform_mapping icecube800bc_platform_mapping icetea800bc_platform_mapping diff --git a/cmake/AgentPlatformsCommon.cmake b/cmake/AgentPlatformsCommon.cmake index d3e3c50a0d246..b14f66a83208a 100644 --- a/cmake/AgentPlatformsCommon.cmake +++ b/cmake/AgentPlatformsCommon.cmake @@ -56,6 +56,7 @@ target_link_libraries(platform_mapping_utils ladakh800bcls_platform_mapping minipack3bta_platform_mapping icecube800banw_platform_mapping + j4sim_platform_mapping platform_mode ${RE2} ) diff --git a/cmake/AgentPlatformsCommonJ4Sim.cmake b/cmake/AgentPlatformsCommonJ4Sim.cmake new file mode 100644 index 0000000000000..4c8932655e804 --- /dev/null +++ b/cmake/AgentPlatformsCommonJ4Sim.cmake @@ -0,0 +1,12 @@ +# CMake to build libraries and binaries in fboss/agent/platforms/common/j4sim + +# In general, libraries and binaries in fboss/foo/bar are built by +# cmake/FooBar.cmake + +add_library(j4sim_platform_mapping + fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +) + +target_link_libraries(j4sim_platform_mapping + platform_mapping +) diff --git a/cmake/AgentPlatformsSai.cmake b/cmake/AgentPlatformsSai.cmake index 2d6424595ea0c..3190d2b68cde3 100644 --- a/cmake/AgentPlatformsSai.cmake +++ b/cmake/AgentPlatformsSai.cmake @@ -58,6 +58,8 @@ set(SAI_PLATFORM_SRC fboss/agent/platforms/sai/SaiYangraPlatformPort.cpp fboss/agent/platforms/sai/SaiMinipack3NPlatformPort.cpp # platform oss srcs (== fake_srcs) + fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp + fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp fboss/agent/platforms/sai/oss/SaiBcmMinipackPlatform.cpp fboss/agent/platforms/sai/oss/SaiBcmPlatform.cpp fboss/agent/platforms/sai/oss/SaiBcmMinipackPlatformPort.cpp @@ -131,6 +133,7 @@ target_link_libraries(sai_platform icecube800banw_platform_mapping icecube800bc_platform_mapping icetea800bc_platform_mapping + j4sim_platform_mapping led_structs_types_cpp2 led_mapping_cpp2 wedge800bact_platform_mapping diff --git a/fboss/agent/platforms/common/BUCK b/fboss/agent/platforms/common/BUCK index f276e13891feb..041ab6aef37fd 100644 --- a/fboss/agent/platforms/common/BUCK +++ b/fboss/agent/platforms/common/BUCK @@ -34,6 +34,7 @@ cpp_library( exported_deps = [ ":platform_mapping", "//fboss/agent:fboss-error", + "//fboss/agent/platforms/common/j4sim:j4sim_platform_mapping", "//fboss/agent/platforms/common/darwin:darwin_platform_mapping", "//fboss/agent/platforms/common/elbert:elbert_platform_mapping", "//fboss/agent/platforms/common/fake_test:fake_test_platform_mapping", diff --git a/fboss/agent/platforms/common/PlatformMappingUtils.cpp b/fboss/agent/platforms/common/PlatformMappingUtils.cpp index a8eade0a1ef65..7b396bf14ec70 100644 --- a/fboss/agent/platforms/common/PlatformMappingUtils.cpp +++ b/fboss/agent/platforms/common/PlatformMappingUtils.cpp @@ -23,6 +23,7 @@ #include "fboss/agent/platforms/common/icecube800banw/Icecube800banwPlatformMapping.h" #include "fboss/agent/platforms/common/icecube800bc/Icecube800bcPlatformMapping.h" #include "fboss/agent/platforms/common/icetea800bc/Icetea800bcPlatformMapping.h" +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" #include "fboss/agent/platforms/common/janga800bic/Janga800bicPlatformMapping.h" #include "fboss/agent/platforms/common/ladakh800bcls/Ladakh800bclsPlatformMapping.h" #include "fboss/agent/platforms/common/meru400bfu/Meru400bfuPlatformMapping.h" @@ -219,6 +220,10 @@ std::unique_ptr initPlatformMapping(PlatformType type) { return platformMappingStr.empty() ? std::make_unique() : std::make_unique(platformMappingStr); + case PlatformType::PLATFORM_J4SIM: + return platformMappingStr.empty() + ? std::make_unique() + : std::make_unique(platformMappingStr); case PlatformType::PLATFORM_FAKE_SAI: { std::vector controllingPorts = getFakeSaiControllingPortIDs(); return std::make_unique(controllingPorts); diff --git a/fboss/agent/platforms/common/j4sim/BUCK b/fboss/agent/platforms/common/j4sim/BUCK new file mode 100644 index 0000000000000..9882f6cca57a6 --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/BUCK @@ -0,0 +1,16 @@ +load("@fbcode_macros//build_defs:cpp_library.bzl", "cpp_library") + +oncall("fboss_agent_push") + +cpp_library( + name = "j4sim_platform_mapping", + srcs = [ + "J4SimPlatformMapping.cpp", + ], + headers = [ + "J4SimPlatformMapping.h", + ], + exported_deps = [ + "//fboss/agent/platforms/common:platform_mapping", + ], +) diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp new file mode 100644 index 0000000000000..dc3a73cafaacb --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ + +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" + +namespace facebook::fboss { + +J4SimPlatformMapping::J4SimPlatformMapping() : PlatformMapping() {} + +J4SimPlatformMapping::J4SimPlatformMapping( + const std::string& platformMappingStr) + : PlatformMapping(platformMappingStr) {} + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h new file mode 100644 index 0000000000000..69a404c5f7452 --- /dev/null +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/common/PlatformMapping.h" + +namespace facebook::fboss { + +class J4SimPlatformMapping : public PlatformMapping { + public: + J4SimPlatformMapping(); + explicit J4SimPlatformMapping(const std::string& platformMappingStr); + + private: + // Forbidden copy constructor and assignment operator + J4SimPlatformMapping(J4SimPlatformMapping const&) = delete; + J4SimPlatformMapping& operator=(J4SimPlatformMapping const&) = delete; +}; +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp new file mode 100644 index 0000000000000..78c057daf53ba --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ + +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h" + +#include "fboss/agent/hw/switch_asics/Q4DAsic.h" +#include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" + +namespace { +constexpr auto kCpuPortSpeed = 10000; +constexpr auto kSingleStageCpuPortNumVoqs = 8; +constexpr auto kDualStageCpuPortNumVoqs = 3; +} // namespace + +namespace facebook::fboss { + +SaiBcmJ4SimPlatform::SaiBcmJ4SimPlatform( + std::unique_ptr productInfo, + folly::MacAddress localMac, + const std::string& platformMappingStr) + : SaiBcmPlatform( + std::move(productInfo), + platformMappingStr.empty() + ? std::make_unique() + : std::make_unique(platformMappingStr), + localMac) {} + +void SaiBcmJ4SimPlatform::setupAsic( + std::optional switchId, + const cfg::SwitchInfo& switchInfo, + std::optional fabricNodeRole) { + CHECK(!fabricNodeRole.has_value()); + asic_ = std::make_unique(switchId, switchInfo); +} + +HwAsic* SaiBcmJ4SimPlatform::getAsic() const { + return asic_.get(); +} + +std::vector +SaiBcmJ4SimPlatform::getInternalSystemPortConfig() const { + CHECK(asic_) << " Asic must be set before getting sys port info"; + CHECK(asic_->getSwitchId()) << " Switch Id must be set before sys port info"; + + const uint32_t switchId = static_cast(*asic_->getSwitchId()); + const uint32_t speed = kCpuPortSpeed; + const uint32_t numVoqs = isDualStage3Q2QMode() ? kDualStageCpuPortNumVoqs + : kSingleStageCpuPortNumVoqs; + auto cpuPortsCoreAndPortIdx = + getPlatformMapping()->getCpuPortsCoreAndPortIdx(); + + CHECK( + cpuPortsCoreAndPortIdx.size() == 1 || cpuPortsCoreAndPortIdx.size() == 4) + << "Create one CPU port for the ASIC or one CPU port for each core"; + + std::vector sysPortConfig; + for (auto [cpuPortID, coreAndPortIdx] : cpuPortsCoreAndPortIdx) { + auto [core, port] = coreAndPortIdx; + sysPortConfig.push_back({cpuPortID, switchId, core, port, speed, numVoqs}); + } + return sysPortConfig; +} +SaiBcmJ4SimPlatform::~SaiBcmJ4SimPlatform() = default; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h new file mode 100644 index 0000000000000..89deeeeac25fc --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/sai/SaiBcmPlatform.h" + +namespace facebook::fboss { + +class Q4DAsic; + +class SaiBcmJ4SimPlatform : public SaiBcmPlatform { + public: + SaiBcmJ4SimPlatform( + std::unique_ptr productInfo, + folly::MacAddress localMac, + const std::string& platformMappingStr); + ~SaiBcmJ4SimPlatform() override; + HwAsic* getAsic() const override; + + uint32_t numLanesPerCore() const override { + return 8; + } + + uint32_t numCellsAvailable() const override { + return 130665; + } + + bool isSerdesApiSupported() const override { + return true; + } + + void initLEDs() override {} + + std::vector getAllPortsInGroup(PortID /*portID*/) const override { + return {}; + } + + std::vector getSupportedFlexPortModes() const override { + return {}; + } + + bool supportInterfaceType() const override { + return true; + } + + std::optional getInterfaceType( + TransmitterTechnology /*transmitterTech*/, + cfg::PortSpeed /*speed*/) const override { + return std::nullopt; + } + std::vector getInternalSystemPortConfig() + const override; + + private: + void setupAsic( + std::optional switchId, + const cfg::SwitchInfo& switchInfo, + std::optional fabricNodeRole) override; + + std::unique_ptr asic_; +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp new file mode 100644 index 0000000000000..e9ad9bde82d6c --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.cpp @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h" + +namespace facebook::fboss { + +void SaiBcmJ4SimPlatformPort::linkStatusChanged( + bool /* up */, + bool /* adminUp */) {} + +void SaiBcmJ4SimPlatformPort::externalState(PortLedExternalState /*lfs*/) {} + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h new file mode 100644 index 0000000000000..27bba97d9294d --- /dev/null +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2004-present, Facebook, Inc. + * All rights reserved. + * + * This source code is licensed under the BSD-style license found in the + * LICENSE file in the root directory of this source tree. An additional grant + * of patent rights can be found in the PATENTS file in the same directory. + * + */ +#pragma once + +#include "fboss/agent/platforms/sai/SaiBcmPlatformPort.h" + +namespace facebook::fboss { + +class SaiBcmJ4SimPlatformPort : public SaiBcmPlatformPort { + public: + SaiBcmJ4SimPlatformPort(PortID id, SaiPlatform* platform) + : SaiBcmPlatformPort(id, platform) {} + void linkStatusChanged(bool up, bool adminUp) override; + void externalState(PortLedExternalState lfs) override; + + private: + uint32_t currentLedState_{0}; +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiPlatform.cpp b/fboss/agent/platforms/sai/SaiPlatform.cpp index b0e0ba95d1352..7014fac32e4c5 100644 --- a/fboss/agent/platforms/sai/SaiPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiPlatform.cpp @@ -23,6 +23,7 @@ #include "fboss/agent/platforms/sai/SaiBcmIcecube800banwPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmIcecube800bcPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmIcetea800bcPlatformPort.h" +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmLadakh800bclsPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmMinipack3BTAPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmMinipackPlatformPort.h" @@ -420,6 +421,8 @@ void SaiPlatform::initPorts() { saiPort = std::make_unique(portId, this); } else if (platformMode == PlatformType::PLATFORM_TAHANSB800BC) { saiPort = std::make_unique(portId, this); + } else if (platformMode == PlatformType::PLATFORM_J4SIM) { + saiPort = std::make_unique(portId, this); } else if (platformMode == PlatformType::PLATFORM_ICECUBE800BANW) { saiPort = std::make_unique(portId, this); diff --git a/fboss/agent/platforms/sai/SaiPlatformInit.cpp b/fboss/agent/platforms/sai/SaiPlatformInit.cpp index 1a8f20c2a8b54..2e5570cf5a34f 100644 --- a/fboss/agent/platforms/sai/SaiPlatformInit.cpp +++ b/fboss/agent/platforms/sai/SaiPlatformInit.cpp @@ -21,6 +21,7 @@ #include "fboss/agent/platforms/sai/SaiBcmIcecube800banwPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmIcecube800bcPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmIcetea800bcPlatform.h" +#include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmLadakh800bclsPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmMinipack3BTAPlatform.h" #include "fboss/agent/platforms/sai/SaiBcmMinipackPlatform.h" @@ -142,6 +143,9 @@ std::unique_ptr chooseSaiPlatform( } else if (productInfo->getType() == PlatformType::PLATFORM_TAHANSB800BC) { return std::make_unique( std::move(productInfo), localMac, platformMappingStr); + } else if (productInfo->getType() == PlatformType::PLATFORM_J4SIM) { + return std::make_unique( + std::move(productInfo), localMac, platformMappingStr); } else if (productInfo->getType() == PlatformType::PLATFORM_FAKE_SAI) { return std::make_unique(std::move(productInfo)); } diff --git a/fboss/lib/if/fboss_common.thrift b/fboss/lib/if/fboss_common.thrift index 9a5cbf5509ec3..10189c83ab593 100644 --- a/fboss/lib/if/fboss_common.thrift +++ b/fboss/lib/if/fboss_common.thrift @@ -58,6 +58,7 @@ enum PlatformType { PLATFORM_LADAKH800BCLS = 45, PLATFORM_MINIPACK3BTA = 46, PLATFORM_ICECUBE800BANW = 47, + PLATFORM_J4SIM = 48, # Placeholder for unknown platform type PLATFORM_UNKNOWN = 1000, } diff --git a/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift b/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift index e97a65d4ede66..0fb848cd8bfd0 100644 --- a/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift +++ b/fboss/lib/platform_mapping_v2/platform_mapping_config.thrift @@ -34,6 +34,7 @@ enum CoreType { J3_EVT = 7, // J3 Eventor Port CHENAB_NIF = 8, TH6_NIF = 9, // TH6 + J4SIM_NIF = 11, // J4Sim // Transceivers OSFP = 100, diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json new file mode 100644 index 0000000000000..e1a2b5762eaf0 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_vendor_config.json @@ -0,0 +1,22 @@ +{ + "config" : { + "common_config" : { + + }, + "prod_config_only" : { + + }, + "hw_test_config_only" : { + + }, + "link_test_config_only" : { + + }, + "benchmark_config_only" : { + + }, + "port_map_config" : { + + } + } +} diff --git a/fboss/lib/platforms/PlatformMode.h b/fboss/lib/platforms/PlatformMode.h index f09eea8619ec0..93c8d05e56eb2 100644 --- a/fboss/lib/platforms/PlatformMode.h +++ b/fboss/lib/platforms/PlatformMode.h @@ -114,6 +114,8 @@ inline std::string toString(PlatformType mode) { return "LADAKH800BCLS"; case PlatformType::PLATFORM_ICECUBE800BANW: return "ICECUBE800BANW"; + case PlatformType::PLATFORM_J4SIM: + return "J4SIM"; case PlatformType::PLATFORM_UNKNOWN: return "UNKNOWN"; } diff --git a/fboss/lib/platforms/PlatformProductInfo.cpp b/fboss/lib/platforms/PlatformProductInfo.cpp index f02568a18e046..60aaf97a43d6f 100644 --- a/fboss/lib/platforms/PlatformProductInfo.cpp +++ b/fboss/lib/platforms/PlatformProductInfo.cpp @@ -210,6 +210,8 @@ void PlatformProductInfo::initMode() { modelName.find("Icecube800banw") == 0 || modelName.find("ICECUBE800BANW") == 0) { type_ = PlatformType::PLATFORM_ICECUBE800BANW; + } else if (modelName.find("J4Sim") == 0 || modelName.find("J4SIM") == 0) { + type_ = PlatformType::PLATFORM_J4SIM; } else { throw FbossError("invalid model name " + modelName); } @@ -290,6 +292,8 @@ void PlatformProductInfo::initMode() { type_ = PlatformType::PLATFORM_LADAKH800BCLS; } else if (FLAGS_mode == "icecube800banw") { type_ = PlatformType::PLATFORM_ICECUBE800BANW; + } else if (FLAGS_mode == "j4sim") { + type_ = PlatformType::PLATFORM_J4SIM; } else { throw std::runtime_error("invalid mode " + FLAGS_mode); } From 248f65111bf39b77f875a90246b19b6cb1aee16f Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 15:53:18 -0800 Subject: [PATCH 05/16] Update trace csv and vendor mappings --- .../j4sim/j4sim_port_profile_mapping.csv | 240 +++++++++--------- .../platforms/j4sim/j4sim_static_mapping.csv | 240 +++++++++--------- 2 files changed, 240 insertions(+), 240 deletions(-) diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv index 846ee56c8080b..fa5757e5a1721 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv @@ -7,123 +7,123 @@ Global_PortID,Logical_PortID,Port_Name,Supported_Port_Profiles,Attached_CoreID,A 6,6,eth1/1/6,56-47-49-43,,,,0,0 7,7,eth1/1/7,54-56-47-49-43,,,,0,0 8,8,eth1/1/8,56-47-49-43,,,,0,0 -1,1,eth1/2/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -2,2,eth1/2/2,56-47-49-43,,,,0,0 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+126,126,eth1/16/6,56-47-49-43,,,,0,0 +127,127,eth1/16/7,54-56-47-49-43,,,,0,0 +128,128,eth1/16/8,56-47-49-43,,,,0,0 diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv index 287ba3edf0df7..cb4736d04c2e0 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv @@ -7,123 +7,123 @@ A_SLOT_ID,A_CHIP_ID,A_CHIP_TYPE,A_CORE_ID,A_CORE_TYPE,A_CORE_LANE,A_PHYSICAL_TX_ 1,1,NPU,0,J4SIM_NIF,5,5,5,N,N,1,1,TRANSCEIVER,0,OSFP,5,5,5,N,N 1,1,NPU,0,J4SIM_NIF,6,6,6,N,N,1,1,TRANSCEIVER,0,OSFP,6,6,6,N,N 1,1,NPU,0,J4SIM_NIF,7,7,7,N,N,1,1,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,2,NPU,0,J4SIM_NIF,0,0,0,N,N,1,2,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,2,NPU,0,J4SIM_NIF,1,1,1,N,N,1,2,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,2,NPU,0,J4SIM_NIF,2,2,2,N,N,1,2,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,2,NPU,0,J4SIM_NIF,3,3,3,N,N,1,2,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,2,NPU,0,J4SIM_NIF,4,4,4,N,N,1,2,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,2,NPU,0,J4SIM_NIF,5,5,5,N,N,1,2,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,2,NPU,0,J4SIM_NIF,6,6,6,N,N,1,2,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,2,NPU,0,J4SIM_NIF,7,7,7,N,N,1,2,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,3,NPU,0,J4SIM_NIF,0,0,0,N,N,1,3,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,3,NPU,0,J4SIM_NIF,1,1,1,N,N,1,3,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,3,NPU,0,J4SIM_NIF,2,2,2,N,N,1,3,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,3,NPU,0,J4SIM_NIF,3,3,3,N,N,1,3,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,3,NPU,0,J4SIM_NIF,4,4,4,N,N,1,3,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,3,NPU,0,J4SIM_NIF,5,5,5,N,N,1,3,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,3,NPU,0,J4SIM_NIF,6,6,6,N,N,1,3,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,3,NPU,0,J4SIM_NIF,7,7,7,N,N,1,3,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,4,NPU,0,J4SIM_NIF,0,0,0,N,N,1,4,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,4,NPU,0,J4SIM_NIF,1,1,1,N,N,1,4,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,4,NPU,0,J4SIM_NIF,2,2,2,N,N,1,4,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,4,NPU,0,J4SIM_NIF,3,3,3,N,N,1,4,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,4,NPU,0,J4SIM_NIF,4,4,4,N,N,1,4,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,4,NPU,0,J4SIM_NIF,5,5,5,N,N,1,4,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,4,NPU,0,J4SIM_NIF,6,6,6,N,N,1,4,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,4,NPU,0,J4SIM_NIF,7,7,7,N,N,1,4,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,5,NPU,0,J4SIM_NIF,0,0,0,N,N,1,5,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,5,NPU,0,J4SIM_NIF,1,1,1,N,N,1,5,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,5,NPU,0,J4SIM_NIF,2,2,2,N,N,1,5,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,5,NPU,0,J4SIM_NIF,3,3,3,N,N,1,5,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,5,NPU,0,J4SIM_NIF,4,4,4,N,N,1,5,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,5,NPU,0,J4SIM_NIF,5,5,5,N,N,1,5,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,5,NPU,0,J4SIM_NIF,6,6,6,N,N,1,5,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,5,NPU,0,J4SIM_NIF,7,7,7,N,N,1,5,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,6,NPU,0,J4SIM_NIF,0,0,0,N,N,1,6,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,6,NPU,0,J4SIM_NIF,1,1,1,N,N,1,6,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,6,NPU,0,J4SIM_NIF,2,2,2,N,N,1,6,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,6,NPU,0,J4SIM_NIF,3,3,3,N,N,1,6,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,6,NPU,0,J4SIM_NIF,4,4,4,N,N,1,6,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,6,NPU,0,J4SIM_NIF,5,5,5,N,N,1,6,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,6,NPU,0,J4SIM_NIF,6,6,6,N,N,1,6,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,6,NPU,0,J4SIM_NIF,7,7,7,N,N,1,6,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,7,NPU,0,J4SIM_NIF,0,0,0,N,N,1,7,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,7,NPU,0,J4SIM_NIF,1,1,1,N,N,1,7,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,7,NPU,0,J4SIM_NIF,2,2,2,N,N,1,7,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,7,NPU,0,J4SIM_NIF,3,3,3,N,N,1,7,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,7,NPU,0,J4SIM_NIF,4,4,4,N,N,1,7,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,7,NPU,0,J4SIM_NIF,5,5,5,N,N,1,7,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,7,NPU,0,J4SIM_NIF,6,6,6,N,N,1,7,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,7,NPU,0,J4SIM_NIF,7,7,7,N,N,1,7,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,8,NPU,0,J4SIM_NIF,0,0,0,N,N,1,8,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,8,NPU,0,J4SIM_NIF,1,1,1,N,N,1,8,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,8,NPU,0,J4SIM_NIF,2,2,2,N,N,1,8,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,8,NPU,0,J4SIM_NIF,3,3,3,N,N,1,8,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,8,NPU,0,J4SIM_NIF,4,4,4,N,N,1,8,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,8,NPU,0,J4SIM_NIF,5,5,5,N,N,1,8,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,8,NPU,0,J4SIM_NIF,6,6,6,N,N,1,8,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,8,NPU,0,J4SIM_NIF,7,7,7,N,N,1,8,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,9,NPU,0,J4SIM_NIF,0,0,0,N,N,1,9,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,9,NPU,0,J4SIM_NIF,1,1,1,N,N,1,9,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,9,NPU,0,J4SIM_NIF,2,2,2,N,N,1,9,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,9,NPU,0,J4SIM_NIF,3,3,3,N,N,1,9,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,9,NPU,0,J4SIM_NIF,4,4,4,N,N,1,9,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,9,NPU,0,J4SIM_NIF,5,5,5,N,N,1,9,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,9,NPU,0,J4SIM_NIF,6,6,6,N,N,1,9,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,9,NPU,0,J4SIM_NIF,7,7,7,N,N,1,9,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,10,NPU,0,J4SIM_NIF,0,0,0,N,N,1,10,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,10,NPU,0,J4SIM_NIF,1,1,1,N,N,1,10,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,10,NPU,0,J4SIM_NIF,2,2,2,N,N,1,10,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,10,NPU,0,J4SIM_NIF,3,3,3,N,N,1,10,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,10,NPU,0,J4SIM_NIF,4,4,4,N,N,1,10,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,10,NPU,0,J4SIM_NIF,5,5,5,N,N,1,10,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,10,NPU,0,J4SIM_NIF,6,6,6,N,N,1,10,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,10,NPU,0,J4SIM_NIF,7,7,7,N,N,1,10,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,11,NPU,0,J4SIM_NIF,0,0,0,N,N,1,11,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,11,NPU,0,J4SIM_NIF,1,1,1,N,N,1,11,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,11,NPU,0,J4SIM_NIF,2,2,2,N,N,1,11,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,11,NPU,0,J4SIM_NIF,3,3,3,N,N,1,11,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,11,NPU,0,J4SIM_NIF,4,4,4,N,N,1,11,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,11,NPU,0,J4SIM_NIF,5,5,5,N,N,1,11,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,11,NPU,0,J4SIM_NIF,6,6,6,N,N,1,11,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,11,NPU,0,J4SIM_NIF,7,7,7,N,N,1,11,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,12,NPU,0,J4SIM_NIF,0,0,0,N,N,1,12,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,12,NPU,0,J4SIM_NIF,1,1,1,N,N,1,12,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,12,NPU,0,J4SIM_NIF,2,2,2,N,N,1,12,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,12,NPU,0,J4SIM_NIF,3,3,3,N,N,1,12,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,12,NPU,0,J4SIM_NIF,4,4,4,N,N,1,12,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,12,NPU,0,J4SIM_NIF,5,5,5,N,N,1,12,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,12,NPU,0,J4SIM_NIF,6,6,6,N,N,1,12,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,12,NPU,0,J4SIM_NIF,7,7,7,N,N,1,12,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,13,NPU,0,J4SIM_NIF,0,0,0,N,N,1,13,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,13,NPU,0,J4SIM_NIF,1,1,1,N,N,1,13,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,13,NPU,0,J4SIM_NIF,2,2,2,N,N,1,13,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,13,NPU,0,J4SIM_NIF,3,3,3,N,N,1,13,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,13,NPU,0,J4SIM_NIF,4,4,4,N,N,1,13,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,13,NPU,0,J4SIM_NIF,5,5,5,N,N,1,13,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,13,NPU,0,J4SIM_NIF,6,6,6,N,N,1,13,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,13,NPU,0,J4SIM_NIF,7,7,7,N,N,1,13,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,14,NPU,0,J4SIM_NIF,0,0,0,N,N,1,14,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,14,NPU,0,J4SIM_NIF,1,1,1,N,N,1,14,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,14,NPU,0,J4SIM_NIF,2,2,2,N,N,1,14,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,14,NPU,0,J4SIM_NIF,3,3,3,N,N,1,14,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,14,NPU,0,J4SIM_NIF,4,4,4,N,N,1,14,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,14,NPU,0,J4SIM_NIF,5,5,5,N,N,1,14,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,14,NPU,0,J4SIM_NIF,6,6,6,N,N,1,14,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,14,NPU,0,J4SIM_NIF,7,7,7,N,N,1,14,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,15,NPU,0,J4SIM_NIF,0,0,0,N,N,1,15,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,15,NPU,0,J4SIM_NIF,1,1,1,N,N,1,15,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,15,NPU,0,J4SIM_NIF,2,2,2,N,N,1,15,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,15,NPU,0,J4SIM_NIF,3,3,3,N,N,1,15,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,15,NPU,0,J4SIM_NIF,4,4,4,N,N,1,15,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,15,NPU,0,J4SIM_NIF,5,5,5,N,N,1,15,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,15,NPU,0,J4SIM_NIF,6,6,6,N,N,1,15,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,15,NPU,0,J4SIM_NIF,7,7,7,N,N,1,15,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,16,NPU,0,J4SIM_NIF,0,0,0,N,N,1,16,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,16,NPU,0,J4SIM_NIF,1,1,1,N,N,1,16,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,16,NPU,0,J4SIM_NIF,2,2,2,N,N,1,16,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,16,NPU,0,J4SIM_NIF,3,3,3,N,N,1,16,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,16,NPU,0,J4SIM_NIF,4,4,4,N,N,1,16,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,16,NPU,0,J4SIM_NIF,5,5,5,N,N,1,16,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,16,NPU,0,J4SIM_NIF,6,6,6,N,N,1,16,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,16,NPU,0,J4SIM_NIF,7,7,7,N,N,1,16,TRANSCEIVER,0,OSFP,7,7,7,N,N +1,1,NPU,1,J4SIM_NIF,0,0,0,N,N,1,2,TRANSCEIVER,0,OSFP,0,0,0,N,N +1,1,NPU,1,J4SIM_NIF,1,1,1,N,N,1,2,TRANSCEIVER,0,OSFP,1,1,1,N,N +1,1,NPU,1,J4SIM_NIF,2,2,2,N,N,1,2,TRANSCEIVER,0,OSFP,2,2,2,N,N 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.../j4sim_platform_mapping.json | 35498 ++++++++++++++++ .../j4sim/j4sim_profile_settings.csv | 30 +- 2 files changed, 35513 insertions(+), 15 deletions(-) create mode 100644 fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json diff --git a/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json new file mode 100644 index 0000000000000..bf3bdaa90e768 --- /dev/null +++ b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json @@ -0,0 +1,35498 @@ +{ + "ports": { + "1": { + "mapping": { + "id": 1, + "name": "eth1/1/1", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + }, + "z": { + "end": { + "chip": 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+ { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 7 + } + } + ] + } + }, + "56": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 4 + } + } + ] + } + }, + "47": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 4 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 4 + } + } + ] + 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"subsumedPorts": [ + 128 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 7 + } + } + ] + } + }, + "56": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 6 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 6 + } + } + ] + } + }, + "47": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 6 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "lane": 6 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "lane": 6 + } + } + ], + "transceiver": [ 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"physicalID": 4 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core5", + "type": 1, + "physicalID": 5 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core6", + "type": 1, + "physicalID": 6 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core7", + "type": 1, + "physicalID": 7 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core8", + "type": 1, + "physicalID": 8 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core9", + "type": 1, + "physicalID": 9 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core10", + "type": 1, + "physicalID": 10 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core11", + "type": 1, + "physicalID": 11 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core12", + "type": 1, + "physicalID": 12 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core13", + "type": 1, + "physicalID": 13 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core14", + "type": 1, + "physicalID": 14 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core15", + "type": 1, + "physicalID": 15 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip1", + "type": 3, + "physicalID": 0 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip2", + "type": 3, + "physicalID": 1 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip3", + "type": 3, + "physicalID": 2 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip4", + "type": 3, + "physicalID": 3 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip5", + "type": 3, + "physicalID": 4 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip6", + "type": 3, + "physicalID": 5 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip7", + "type": 3, + "physicalID": 6 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip8", + "type": 3, + "physicalID": 7 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip9", + "type": 3, + "physicalID": 8 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip10", + "type": 3, + "physicalID": 9 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip11", + "type": 3, + "physicalID": 10 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip12", + "type": 3, + "physicalID": 11 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip13", + "type": 3, + "physicalID": 12 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip14", + "type": 3, + "physicalID": 13 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip15", + "type": 3, + "physicalID": 14 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip16", + "type": 3, + "physicalID": 15 + } + ], + "platformSupportedProfiles": [ + { + "factor": { + "profileID": 35 + }, + "profile": { + "speed": 400000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 1, + "interfaceType": 13 + } + } + }, + { + "factor": { + "profileID": 38 + }, + "profile": { + "speed": 400000, + "iphy": { + "numLanes": 4, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 21 + } + } + }, + { + "factor": { + "profileID": 39 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 23 + } + } + }, + { + "factor": { + "profileID": 43 + }, + "profile": { + "speed": 50000, + "iphy": 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"interfaceType": 21 + } + } + }, + { + "factor": { + "profileID": 54 + }, + "profile": { + "speed": 200000, + "iphy": { + "numLanes": 2, + "modulation": 2, + "fec": 544, + "medium": 1, + "interfaceType": 11 + } + } + }, + { + "factor": { + "profileID": 22 + }, + "profile": { + "speed": 100000, + "iphy": { + "numLanes": 4, + "modulation": 1, + "fec": 528, + "medium": 1, + "interfaceType": 12 + } + } + }, + { + "factor": { + "profileID": 24 + }, + "profile": { + "speed": 200000, + "iphy": { + "numLanes": 4, + "modulation": 2, + "fec": 11, + "medium": 1, + "interfaceType": 12 + } + } + }, + { + "factor": { + "profileID": 25 + }, + "profile": { + "speed": 200000, + "iphy": { + "numLanes": 4, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 21 + } + } + }, + { + "factor": { + "profileID": 56 + }, + "profile": { + "speed": 100000, + "iphy": { + "numLanes": 1, + "modulation": 2, + "fec": 544, + "medium": 1, + "interfaceType": 10 + } + } + } + ] +} diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv index d146eb222eecb..de57fb84804f9 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv @@ -1,15 +1,15 @@ -Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type -100000,NPU,TRANSCEIVER,1,PAM4,RS544,OPTICAL,SR, -100000,NPU,TRANSCEIVER,1,PAM4,NONE,COPPER,CR, -100000,NPU,TRANSCEIVER,1,PAM4,RS544,COPPER,CR, -100000,NPU,TRANSCEIVER,4,NRZ,RS528,COPPER,CR4, -100000,NPU,TRANSCEIVER,4,NRZ,RS528,OPTICAL,SR4, -200000,NPU,TRANSCEIVER,2,PAM4,RS544,COPPER,CR2, -200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,COPPER,CR4, -200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,OPTICAL,SR4, -400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,OPTICAL,SR4, -400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,COPPER,CR4, -400000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,COPPER,CR8, -50000,NPU,TRANSCEIVER,1,PAM4,RS544,COPPER,CR, -800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,OPTICAL,SR8, -800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,COPPER,CR8, +Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,A_FEC,Z_FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type +100000,NPU,TRANSCEIVER,1,PAM4,RS544,,OPTICAL,SR, +100000,NPU,TRANSCEIVER,1,PAM4,NONE,,COPPER,CR, +100000,NPU,TRANSCEIVER,1,PAM4,RS544,,COPPER,CR, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,,COPPER,CR4, +100000,NPU,TRANSCEIVER,4,NRZ,RS528,,OPTICAL,SR4, +200000,NPU,TRANSCEIVER,2,PAM4,RS544,,COPPER,CR2, +200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, +200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,SR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,SR4, +400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, +400000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, +50000,NPU,TRANSCEIVER,1,PAM4,RS544,,COPPER,CR, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,OPTICAL,SR8, +800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, From a3e3cd65fa17e8ca7fa19e83b2baf6d3a23bd777 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 16:46:28 -0800 Subject: [PATCH 07/16] Add ASIC_TYPE_JERICHO4 to AsicType enum --- fboss/agent/switch_config.thrift | 1 + 1 file changed, 1 insertion(+) diff --git a/fboss/agent/switch_config.thrift b/fboss/agent/switch_config.thrift index 0c8916c688ada..64fdc740895c4 100644 --- a/fboss/agent/switch_config.thrift +++ b/fboss/agent/switch_config.thrift @@ -1543,6 +1543,7 @@ enum AsicType { ASIC_TYPE_G202X = 20, ASIC_TYPE_FAKE_NO_WARMBOOT = 21, ASIC_TYPE_TOMAHAWKULTRA1 = 22, + ASIC_TYPE_JERICHO4 = 23, } /** * The configuration for an interface From 522faa7634ad6d0d4a88011820eea359318fd1e2 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 17 Feb 2026 16:51:42 -0800 Subject: [PATCH 08/16] Add Jericho4Asic.h and make J4Sim stuff use it instead of Q4DAsic.h --- fboss/agent/hw/switch_asics/Jericho4Asic.h | 23 +++++++++++++++++++ .../platforms/sai/SaiBcmJ4SimPlatform.cpp | 4 ++-- .../agent/platforms/sai/SaiBcmJ4SimPlatform.h | 4 ++-- 3 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 fboss/agent/hw/switch_asics/Jericho4Asic.h diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h new file mode 100644 index 0000000000000..ff03ef3d33920 --- /dev/null +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -0,0 +1,23 @@ +// Copyright 2004-present Facebook. All Rights Reserved. + +#pragma once + +#include +#include "fboss/agent/hw/switch_asics/Q4DAsic.h" + +namespace facebook::fboss { + +class Jericho4Asic : public Q4DAsic { + public: + Jericho4Asic( + std::optional switchId, + cfg::SwitchInfo switchInfo, + std::optional sdkVersion = std::nullopt) + : Q4DAsic(switchId, switchInfo, sdkVersion) {} + + cfg::AsicType getAsicType() const override { + return cfg::AsicType::ASIC_TYPE_JERICHO4; + } +}; + +} // namespace facebook::fboss diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp index 78c057daf53ba..c3a4776d2cc1f 100644 --- a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp @@ -10,7 +10,7 @@ #include "fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h" -#include "fboss/agent/hw/switch_asics/Q4DAsic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" namespace { @@ -37,7 +37,7 @@ void SaiBcmJ4SimPlatform::setupAsic( const cfg::SwitchInfo& switchInfo, std::optional fabricNodeRole) { CHECK(!fabricNodeRole.has_value()); - asic_ = std::make_unique(switchId, switchInfo); + asic_ = std::make_unique(switchId, switchInfo); } HwAsic* SaiBcmJ4SimPlatform::getAsic() const { diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h index 89deeeeac25fc..aa1c11d956c6b 100644 --- a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.h @@ -13,7 +13,7 @@ namespace facebook::fboss { -class Q4DAsic; +class Jericho4Asic; class SaiBcmJ4SimPlatform : public SaiBcmPlatform { public: @@ -64,7 +64,7 @@ class SaiBcmJ4SimPlatform : public SaiBcmPlatform { const cfg::SwitchInfo& switchInfo, std::optional fabricNodeRole) override; - std::unique_ptr asic_; + std::unique_ptr asic_; }; } // namespace facebook::fboss From a647e92c2d2a1ecfeb0b69a449196e8fb8855bbb Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Wed, 18 Feb 2026 09:39:04 -0800 Subject: [PATCH 09/16] Update Jericho4Asic to inherit from Jericho3Asic, and set max port speed 200G --- fboss/agent/hw/switch_asics/HwAsic.cpp | 3 +++ fboss/agent/hw/switch_asics/Jericho4Asic.h | 8 ++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/fboss/agent/hw/switch_asics/HwAsic.cpp b/fboss/agent/hw/switch_asics/HwAsic.cpp index 676391b85d34d..5ba57db8c1f8b 100644 --- a/fboss/agent/hw/switch_asics/HwAsic.cpp +++ b/fboss/agent/hw/switch_asics/HwAsic.cpp @@ -18,6 +18,7 @@ #include "fboss/agent/hw/switch_asics/G202xAsic.h" #include "fboss/agent/hw/switch_asics/Jericho2Asic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/hw/switch_asics/MockAsic.h" #include "fboss/agent/hw/switch_asics/Ramon3Asic.h" #include "fboss/agent/hw/switch_asics/RamonAsic.h" @@ -120,6 +121,8 @@ std::unique_ptr HwAsic::makeAsic( return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_JERICHO3: return std::make_unique(switchId, switchInfo, sdkVersion); + case cfg::AsicType::ASIC_TYPE_JERICHO4: + return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_RAMON: return std::make_unique(switchId, switchInfo, sdkVersion); case cfg::AsicType::ASIC_TYPE_RAMON3: diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h index ff03ef3d33920..d26b03f364163 100644 --- a/fboss/agent/hw/switch_asics/Jericho4Asic.h +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -3,7 +3,7 @@ #pragma once #include -#include "fboss/agent/hw/switch_asics/Q4DAsic.h" +#include "fboss/agent/hw/switch_asics/Jericho3Asic.h" namespace facebook::fboss { @@ -13,11 +13,15 @@ class Jericho4Asic : public Q4DAsic { std::optional switchId, cfg::SwitchInfo switchInfo, std::optional sdkVersion = std::nullopt) - : Q4DAsic(switchId, switchInfo, sdkVersion) {} + : Jericho3Asic(switchId, switchInfo, sdkVersion) {} cfg::AsicType getAsicType() const override { return cfg::AsicType::ASIC_TYPE_JERICHO4; } + + cfg::PortSpeed getMaxPortSpeed() const override { + return cfg::PortSpeed::TWOHUNDREDG; + } }; } // namespace facebook::fboss From 0a0f237f1826354d643a95336d5c00bc8f3eabc5 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Wed, 18 Feb 2026 10:00:44 -0800 Subject: [PATCH 10/16] Changes to get generate.py working, and exclude all except pm config --- .../configs/j4sim/platform_manager.json | 188 ++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 fboss/platform/configs/j4sim/platform_manager.json diff --git a/fboss/platform/configs/j4sim/platform_manager.json b/fboss/platform/configs/j4sim/platform_manager.json new file mode 100644 index 0000000000000..1caaee14efa3c --- /dev/null +++ b/fboss/platform/configs/j4sim/platform_manager.json @@ -0,0 +1,188 @@ +{ + "platformName": "J4SIM", + "rootPmUnitName": "SCM", + "rootSlotType": "SCM_SLOT", + "slotTypeConfigs": { + "SCM_SLOT": { + "numOutgoingI2cBuses": 0, + "idpromConfig": { + "busName": "SMBus I801 adapter at 1000", + "address": "0x50", + "kernelDeviceName": "24c512", + "offset": 15360 + }, + "pmUnitName": "SCM" + }, + "SMB_SLOT": { + "numOutgoingI2cBuses": 5, + "idpromConfig": { + "busName": "INCOMING@1", + "address": "0x50", + "kernelDeviceName": "24c512", + "offset": 15360 + }, + "pmUnitName": "SMB" + }, + "PSU_SLOT": { + "numOutgoingI2cBuses": 1, + "pmUnitName": "PSU" + }, + "FAN_SLOT": { + "numOutgoingI2cBuses": 0, + "pmUnitName": "FAN" + } + }, + "pmUnitConfigs": { + "SCM": { + "pluggedInSlotType": "SCM_SLOT", + "i2cDeviceConfigs": [ + { + "busName": "SCM_I2C_MASTER_0@0", + "address": "0x40", + "kernelDeviceName": "pmbus", + "pmUnitScopedName": "SCM_MPS_PMBUS" + } + ], + "outgoingSlotConfigs": { + "SMB_SLOT@0": { + "slotType": "SMB_SLOT", + "outgoingI2cBusNames": [ + "SCM_I2C_MASTER_0@0", + "SCM_I2C_MASTER_1@0", + "SCM_I2C_MASTER_1@1", + "SCM_I2C_MASTER_1@2", + "SCM_I2C_MASTER_1@3" + ] + } + }, + "pciDeviceConfigs": [ + { + "pmUnitScopedName": "SCM_FPGA", + "vendorId": "0x3475", + "deviceId": "0x0001", + "subSystemVendorId": "0x3475", + "subSystemDeviceId": "0x0008", + "i2cAdapterBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "SCM_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8000 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 0, + "numAdapters": 2, + "numBusesPerAdapter": 8 + } + ], + "spiMasterConfigs": [], + "infoRomConfigs": [ + { + "pmUnitScopedName": "SCM_FPGA_INFO_ROM", + "deviceName": "fpga_info_iob", + "csrOffset": "0x100" + } + ], + "miscCtrlConfigs": [ + { + "pmUnitScopedName": "SCM_ADC", + "deviceName": "adc", + "csrOffset": "0x7300" + } + ] + } + ], + "embeddedSensorConfigs": [ + { + "pmUnitScopedName": "CPU_CORE_TEMP", + "sysfsPath": "/sys/bus/platform/devices/coretemp.0" + }, + { + "pmUnitScopedName": "NVME_TEMP", + "sysfsPath": "/sys/class/nvme/nvme0" + } + ] + }, + "SMB": { + "pluggedInSlotType": "SMB_SLOT", + "i2cDeviceConfigs": [], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [ + { + "pmUnitScopedName": "SMB_FPGA", + "vendorId": "0x3475", + "deviceId": "0x0001", + "subSystemVendorId": "0x3475", + "subSystemDeviceId": "0x0015", + "i2cAdapterBlockConfigs": [], + "spiMasterConfigs": [], + "ledCtrlBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "OSFP", + "deviceName": "port_led", + "csrOffsetCalc": "0x6100 + ({portNum} - {startPort})*0x20 + ({ledNum} - 1)*0x10", + "numPorts": 64, + "ledPerPort": 2, + "startPort": 1 + }, + { + "pmUnitScopedNamePrefix": "QSFP", + "deviceName": "port_led", + "csrOffsetCalc": "0x6900 + ({portNum} - {startPort})*0x10 + ({ledNum} - 1)*0x10", + "numPorts": 4, + "ledPerPort": 1, + "startPort": 65 + } + ], + "xcvrCtrlBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "OSFP", + "deviceName": "xcvr_ctrl", + "csrOffsetCalc": "0xa010 + ({portNum} - {startPort})*0x10", + "numPorts": 64, + "startPort": 1 + }, + { + "pmUnitScopedNamePrefix": "QSFP", + "deviceName": "xcvr_ctrl", + "csrOffsetCalc": "0xa410 + ({portNum} - {startPort})*0x10", + "numPorts": 4, + "startPort": 65 + } + ], + "infoRomConfigs": [] + } + ] + }, + "PSU": { + "pluggedInSlotType": "PSU_SLOT", + "i2cDeviceConfigs": [ + { + "busName": "INCOMING@0", + "address": "0x58", + "kernelDeviceName": "pmbus", + "pmUnitScopedName": "PSU_PMBUS" + } + ], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [] + }, + "FAN": { + "pluggedInSlotType": "FAN_SLOT", + "i2cDeviceConfigs": [], + "outgoingSlotConfigs": {}, + "pciDeviceConfigs": [] + } + }, + "i2cAdaptersFromCpu": [ + "SMBus I801 adapter at 1000" + ], + "symbolicLinkToDevicePath": {}, + "chassisEepromDevicePath": "/SMB_SLOT@0/[IDPROM]", + "numXcvrs": 68, + "bspKmodsRpmName": "arista_bsp_kmods", + "bspKmodsRpmVersion": "0.7.17-1", + "requiredKmodsToLoad": [ + "spidev", + "i2c_i801", + "scd", + "ledtrig_timer" + ] +} From ac29e526407122b067aa99ff89a3d05405a9ac21 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Wed, 18 Feb 2026 15:08:38 -0800 Subject: [PATCH 11/16] Fix J4 not inheriting from J3 --- fboss/agent/hw/switch_asics/Jericho4Asic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h index d26b03f364163..1e2a56fc8a56e 100644 --- a/fboss/agent/hw/switch_asics/Jericho4Asic.h +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -7,7 +7,7 @@ namespace facebook::fboss { -class Jericho4Asic : public Q4DAsic { +class Jericho4Asic : public Jericho3Asic { public: Jericho4Asic( std::optional switchId, From 85353c8d28f41a342f9d051b85a87168a0f7c203 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Thu, 19 Feb 2026 08:34:14 -0800 Subject: [PATCH 12/16] Address comments, and make changes to get build working for J4Sim/Jericho4 --- fboss/agent/ApplyThriftConfig.cpp | 1 + fboss/agent/AsicUtils.cpp | 8 + fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp | 1 + .../hw_test/HwTestTamUtilsThriftHandler.cpp | 1 + .../hw/sai/switch/SaiAclTableManager.cpp | 5 +- .../agent/hw/sai/switch/SaiBufferManager.cpp | 2 + fboss/agent/hw/sai/switch/SaiPortManager.cpp | 1 + .../hw/sai/switch/SaiVirtualRouterManager.cpp | 1 + fboss/agent/hw/switch_asics/Jericho4Asic.h | 10 +- .../hw/test/HwHashPolarizationTestUtils.cpp | 2 + .../dataplane_tests/HwProdInvariantHelper.cpp | 1 + fboss/agent/platforms/sai/SaiPlatform.cpp | 1 + fboss/agent/switch_config.thrift | 1 + .../AgentDiagShellStressTests.cpp | 1 + .../prod_agent_tests/ProdInvariantTests.cpp | 1 + fboss/agent/test/utils/ConfigUtils.cpp | 14 +- fboss/agent/test/utils/CoppTestUtils.cpp | 9 +- fboss/agent/test/utils/InvariantTestUtils.cpp | 1 + .../j4sim.agent.materialized_JSON | 946 ++++++++++++++++++ .../configs/j4sim/platform_manager.json | 272 ++++- 20 files changed, 1267 insertions(+), 12 deletions(-) create mode 100644 fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON diff --git a/fboss/agent/ApplyThriftConfig.cpp b/fboss/agent/ApplyThriftConfig.cpp index ec0ed70bb3e31..5dee92226a6df 100644 --- a/fboss/agent/ApplyThriftConfig.cpp +++ b/fboss/agent/ApplyThriftConfig.cpp @@ -1175,6 +1175,7 @@ void ThriftConfigApplier::processUpdatedDsfNodes() { asicCore = 1; break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: if (isDualStage3Q2QMode()) { asicCore = 447; } else { diff --git a/fboss/agent/AsicUtils.cpp b/fboss/agent/AsicUtils.cpp index 31261bdabcd90..ea4594c8dfbc8 100644 --- a/fboss/agent/AsicUtils.cpp +++ b/fboss/agent/AsicUtils.cpp @@ -10,6 +10,7 @@ #include "fboss/agent/AsicUtils.h" #include "fboss/agent/hw/switch_asics/Jericho2Asic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/hw/switch_asics/Ramon3Asic.h" #include "fboss/agent/hw/switch_asics/RamonAsic.h" @@ -39,6 +40,11 @@ const HwAsic& getHwAsicForAsicType(const cfg::AsicType& asicType) { static Jericho3Asic jericho3Asic{switchId, switchInfo}; return jericho3Asic; } + case cfg::AsicType::ASIC_TYPE_JERICHO4: { + switchInfo.switchType() = cfg::SwitchType::VOQ; + static Jericho4Asic jericho4Asic{switchId, switchInfo}; + return jericho4Asic; + } case cfg::AsicType::ASIC_TYPE_RAMON: { switchInfo.switchType() = cfg::SwitchType::FABRIC; static RamonAsic ramonAsic{switchId, switchInfo}; @@ -82,6 +88,8 @@ uint32_t getFabricPortsPerVirtualDevice(const cfg::AsicType asicType) { return 192; case cfg::AsicType::ASIC_TYPE_JERICHO3: return 160; + case cfg::AsicType::ASIC_TYPE_JERICHO4: + return 160; case cfg::AsicType::ASIC_TYPE_RAMON3: return 256; case cfg::AsicType::ASIC_TYPE_FAKE: diff --git a/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp b/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp index 3629cf64fd3db..40be498126700 100644 --- a/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp +++ b/fboss/agent/hw/sai/hw_test/HwTestTamUtils.cpp @@ -141,6 +141,7 @@ void triggerParityError(HwSwitchEnsemble* ensemble) { triggerBcmJericho2ParityError(ensemble); break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: triggerBcmJericho3ParityError(ensemble); break; case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp b/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp index 357d8f02d4806..6c41183f7cd18 100644 --- a/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp +++ b/fboss/agent/hw/sai/hw_test/HwTestTamUtilsThriftHandler.cpp @@ -236,6 +236,7 @@ void HwTestThriftHandler::triggerParityError() { triggerBcmJericho2ParityError(hwSwitch_); break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: triggerBcmJericho3ParityError(hwSwitch_); break; case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp b/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp index 30ceb503f6f29..ac3fa7d9a9e45 100644 --- a/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiAclTableManager.cpp @@ -1682,8 +1682,9 @@ std::set SaiAclTableManager::getSupportedQualifierSet( platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_TRIDENT2; bool isJericho2 = platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO2; - bool isJericho3 = - platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3; + bool isJericho3 = platform_->getAsic()->getAsicType() == + cfg::AsicType::ASIC_TYPE_JERICHO3 || + platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4; bool isTomahawk5 = platform_->getAsic()->getAsicType() == cfg::AsicType::ASIC_TYPE_TOMAHAWK5; bool isChenab = diff --git a/fboss/agent/hw/sai/switch/SaiBufferManager.cpp b/fboss/agent/hw/sai/switch/SaiBufferManager.cpp index 31742f7d3af7a..8f9a359d0394c 100644 --- a/fboss/agent/hw/sai/switch/SaiBufferManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiBufferManager.cpp @@ -109,6 +109,7 @@ void assertMaxBufferPoolSize(const SaiPlatform* platform) { break; case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_TRIDENT2: CHECK_EQ(maxEgressPoolSize, availableBuffer); break; @@ -201,6 +202,7 @@ uint64_t SaiBufferManager::getMaxEgressPoolBytes(const SaiPlatform* platform) { } case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: /* * XXX: TODO: Need to check if there is a way to compute the * buffers available for use in Jericho2 without using the diff --git a/fboss/agent/hw/sai/switch/SaiPortManager.cpp b/fboss/agent/hw/sai/switch/SaiPortManager.cpp index 30897e2a51805..ccf1d3eecb26e 100644 --- a/fboss/agent/hw/sai/switch/SaiPortManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiPortManager.cpp @@ -611,6 +611,7 @@ int getWorstCaseAssumedOpticsDelayNS( case cfg::AsicType::ASIC_TYPE_G202X: break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: if (portType == cfg::PortType::FABRIC_PORT) { return 110; } else { diff --git a/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp b/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp index 93d52d0ad656c..86dfa0a7b14bc 100644 --- a/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp +++ b/fboss/agent/hw/sai/switch/SaiVirtualRouterManager.cpp @@ -110,6 +110,7 @@ SaiVirtualRouterManager::createMplsRouterInterface(VirtualRouterSaiId vrId) { case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_CHENAB: diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h index 1e2a56fc8a56e..0c1df66398630 100644 --- a/fboss/agent/hw/switch_asics/Jericho4Asic.h +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -20,7 +20,15 @@ class Jericho4Asic : public Jericho3Asic { } cfg::PortSpeed getMaxPortSpeed() const override { - return cfg::PortSpeed::TWOHUNDREDG; + return cfg::PortSpeed::ONEPOINTSIXT; + } + + bool isSupported(Feature feature) const override { + // TBD if necessary + if (feature == HwAsic::Feature::SWITCH_ISOLATE) { + return false; + } + return Jericho3Asic::isSupported(feature); } }; diff --git a/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp b/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp index bc48f906f5c64..0a4247b41bc84 100644 --- a/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp +++ b/fboss/agent/hw/test/HwHashPolarizationTestUtils.cpp @@ -57,6 +57,7 @@ std::unique_ptr> getFullHashedPackets( case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_G202X: @@ -88,6 +89,7 @@ std::unique_ptr> getFullHashedPackets( case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_G202X: diff --git a/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp b/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp index efc3ee16d28c7..75eb1fef91893 100644 --- a/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp +++ b/fboss/agent/hw/test/dataplane_tests/HwProdInvariantHelper.cpp @@ -174,6 +174,7 @@ void HwProdInvariantHelper::verifySafeDiagCmds() { case cfg::AsicType::ASIC_TYPE_SANDIA_PHY: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/agent/platforms/sai/SaiPlatform.cpp b/fboss/agent/platforms/sai/SaiPlatform.cpp index 7014fac32e4c5..9e42ab5326d30 100644 --- a/fboss/agent/platforms/sai/SaiPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiPlatform.cpp @@ -565,6 +565,7 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( } switch (*dsfNode.asicType()) { case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: // for directly connected interface nodes we don't expect // asic type to change across dsf nodes maxCoreCount = std::max(j3.getNumCores(), maxCoreCount); diff --git a/fboss/agent/switch_config.thrift b/fboss/agent/switch_config.thrift index 64fdc740895c4..4e7a7703abbce 100644 --- a/fboss/agent/switch_config.thrift +++ b/fboss/agent/switch_config.thrift @@ -121,6 +121,7 @@ enum PortSpeed { TWOHUNDREDG = 200000, // 200G FOURHUNDREDG = 400000, // 400G EIGHTHUNDREDG = 800000, // 800G + ONEPOINTSIXT = 1600000, // 1.6T THREEPOINTTWOT = 3200000, // 3.2T } diff --git a/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp b/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp index 827e2b709e2b7..000613f3b7eb0 100644 --- a/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp +++ b/fboss/agent/test/agent_hw_tests/AgentDiagShellStressTests.cpp @@ -33,6 +33,7 @@ class AgentDiagShellStressTest : public AgentHwTest { // No diag shell to test for these ASICs break; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: runBcmDnxCmds(switchId); break; case cfg::AsicType::ASIC_TYPE_EBRO: diff --git a/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp b/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp index 3a83d95bfbb9f..f94027e8f9b14 100644 --- a/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp +++ b/fboss/agent/test/prod_agent_tests/ProdInvariantTests.cpp @@ -373,6 +373,7 @@ void ProdInvariantTest::verifySafeDiagCommands() { case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/agent/test/utils/ConfigUtils.cpp b/fboss/agent/test/utils/ConfigUtils.cpp index 4913f667a9998..bfad452a09b73 100644 --- a/fboss/agent/test/utils/ConfigUtils.cpp +++ b/fboss/agent/test/utils/ConfigUtils.cpp @@ -87,7 +87,9 @@ int getSysPortIdsAllocated( std::optional platformType = std::nullopt) { auto portsConsumed = firstSwitchIdMin; auto deviceIndex = remoteSwitchId / asic.getNumCores(); - CHECK(asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3); + CHECK( + asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asic.getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4); if (deviceIndex < getMaxRdsw(platformType)) { portsConsumed += deviceIndex * getRdswSysPortBlockSize(platformType) - 1; } else { @@ -275,7 +277,8 @@ std::unordered_map getSafeProfileIDs( auto bestSpeed = cfg::PortSpeed::DEFAULT; auto bestProfile = cfg::PortProfileID::PROFILE_DEFAULT; - if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 && + if ((asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) && FLAGS_dual_stage_rdsw_3q_2q) { // When using dual_stage_rdsw_3q_2q mapping. Pick NIF port // speed to be 400G, since that's what we have in chip config @@ -481,6 +484,7 @@ cfg::DsfNode dsfNodeConfig( case cfg::AsicType::ASIC_TYPE_JERICHO2: return PlatformType::PLATFORM_MERU400BIU; case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: return PlatformType::PLATFORM_MERU800BIA; case cfg::AsicType::ASIC_TYPE_RAMON: return PlatformType::PLATFORM_MERU400BFU; @@ -871,7 +875,8 @@ cfg::SwitchConfig genPortVlanCfg( connectionHandle = "0c:00"; } else if ( asicType == cfg::AsicType::ASIC_TYPE_RAMON3 || - asicType == cfg::AsicType::ASIC_TYPE_JERICHO3) { + asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) { connectionHandle = "15:00"; } else if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO2) { connectionHandle = "68:00"; @@ -1104,7 +1109,8 @@ cfg::SwitchInfo generateSwitchInfo( switchInfo.asicType() = asicType; if (asicType == cfg::AsicType::ASIC_TYPE_JERICHO2 || - asicType == cfg::AsicType::ASIC_TYPE_JERICHO3) { + asicType == cfg::AsicType::ASIC_TYPE_JERICHO3 || + asicType == cfg::AsicType::ASIC_TYPE_JERICHO4) { switchInfo.switchMac() = "02:00:00:00:00:01"; } switchInfo.systemPortRanges() = asic->getSystemPortRanges(); diff --git a/fboss/agent/test/utils/CoppTestUtils.cpp b/fboss/agent/test/utils/CoppTestUtils.cpp index 3335aec4ce3cb..711f73bfafbc6 100644 --- a/fboss/agent/test/utils/CoppTestUtils.cpp +++ b/fboss/agent/test/utils/CoppTestUtils.cpp @@ -119,6 +119,7 @@ uint16_t getCoppHighPriQueueId(const HwAsic* hwAsic) { case cfg::AsicType::ASIC_TYPE_YUBA: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_G202X: return 7; case cfg::AsicType::ASIC_TYPE_CHENAB: @@ -166,6 +167,11 @@ cfg::ToCpuAction getCpuActionType(const HwAsic* hwAsic) { return cfg::ToCpuAction::COPY; case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: +<<<<<<< HEAD +======= + case cfg::AsicType::ASIC_TYPE_Q4D: + case cfg::AsicType::ASIC_TYPE_JERICHO4: +>>>>>>> 5504971436 (Address comments, and make changes to get build working for J4Sim/Jericho4) case cfg::AsicType::ASIC_TYPE_CHENAB: return cfg::ToCpuAction::TRAP; case cfg::AsicType::ASIC_TYPE_ELBERT_8DD: @@ -246,7 +252,8 @@ cfg::PortQueueRate getPortQueueRate(const HwAsic* hwAsic, uint16_t queueId) { portQueueRate.pktsPerSec() = getRange(0, pps); } else { uint32_t kbps; - if (hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3) { + if (hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO3 || + hwAsic->getAsicType() == cfg::AsicType::ASIC_TYPE_JERICHO4) { kbps = kCoppDnxLowPriKbitsPerSec; } else { kbps = getCoppQueueKbpsFromPps(hwAsic, pps); diff --git a/fboss/agent/test/utils/InvariantTestUtils.cpp b/fboss/agent/test/utils/InvariantTestUtils.cpp index cbcbe8039dc31..0cf0fbe804f68 100644 --- a/fboss/agent/test/utils/InvariantTestUtils.cpp +++ b/fboss/agent/test/utils/InvariantTestUtils.cpp @@ -46,6 +46,7 @@ void verifySafeDiagCmds(TestEnsembleIf* ensemble) { case cfg::AsicType::ASIC_TYPE_AGERA3: case cfg::AsicType::ASIC_TYPE_JERICHO2: case cfg::AsicType::ASIC_TYPE_JERICHO3: + case cfg::AsicType::ASIC_TYPE_JERICHO4: case cfg::AsicType::ASIC_TYPE_RAMON: case cfg::AsicType::ASIC_TYPE_RAMON3: case cfg::AsicType::ASIC_TYPE_TOMAHAWK5: diff --git a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON new file mode 100644 index 0000000000000..838a64b69f4da --- /dev/null +++ b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON @@ -0,0 +1,946 @@ +{ + "defaultCommandLineArgs": { + "check_wb_handles": "true", + "classid_for_unresolved_routes": "true", + "counter_refresh_interval": "0", + "enable_acl_table_group": "true", + "intf_nbr_tables": "true", + "log_variable_name": "true", + "sai_configure_six_tap": "true", + "set_classid_for_my_subnet_and_ip_routes": "true", + "skip_transceiver_programming": "true", + "use_full_dlb_scale": "true" + }, + "sw": { + "version": 0, + "ports": [], + "vlans": [], + "vlanPorts": [], + "defaultVlan": 0, + "interfaces": [ + { + "intfID": 11, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 1 + }, + { + "intfID": 17, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 1 + }, + { + "intfID": 16, + "routerID": 0, + "vlanID": 0, + "ipAddresses": [], + "mtu": 9000, + "isVirtual": false, + "isStateSyncDisabled": true, + "type": 2, + "scope": 0 + } + ], + "arpTimeoutSeconds": 60, + "arpRefreshSeconds": 20, + "arpAgerInterval": 5, + "proactiveArp": false, + "staticRoutesWithNhops": [], + "staticRoutesToNull": [], + "staticRoutesToCPU": [], + "acls": [], + "maxNeighborProbes": 300, + "staleEntryInterval": 10, + "aggregatePorts": [], + "clientIdToAdminDistance": { + "0": 20, + "1": 1, + "2": 0, + "3": 0, + "4": 0, + "700": 255, + "786": 10 + }, + "sFlowCollectors": [], + "cpuQueues": [], + "loadBalancers": [], + "mirrors": [], + "trafficCounters": [], + "qosPolicies": [], + "defaultPortQueues": [], + "staticMplsRoutesWithNhops": [], + "staticMplsRoutesToNull": [], + "staticMplsRoutesToCPU": [], + "staticIp2MplsRoutes": [], + "portQueueConfigs": {}, + "switchSettings": { + "l2LearningMode": 0, + "qcmEnable": false, + "ptpTcEnable": false, + "l2AgeTimerSeconds": 300, + "maxRouteCounterIDs": 0, + "blockNeighbors": [], + "macAddrsToBlock": [], + "switchType": 2, + "switchId": 0, + "exactMatchTableConfigs": [], + "switchIdToSwitchType_DEPRECATED": {}, + "switchDrainState": 0, + "switchIdToSwitchInfo": { + "0": { + "switchType": 2, + "asicType": 23, + "switchIndex": 0, + "portIdRange": { + "minimum": 0, + "maximum": 2047 + }, + "switchMac": "02:00:00:00:00:01", + "connectionHandle": "15:00", + "systemPortRanges": { + "systemPortRanges": [ + { + "minimum": 10, + "maximum": 53 + } + ] + }, + "localSystemPortOffset": 10, + "globalSystemPortOffset": 10, + "inbandPortId": 1 + } + }, + "vendorMacOuis": [], + "metaMacOuis": [], + "needL2EntryForNeighbor": true + }, + "aclTableGroup": { + "name": "acl-table-group-ingress", + "aclTables": [ + { + "name": "AclTable1", + "priority": 0, + "aclEntries": [], + "actionTypes": [], + "qualifiers": [], + "udfGroups": [] + } + ], + "stage": 0 + }, + "sdkVersion": { + "asicSdk": "sdk", + "saiSdk": "sai" + }, + "dsfNodes": { + "0": { + "name": "intfNode0", + "switchId": 0, + "type": 2, + "loopbackIps": [], + "nodeMac": "02:00:00:00:0F:0B", + "asicType": 23, + "platformType": 51, + "localSystemPortOffset": 10, + "globalSystemPortOffset": 10, + "systemPortRanges": { + "systemPortRanges": [ + { + "minimum": 10, + "maximum": 53 + } + ] + }, + "inbandPortId": 1, + "scheduling": 1000 + } + }, + "defaultVoqConfig": [], + "aclTableGroups": [ + { + "name": "acl-table-group-ingress", + "aclTables": [ + { + "name": "AclTable1", + "priority": 0, + "aclEntries": [], + "actionTypes": [], + "qualifiers": [], + "udfGroups": [] + } + ], + "stage": 0 + } + ], + "mirrorOnDropReports": [] + }, + "platform": { + "chip": { + "asicConfig": { + "common": { + "config": { + "appl_param_multi_cpu_agents": "0", + "dram_temperature_monitor_enable.BCM994EX": "0", + "ext_ram_enabled_bitmap.BCM994EX": "0", + "appl_param_oam_enable.BCM994EX": "0", + "appl_param_rcy_mirror_ports_range.BCM994EX": "100-170", + "bcm_stat_interval": "1000000", + "custom_feature_adapter_do_collect_enable.BCM994EX_ADAPTER": "1", + "custom_feature_cmicx_gen2_pdma_interface_optimization": "1", + "custom_feature_fabric_cgm_ddc_th_tune.BCM994EX": "1", + "custom_feature_programmability_standard_image_name.BCM994EX": "AI23", + "custom_feature_rx_fifo_monitoring_interval_ms": "200", + "custom_feature_ser_event_generate": "1", + "custom_feature_shel_arm_enable": "0", + "custom_feature_statdma_enable": "0", + "custom_feature_use_new_access.BCM994EX": "1", + "custom_feature_use_new_access.BCM994EX_ADAPTER": "1", + "custom_feature_vsqd_lossless_reject_enable": "1", + "customer_x_fap_ss": "1", + "deleted_buffers_file_path": "/tmp/dram_quarantine_deleted_buffers_file", + "dpp_db_path": "/root/brcmsim/tools/sand/db", + "dram_temperature_monitor_enable.BCM994EX_ADAPTER": "0", + "dtm_flow_mapping_mode_region_97.BCM994EX": "0", + "dtm_flow_mapping_mode_region_98.BCM994EX": "0", + "dtm_flow_mapping_mode_region_99.BCM994EX": "0", + "dtm_flow_mapping_mode_region_100.BCM994EX": "0", + "dtm_flow_mapping_mode_region_101.BCM994EX": "0", + "dtm_flow_mapping_mode_region_102.BCM994EX": "0", + "dtm_flow_mapping_mode_region_103.BCM994EX": "0", + "dtm_flow_mapping_mode_region_104.BCM994EX": "0", + "dtm_flow_mapping_mode_region_105.BCM994EX": "0", + "dtm_flow_mapping_mode_region_106.BCM994EX": "0", + "dtm_flow_mapping_mode_region_107.BCM994EX": "0", + "dtm_flow_mapping_mode_region_108.BCM994EX": "0", + "dtm_flow_mapping_mode_region_109.BCM994EX": "0", + "dtm_flow_mapping_mode_region_110.BCM994EX": "0", + "dtm_flow_mapping_mode_region_111.BCM994EX": "0", + "dtm_flow_mapping_mode_region_112.BCM994EX": "0", + "dtm_flow_mapping_mode_region_113.BCM994EX": "0", + "dtm_flow_mapping_mode_region_114.BCM994EX": "0", + "dtm_flow_mapping_mode_region_115.BCM994EX": "0", + "dtm_flow_mapping_mode_region_116.BCM994EX": "0", + "dtm_flow_mapping_mode_region_117.BCM994EX": "0", + "dtm_flow_mapping_mode_region_118.BCM994EX": "0", + "dtm_flow_mapping_mode_region_119.BCM994EX": "0", + "dtm_flow_mapping_mode_region_120.BCM994EX": "0", + "dtm_flow_nof_remote_cores_region.BCM994EX": "8", + "eventor_sbus_dma_channels.BCM994EX": "0,6,0,7", + "fail_on_unsupported_attribute": "1", + "l3_ecmp_max_group_size": "512", + "macro_flow_hash_shuffle_random_seed": "34345645", + "maximal_port_bandwidth.BCM994EX": "1000000", + "mdb_profile.BCM994EX": "Elastic-Balanced", + "mem_cache_enable_all.BCM994EX_ADAPTER": "1", + "outlif_logical_to_physical_phase_map_1.BCM994EX": "S1", + "outlif_logical_to_physical_phase_map_2.BCM994EX": "L1", + "outlif_logical_to_physical_phase_map_3.BCM994EX": "S2", + "outlif_logical_to_physical_phase_map_4.BCM994EX": "L2", + "outlif_logical_to_physical_phase_map_5.BCM994EX": "M1", + "outlif_logical_to_physical_phase_map_6.BCM994EX": "M2", + "outlif_logical_to_physical_phase_map_7.BCM994EX": "M3", + "outlif_logical_to_physical_phase_map_8.BCM994EX": "XL", + "outlif_physical_phase_data_granularity_L1.BCM994EX": "60", + "outlif_physical_phase_data_granularity_L2.BCM994EX": "60", + "outlif_physical_phase_data_granularity_M1.BCM994EX": "60", + "outlif_physical_phase_data_granularity_M2.BCM994EX": "60", + "outlif_physical_phase_data_granularity_M3.BCM994EX": "60", + "outlif_physical_phase_data_granularity_S1.BCM994EX": "60", + "outlif_physical_phase_data_granularity_S2.BCM994EX": "60", + "outlif_physical_phase_data_granularity_XL.BCM994EX": "60", + "pci_override_dev": "0x94E0", + "AI23_mode": "4", + "pcie_host_intf_timeout_purge_enable": "0", + "perform_system_reset_when_needed": "1", + "phy_rx_polarity_flip.BCM994EX": "0", + "phy_tx_polarity_flip.BCM994EX": "0", + "pktio_driver_type": "1", + "pmf_maps_payload_size.BCM994EX": "30", + "pmf_nexem2_stage": "IPMF3", + "polled_irq_delay.BCM994EX_ADAPTER": "200000", + "polled_irq_mode.BCM994EX_ADAPTER": "1", + "port_fec_cc": "9", + "port_init_speed_cc.BCM994EX": "200000", + "port_init_speed_cd.BCM994EX": "400000", + "port_init_speed_ce.BCM994EX": "100000", + "port_init_speed_d3c.BCM994EX": "800000", + "port_init_speed_eventor.BCM994EX": "100000", + "port_init_speed_fabric.BCM994EX": "212500", + "port_init_speed_le.BCM994EX": "50000", + "port_init_speed_rcy.BCM994EX": "100000", + "port_init_speed_sat.BCM994EX": "400000", + "port_init_speed_xe.BCM994EX": "25000", + "port_init_speed_xe13.BCM994EX": "10000", + "port_init_speed_xe14.BCM994EX": "10000", + "port_init_speed_xe15.BCM994EX": "10000", + "port_init_speed_xe16.BCM994EX": "10000", + "port_init_speed_xl.BCM994EX": "40000", + "port_priorities": "8", + "port_priorities_cpu": "2", + "port_priorities_rcy": "2", + "port_priorities_sch.BCM994EX": "8", + "programmability_image_name.BCM994EX": "AI23", + "programmability_ucode_relative_path.BCM994EX": "pemla/ucode/AI23/jr3native/u_code_db2pem.txt", + "qos_map_multi_get_mode": "1", + "rif_id_max": "0x2000", + "sai_dis_ctr_incr_on_port_ln_dn": "0", + "sai_disable_srcmacqedstmac_ctrl": "0x1", + "sai_eventor_port_lane_base": "1000", + "sai_global_scoped_rcy_port": "8", + "sai_l3_max_ecmp_paths": "512", + "sai_ocb_fc_config": "2", + "sai_pfc_defaults_disable": "0x1", + "sai_recycle_port_lane_base": "512", + "sai_tc_mirror_buffer_size_bytes": "1", + "sai_trigger_linkscan_remote_local_faults": "1", + "sai_uncached_port_stats": "0x1", + "sai_voq_wm_latency_enable": "1", + "sat_enable.BCM994EX_ADAPTER": "1", + "soc_family.BCM994EX": "BCM994EX", + "stable_location.BCM994EX": "4", + "stable_location.BCM994EX_ADAPTER": "4", + "stable_size": "1450000000", + "sw_state_max_size": "1400000000", + "tm_port_header_type_in_0.BCM994EX": "INJECTED", + "tm_port_header_type_in_1.BCM994EX": "INJECTED", + "tm_port_header_type_in_2.BCM994EX": "INJECTED", + "tm_port_header_type_in_3.BCM994EX": "INJECTED", + "tm_port_header_type_in_4.BCM994EX": "INJECTED", + "tm_port_header_type_in_5.BCM994EX": "INJECTED", + "tm_port_header_type_in_6.BCM994EX": "INJECTED", + "tm_port_header_type_in_7.BCM994EX": "INJECTED", + "tm_port_header_type_in_9.BCM994EX": "INJECTED", + "tm_port_header_type_in_10.BCM994EX": "INJECTED", + "ucode_port_240.BCM994EX": "OLP0:core_0.240", + "ucode_port_241.BCM994EX": "OLP1:core_0.241", + "ucode_port_0.BCM994EX": "CPU.0:core_0.0:datapath_0", + "ucode_port_1.BCM994EX": "CPU.8:core_0.1:datapath_1", + "ucode_port_2.BCM994EX": "CPU.16:core_0.2:datapath_0", + "ucode_port_3.BCM994EX": "CPU.24:core_1.0:datapath_0", + "ucode_port_4.BCM994EX": "CPU.32:core_1.1:datapath_1", + "ucode_port_5.BCM994EX": "CPU.40:core_2.0:datapath_0", + "ucode_port_6.BCM994EX": "CPU.48:core_2.1:datapath_1", + "ucode_port_7.BCM994EX": "CPU.56:core_3.0:datapath_0", + "ucode_port_8.BCM994EX": "CPU.64:core_3.1:datapath_1", + "ucode_port_9.BCM994EX": "CPU.72:core_4.0:datapath_0", + "ucode_port_10.BCM994EX": "CPU.80:core_4.1:datapath_1", + "ucode_port_11.BCM994EX": "CPU.88:core_5.0:datapath_0", + "ucode_port_12.BCM994EX": "CPU.96:core_5.1:datapath_1", + "ucode_port_13.BCM994EX": "CPU.104:core_6.0:datapath_0", + "ucode_port_14.BCM994EX": "CPU.112:core_6.1:datapath_1", + "ucode_port_15.BCM994EX": "CPU.120:core_7.0:datapath_0", + "ucode_port_16.BCM994EX": "CPU.128:core_7.1:datapath_1", + "ucode_port_17.BCM994EX": "RCY.0:core_0.3:datapath_0", + "ucode_port_18.BCM994EX": "RCY.8:core_0.4:datapath_1", + "ucode_port_19.BCM994EX": "RCY.16:core_1.2:datapath_0", + "ucode_port_20.BCM994EX": "RCY.24:core_1.3:datapath_1", + "ucode_port_21.BCM994EX": "RCY.32:core_2.2:datapath_0", + "ucode_port_22.BCM994EX": "RCY.40:core_2.3:datapath_1", + "ucode_port_23.BCM994EX": "RCY.48:core_3.2:datapath_0", + "ucode_port_24.BCM994EX": "RCY.56:core_3.3:datapath_1", + "ucode_port_25.BCM994EX": "RCY.64:core_4.2:datapath_0", + "ucode_port_26.BCM994EX": "RCY.72:core_4.3:datapath_1", + "ucode_port_27.BCM994EX": "RCY.80:core_5.2:datapath_0", + "ucode_port_28.BCM994EX": "RCY.88:core_5.3:datapath_1", + "ucode_port_29.BCM994EX": "RCY.96:core_6.2:datapath_0", + "ucode_port_30.BCM994EX": "RCY.104:core_6.3:datapath_1", + "ucode_port_31.BCM994EX": "RCY.112:core_7.2:datapath_0", + "ucode_port_32.BCM994EX": "RCY.120:core_7.3:datapath_1", + "ucode_port_33.BCM994EX": "EVENTOR:core_0.6:datapath_0", + "ucode_port_34.BCM994EX": "EVENTOR:core_4.4:datapath_0", + "ucode_port_35.BCM994EX": "D3CE.0:core_0.7:datapath_0", + "ucode_port_36.BCM994EX": "D3CE.1:core_0.8:datapath_0", + "ucode_port_37.BCM994EX": "D3CE.2:core_0.9:datapath_0", + "ucode_port_38.BCM994EX": "D3CE.3:core_0.10:datapath_0", + "ucode_port_39.BCM994EX": "D3CE.4:core_0.11:datapath_1", + "ucode_port_40.BCM994EX": "D3CE.5:core_0.12:datapath_1", + "ucode_port_41.BCM994EX": "D3CE.6:core_0.13:datapath_1", + "ucode_port_42.BCM994EX": "D3CE.7:core_0.14:datapath_1", + "ucode_port_43.BCM994EX": "D3CE.8:core_1.4:datapath_0", + "ucode_port_44.BCM994EX": "D3CE.9:core_1.5:datapath_0", + "ucode_port_45.BCM994EX": "D3CE.10:core_1.6:datapath_0", + "ucode_port_46.BCM994EX": "D3CE.11:core_1.7:datapath_0", + "ucode_port_47.BCM994EX": "D3CE.12:core_1.8:datapath_1", + "ucode_port_48.BCM994EX": "D3CE.13:core_1.9:datapath_1", + "ucode_port_49.BCM994EX": "D3CE.14:core_1.10:datapath_1", + "ucode_port_50.BCM994EX": "D3CE.15:core_1.11:datapath_1", + "ucode_port_51.BCM994EX": "D3CE.16:core_2.4:datapath_0", + "ucode_port_52.BCM994EX": "D3CE.17:core_2.5:datapath_0", + "ucode_port_53.BCM994EX": "D3CE.18:core_2.6:datapath_0", + "ucode_port_54.BCM994EX": "D3CE.19:core_2.7:datapath_0", + "ucode_port_55.BCM994EX": "D3CE.20:core_2.8:datapath_1", + "ucode_port_56.BCM994EX": "D3CE.21:core_2.9:datapath_1", + "ucode_port_57.BCM994EX": "D3CE.22:core_2.10:datapath_1", + "ucode_port_58.BCM994EX": "D3CE.23:core_2.11:datapath_1", + "ucode_port_59.BCM994EX": "D3CE.24:core_3.4:datapath_0", + "ucode_port_60.BCM994EX": "D3CE.25:core_3.5:datapath_0", + "ucode_port_61.BCM994EX": "D3CE.26:core_3.6:datapath_0", + "ucode_port_62.BCM994EX": "D3CE.27:core_3.7:datapath_0", + "ucode_port_63.BCM994EX": "D3CE.28:core_3.8:datapath_1", + "ucode_port_64.BCM994EX": "D3CE.29:core_3.9:datapath_1", + "ucode_port_65.BCM994EX": "D3CE.30:core_3.10:datapath_1", + "ucode_port_66.BCM994EX": "D3CE.31:core_3.11:datapath_1", + "ucode_port_67.BCM994EX": "D3CE.32:core_4.5:datapath_0", + "ucode_port_68.BCM994EX": "D3CE.33:core_4.6:datapath_0", + "ucode_port_69.BCM994EX": "D3CE.34:core_4.7:datapath_0", + "ucode_port_70.BCM994EX": "D3CE.35:core_4.8:datapath_0", + "ucode_port_71.BCM994EX": "D3CE.36:core_4.9:datapath_1", + "ucode_port_72.BCM994EX": "D3CE.37:core_4.10:datapath_1", + "ucode_port_73.BCM994EX": "D3CE.38:core_4.11:datapath_1", + "ucode_port_74.BCM994EX": "D3CE.39:core_4.12:datapath_1", + "ucode_port_75.BCM994EX": "D3CE.40:core_5.4:datapath_0", + "ucode_port_76.BCM994EX": "D3CE.41:core_5.5:datapath_0", + "ucode_port_77.BCM994EX": "D3CE.42:core_5.6:datapath_0", + "ucode_port_78.BCM994EX": "D3CE.43:core_5.7:datapath_0", + "ucode_port_79.BCM994EX": "D3CE.44:core_5.8:datapath_1", + "ucode_port_80.BCM994EX": "D3CE.45:core_5.9:datapath_1", + "ucode_port_81.BCM994EX": "D3CE.46:core_5.10:datapath_1", + "ucode_port_82.BCM994EX": "D3CE.47:core_5.11:datapath_1", + "ucode_port_83.BCM994EX": "D3CE.48:core_6.4:datapath_0", + "ucode_port_84.BCM994EX": "D3CE.49:core_6.5:datapath_0", + "ucode_port_85.BCM994EX": "D3CE.50:core_6.6:datapath_0", + "ucode_port_86.BCM994EX": "D3CE.51:core_6.7:datapath_0", + "ucode_port_87.BCM994EX": "D3CE.52:core_6.8:datapath_1", + "ucode_port_88.BCM994EX": "D3CE.53:core_6.9:datapath_1", + "ucode_port_89.BCM994EX": "D3CE.54:core_6.10:datapath_1", + "ucode_port_90.BCM994EX": "D3CE.55:core_6.11:datapath_1", + "ucode_port_91.BCM994EX": "D3CE.56:core_7.4:datapath_0", + "ucode_port_92.BCM994EX": "D3CE.57:core_7.5:datapath_0", + "ucode_port_93.BCM994EX": "D3CE.58:core_7.6:datapath_0", + "ucode_port_94.BCM994EX": "D3CE.59:core_7.7:datapath_0", + "ucode_port_95.BCM994EX": "D3CE.60:core_7.8:datapath_1", + "ucode_port_96.BCM994EX": "D3CE.61:core_7.9:datapath_1", + "ucode_port_97.BCM994EX": "D3CE.62:core_7.10:datapath_1", + "ucode_port_98.BCM994EX": "D3CE.63:core_7.11:datapath_1", + "lane_to_serdes_map_nif_lane0": "rx0:tx0", + "lane_to_serdes_map_nif_lane1": "rx1:tx1", + "lane_to_serdes_map_nif_lane2": "rx2:tx2", + "lane_to_serdes_map_nif_lane3": "rx3:tx3", + "lane_to_serdes_map_nif_lane4": "rx4:tx4", + "lane_to_serdes_map_nif_lane5": "rx5:tx5", + "lane_to_serdes_map_nif_lane6": "rx6:tx6", + "lane_to_serdes_map_nif_lane7": "rx7:tx7", + "lane_to_serdes_map_nif_lane8": "rx8:tx8", + "lane_to_serdes_map_nif_lane9": "rx9:tx9", + "lane_to_serdes_map_nif_lane10": "rx10:tx10", + "lane_to_serdes_map_nif_lane11": "rx11:tx11", + "lane_to_serdes_map_nif_lane12": "rx12:tx12", + "lane_to_serdes_map_nif_lane13": "rx13:tx13", + "lane_to_serdes_map_nif_lane14": "rx14:tx14", + "lane_to_serdes_map_nif_lane15": "rx15:tx15", + "lane_to_serdes_map_nif_lane16": "rx16:tx16", + "lane_to_serdes_map_nif_lane17": "rx17:tx17", + "lane_to_serdes_map_nif_lane18": "rx18:tx18", + "lane_to_serdes_map_nif_lane19": "rx19:tx19", + "lane_to_serdes_map_nif_lane20": "rx20:tx20", + "lane_to_serdes_map_nif_lane21": "rx21:tx21", + "lane_to_serdes_map_nif_lane22": "rx22:tx22", + "lane_to_serdes_map_nif_lane23": "rx23:tx23", + "lane_to_serdes_map_nif_lane24": "rx24:tx24", + "lane_to_serdes_map_nif_lane25": "rx25:tx25", + "lane_to_serdes_map_nif_lane26": "rx26:tx26", + "lane_to_serdes_map_nif_lane27": "rx27:tx27", + "lane_to_serdes_map_nif_lane28": "rx28:tx28", + "lane_to_serdes_map_nif_lane29": "rx29:tx29", + "lane_to_serdes_map_nif_lane30": "rx30:tx30", + "lane_to_serdes_map_nif_lane31": "rx31:tx31", + "lane_to_serdes_map_nif_lane32": "rx32:tx32", + "lane_to_serdes_map_nif_lane33": "rx33:tx33", + "lane_to_serdes_map_nif_lane34": "rx34:tx34", + "lane_to_serdes_map_nif_lane35": "rx35:tx35", + "lane_to_serdes_map_nif_lane36": "rx36:tx36", + "lane_to_serdes_map_nif_lane37": "rx37:tx37", + "lane_to_serdes_map_nif_lane38": "rx38:tx38", + "lane_to_serdes_map_nif_lane39": "rx39:tx39", + "lane_to_serdes_map_nif_lane40": "rx40:tx40", + "lane_to_serdes_map_nif_lane41": "rx41:tx41", + "lane_to_serdes_map_nif_lane42": "rx42:tx42", + "lane_to_serdes_map_nif_lane43": "rx43:tx43", + "lane_to_serdes_map_nif_lane44": "rx44:tx44", + "lane_to_serdes_map_nif_lane45": "rx45:tx45", + "lane_to_serdes_map_nif_lane46": "rx46:tx46", + "lane_to_serdes_map_nif_lane47": "rx47:tx47", + "lane_to_serdes_map_nif_lane48": "rx48:tx48", + "lane_to_serdes_map_nif_lane49": "rx49:tx49", + "lane_to_serdes_map_nif_lane50": "rx50:tx50", + "lane_to_serdes_map_nif_lane51": "rx51:tx51", + "lane_to_serdes_map_nif_lane52": "rx52:tx52", + "lane_to_serdes_map_nif_lane53": "rx53:tx53", + "lane_to_serdes_map_nif_lane54": "rx54:tx54", + "lane_to_serdes_map_nif_lane55": "rx55:tx55", + "lane_to_serdes_map_nif_lane56": "rx56:tx56", + "lane_to_serdes_map_nif_lane57": "rx57:tx57", + "lane_to_serdes_map_nif_lane58": "rx58:tx58", + "lane_to_serdes_map_nif_lane59": "rx59:tx59", + "lane_to_serdes_map_nif_lane60": "rx60:tx60", + "lane_to_serdes_map_nif_lane61": "rx61:tx61", + "lane_to_serdes_map_nif_lane62": "rx62:tx62", + "lane_to_serdes_map_nif_lane63": "rx63:tx63", + "lane_to_serdes_map_nif_lane64": "rx64:tx64", + "lane_to_serdes_map_nif_lane65": "rx65:tx65", + "lane_to_serdes_map_nif_lane66": "rx66:tx66", + "lane_to_serdes_map_nif_lane67": "rx67:tx67", + "lane_to_serdes_map_nif_lane68": "rx68:tx68", + "lane_to_serdes_map_nif_lane69": "rx69:tx69", + "lane_to_serdes_map_nif_lane70": "rx70:tx70", + "lane_to_serdes_map_nif_lane71": "rx71:tx71", + "lane_to_serdes_map_nif_lane72": "rx72:tx72", + "lane_to_serdes_map_nif_lane73": "rx73:tx73", + "lane_to_serdes_map_nif_lane74": "rx74:tx74", + "lane_to_serdes_map_nif_lane75": "rx75:tx75", + "lane_to_serdes_map_nif_lane76": "rx76:tx76", + "lane_to_serdes_map_nif_lane77": "rx77:tx77", + "lane_to_serdes_map_nif_lane78": "rx78:tx78", + "lane_to_serdes_map_nif_lane79": "rx79:tx79", + "lane_to_serdes_map_nif_lane80": "rx80:tx80", + "lane_to_serdes_map_nif_lane81": "rx81:tx81", + "lane_to_serdes_map_nif_lane82": "rx82:tx82", + "lane_to_serdes_map_nif_lane83": "rx83:tx83", + "lane_to_serdes_map_nif_lane84": "rx84:tx84", + "lane_to_serdes_map_nif_lane85": "rx85:tx85", + "lane_to_serdes_map_nif_lane86": "rx86:tx86", + "lane_to_serdes_map_nif_lane87": "rx87:tx87", + "lane_to_serdes_map_nif_lane88": "rx88:tx88", + "lane_to_serdes_map_nif_lane89": "rx89:tx89", + "lane_to_serdes_map_nif_lane90": "rx90:tx90", + "lane_to_serdes_map_nif_lane91": "rx91:tx91", + "lane_to_serdes_map_nif_lane92": "rx92:tx92", + "lane_to_serdes_map_nif_lane93": "rx93:tx93", + "lane_to_serdes_map_nif_lane94": "rx94:tx94", + "lane_to_serdes_map_nif_lane95": "rx95:tx95", + "lane_to_serdes_map_nif_lane96": "rx96:tx96", + "lane_to_serdes_map_nif_lane97": "rx97:tx97", + "lane_to_serdes_map_nif_lane98": "rx98:tx98", + "lane_to_serdes_map_nif_lane99": "rx99:tx99", + "lane_to_serdes_map_nif_lane100": "rx100:tx100", + "lane_to_serdes_map_nif_lane101": "rx101:tx101", + "lane_to_serdes_map_nif_lane102": "rx102:tx102", + "lane_to_serdes_map_nif_lane103": "rx103:tx103", + "lane_to_serdes_map_nif_lane104": "rx104:tx104", + "lane_to_serdes_map_nif_lane105": "rx105:tx105", + "lane_to_serdes_map_nif_lane106": "rx106:tx106", + "lane_to_serdes_map_nif_lane107": "rx107:tx107", + "lane_to_serdes_map_nif_lane108": "rx108:tx108", + "lane_to_serdes_map_nif_lane109": "rx109:tx109", + "lane_to_serdes_map_nif_lane110": "rx110:tx110", + "lane_to_serdes_map_nif_lane111": "rx111:tx111", + "lane_to_serdes_map_nif_lane112": "rx112:tx112", + "lane_to_serdes_map_nif_lane113": "rx113:tx113", + "lane_to_serdes_map_nif_lane114": "rx114:tx114", + "lane_to_serdes_map_nif_lane115": "rx115:tx115", + "lane_to_serdes_map_nif_lane116": "rx116:tx116", + "lane_to_serdes_map_nif_lane117": "rx117:tx117", + "lane_to_serdes_map_nif_lane118": "rx118:tx118", + "lane_to_serdes_map_nif_lane119": "rx119:tx119", + "lane_to_serdes_map_nif_lane120": "rx120:tx120", + "lane_to_serdes_map_nif_lane121": "rx121:tx121", + "lane_to_serdes_map_nif_lane122": "rx122:tx122", + "lane_to_serdes_map_nif_lane123": "rx123:tx123", + "lane_to_serdes_map_nif_lane124": "rx124:tx124", + "lane_to_serdes_map_nif_lane125": "rx125:tx125", + "lane_to_serdes_map_nif_lane126": "rx126:tx126", + "lane_to_serdes_map_nif_lane127": "rx127:tx127", + "lane_to_serdes_map_nif_lane128": "rx128:tx128", + "lane_to_serdes_map_nif_lane129": "rx129:tx129", + "lane_to_serdes_map_nif_lane130": "rx130:tx130", + "lane_to_serdes_map_nif_lane131": "rx131:tx131", + "lane_to_serdes_map_nif_lane132": "rx132:tx132", + "lane_to_serdes_map_nif_lane133": "rx133:tx133", + "lane_to_serdes_map_nif_lane134": "rx134:tx134", + "lane_to_serdes_map_nif_lane135": "rx135:tx135", + "lane_to_serdes_map_nif_lane136": "rx136:tx136", + "lane_to_serdes_map_nif_lane137": "rx137:tx137", + "lane_to_serdes_map_nif_lane138": "rx138:tx138", + "lane_to_serdes_map_nif_lane139": "rx139:tx139", + "lane_to_serdes_map_nif_lane140": "rx140:tx140", + "lane_to_serdes_map_nif_lane141": "rx141:tx141", + "lane_to_serdes_map_nif_lane142": "rx142:tx142", + "lane_to_serdes_map_nif_lane143": "rx143:tx143", + "lane_to_serdes_map_nif_lane144": "rx144:tx144", + "lane_to_serdes_map_nif_lane145": "rx145:tx145", + "lane_to_serdes_map_nif_lane146": "rx146:tx146", + "lane_to_serdes_map_nif_lane147": "rx147:tx147", + "lane_to_serdes_map_nif_lane148": "rx148:tx148", + "lane_to_serdes_map_nif_lane149": "rx149:tx149", + "lane_to_serdes_map_nif_lane150": "rx150:tx150", + "lane_to_serdes_map_nif_lane151": "rx151:tx151", + "lane_to_serdes_map_nif_lane152": "rx152:tx152", + "lane_to_serdes_map_nif_lane153": "rx153:tx153", + "lane_to_serdes_map_nif_lane154": "rx154:tx154", + "lane_to_serdes_map_nif_lane155": "rx155:tx155", + "lane_to_serdes_map_nif_lane156": "rx156:tx156", + "lane_to_serdes_map_nif_lane157": "rx157:tx157", + "lane_to_serdes_map_nif_lane158": "rx158:tx158", + "lane_to_serdes_map_nif_lane159": "rx159:tx159", + "lane_to_serdes_map_nif_lane160": "rx160:tx160", + "lane_to_serdes_map_nif_lane161": "rx161:tx161", + "lane_to_serdes_map_nif_lane162": "rx162:tx162", + "lane_to_serdes_map_nif_lane163": "rx163:tx163", + "lane_to_serdes_map_nif_lane164": "rx164:tx164", + "lane_to_serdes_map_nif_lane165": "rx165:tx165", + "lane_to_serdes_map_nif_lane166": "rx166:tx166", + "lane_to_serdes_map_nif_lane167": "rx167:tx167", + "lane_to_serdes_map_nif_lane168": "rx168:tx168", + "lane_to_serdes_map_nif_lane169": "rx169:tx169", + "lane_to_serdes_map_nif_lane170": "rx170:tx170", + "lane_to_serdes_map_nif_lane171": "rx171:tx171", + "lane_to_serdes_map_nif_lane172": "rx172:tx172", + "lane_to_serdes_map_nif_lane173": "rx173:tx173", + "lane_to_serdes_map_nif_lane174": "rx174:tx174", + "lane_to_serdes_map_nif_lane175": "rx175:tx175", + "lane_to_serdes_map_nif_lane176": "rx176:tx176", + "lane_to_serdes_map_nif_lane177": "rx177:tx177", + "lane_to_serdes_map_nif_lane178": "rx178:tx178", + "lane_to_serdes_map_nif_lane179": "rx179:tx179", + "lane_to_serdes_map_nif_lane180": "rx180:tx180", + "lane_to_serdes_map_nif_lane181": "rx181:tx181", + "lane_to_serdes_map_nif_lane182": "rx182:tx182", + "lane_to_serdes_map_nif_lane183": "rx183:tx183", + "lane_to_serdes_map_nif_lane184": "rx184:tx184", + "lane_to_serdes_map_nif_lane185": "rx185:tx185", + "lane_to_serdes_map_nif_lane186": "rx186:tx186", + "lane_to_serdes_map_nif_lane187": "rx187:tx187", + "lane_to_serdes_map_nif_lane188": "rx188:tx188", + "lane_to_serdes_map_nif_lane189": "rx189:tx189", + "lane_to_serdes_map_nif_lane190": "rx190:tx190", + "lane_to_serdes_map_nif_lane191": "rx191:tx191", + "lane_to_serdes_map_nif_lane192": "rx192:tx192", + "lane_to_serdes_map_nif_lane193": "rx193:tx193", + "lane_to_serdes_map_nif_lane194": "rx194:tx194", + "lane_to_serdes_map_nif_lane195": "rx195:tx195", + "lane_to_serdes_map_nif_lane196": "rx196:tx196", + "lane_to_serdes_map_nif_lane197": "rx197:tx197", + "lane_to_serdes_map_nif_lane198": "rx198:tx198", + "lane_to_serdes_map_nif_lane199": "rx199:tx199", + "lane_to_serdes_map_nif_lane200": "rx200:tx200", + "lane_to_serdes_map_nif_lane201": "rx201:tx201", + "lane_to_serdes_map_nif_lane202": "rx202:tx202", + "lane_to_serdes_map_nif_lane203": "rx203:tx203", + "lane_to_serdes_map_nif_lane204": "rx204:tx204", + "lane_to_serdes_map_nif_lane205": "rx205:tx205", + "lane_to_serdes_map_nif_lane206": "rx206:tx206", + "lane_to_serdes_map_nif_lane207": "rx207:tx207", + "lane_to_serdes_map_nif_lane208": "rx208:tx208", + "lane_to_serdes_map_nif_lane209": "rx209:tx209", + "lane_to_serdes_map_nif_lane210": "rx210:tx210", + "lane_to_serdes_map_nif_lane211": "rx211:tx211", + "lane_to_serdes_map_nif_lane212": "rx212:tx212", + "lane_to_serdes_map_nif_lane213": "rx213:tx213", + "lane_to_serdes_map_nif_lane214": "rx214:tx214", + "lane_to_serdes_map_nif_lane215": "rx215:tx215", + "lane_to_serdes_map_nif_lane216": "rx216:tx216", + "lane_to_serdes_map_nif_lane217": "rx217:tx217", + "lane_to_serdes_map_nif_lane218": "rx218:tx218", + "lane_to_serdes_map_nif_lane219": "rx219:tx219", + "lane_to_serdes_map_nif_lane220": "rx220:tx220", + "lane_to_serdes_map_nif_lane221": "rx221:tx221", + "lane_to_serdes_map_nif_lane222": "rx222:tx222", + "lane_to_serdes_map_nif_lane223": "rx223:tx223", + "lane_to_serdes_map_nif_lane224": "rx224:tx224", + "lane_to_serdes_map_nif_lane225": "rx225:tx225", + "lane_to_serdes_map_nif_lane226": "rx226:tx226", + "lane_to_serdes_map_nif_lane227": "rx227:tx227", + "lane_to_serdes_map_nif_lane228": "rx228:tx228", + "lane_to_serdes_map_nif_lane229": "rx229:tx229", + "lane_to_serdes_map_nif_lane230": "rx230:tx230", + "lane_to_serdes_map_nif_lane231": "rx231:tx231", + "lane_to_serdes_map_nif_lane232": "rx232:tx232", + "lane_to_serdes_map_nif_lane233": "rx233:tx233", + "lane_to_serdes_map_nif_lane234": "rx234:tx234", + "lane_to_serdes_map_nif_lane235": "rx235:tx235", + "lane_to_serdes_map_nif_lane236": "rx236:tx236", + "lane_to_serdes_map_nif_lane237": "rx237:tx237", + "lane_to_serdes_map_nif_lane238": "rx238:tx238", + "lane_to_serdes_map_nif_lane239": "rx239:tx239", + "lane_to_serdes_map_nif_lane240": "rx240:tx240", + "lane_to_serdes_map_nif_lane241": "rx241:tx241", + "lane_to_serdes_map_nif_lane242": "rx242:tx242", + "lane_to_serdes_map_nif_lane243": "rx243:tx243", + "lane_to_serdes_map_nif_lane244": "rx244:tx244", + "lane_to_serdes_map_nif_lane245": "rx245:tx245", + "lane_to_serdes_map_nif_lane246": "rx246:tx246", + "lane_to_serdes_map_nif_lane247": "rx247:tx247", + "lane_to_serdes_map_nif_lane248": "rx248:tx248", + "lane_to_serdes_map_nif_lane249": "rx249:tx249", + "lane_to_serdes_map_nif_lane250": "rx250:tx250", + "lane_to_serdes_map_nif_lane251": "rx251:tx251", + "lane_to_serdes_map_nif_lane252": "rx252:tx252", + "lane_to_serdes_map_nif_lane253": "rx253:tx253", + "lane_to_serdes_map_nif_lane254": "rx254:tx254", + "lane_to_serdes_map_nif_lane255": "rx255:tx255", + "lane_to_serdes_map_nif_lane256": "rx256:tx256", + "lane_to_serdes_map_nif_lane257": "rx257:tx257", + "lane_to_serdes_map_nif_lane258": "rx258:tx258", + "lane_to_serdes_map_nif_lane259": "rx259:tx259", + "lane_to_serdes_map_nif_lane260": "rx260:tx260", + "lane_to_serdes_map_nif_lane261": "rx261:tx261", + "lane_to_serdes_map_nif_lane262": "rx262:tx262", + "lane_to_serdes_map_nif_lane263": "rx263:tx263", + "lane_to_serdes_map_nif_lane264": "rx264:tx264", + "lane_to_serdes_map_nif_lane265": "rx265:tx265", + "lane_to_serdes_map_nif_lane266": "rx266:tx266", + "lane_to_serdes_map_nif_lane267": "rx267:tx267", + "lane_to_serdes_map_nif_lane268": "rx268:tx268", + "lane_to_serdes_map_nif_lane269": "rx269:tx269", + "lane_to_serdes_map_nif_lane270": "rx270:tx270", + "lane_to_serdes_map_nif_lane271": "rx271:tx271", + "lane_to_serdes_map_nif_lane272": "rx272:tx272", + "lane_to_serdes_map_nif_lane273": "rx273:tx273", + "lane_to_serdes_map_nif_lane274": "rx274:tx274", + "lane_to_serdes_map_nif_lane275": "rx275:tx275", + "lane_to_serdes_map_nif_lane276": "rx276:tx276", + "lane_to_serdes_map_nif_lane277": "rx277:tx277", + "lane_to_serdes_map_nif_lane278": "rx278:tx278", + "lane_to_serdes_map_nif_lane279": "rx279:tx279", + "lane_to_serdes_map_nif_lane280": "rx280:tx280", + "lane_to_serdes_map_nif_lane281": "rx281:tx281", + "lane_to_serdes_map_nif_lane282": "rx282:tx282", + "lane_to_serdes_map_nif_lane283": "rx283:tx283", + "lane_to_serdes_map_nif_lane284": "rx284:tx284", + "lane_to_serdes_map_nif_lane285": "rx285:tx285", + "lane_to_serdes_map_nif_lane286": "rx286:tx286", + "lane_to_serdes_map_nif_lane287": "rx287:tx287", + "lane_to_serdes_map_nif_lane288": "rx288:tx288", + "lane_to_serdes_map_nif_lane289": "rx289:tx289", + "lane_to_serdes_map_nif_lane290": "rx290:tx290", + "lane_to_serdes_map_nif_lane291": "rx291:tx291", + "lane_to_serdes_map_nif_lane292": "rx292:tx292", + "lane_to_serdes_map_nif_lane293": "rx293:tx293", + "lane_to_serdes_map_nif_lane294": "rx294:tx294", + "lane_to_serdes_map_nif_lane295": "rx295:tx295", + "lane_to_serdes_map_nif_lane296": "rx296:tx296", + "lane_to_serdes_map_nif_lane297": "rx297:tx297", + "lane_to_serdes_map_nif_lane298": "rx298:tx298", + "lane_to_serdes_map_nif_lane299": "rx299:tx299", + "lane_to_serdes_map_nif_lane300": "rx300:tx300", + "lane_to_serdes_map_nif_lane301": "rx301:tx301", + "lane_to_serdes_map_nif_lane302": "rx302:tx302", + "lane_to_serdes_map_nif_lane303": "rx303:tx303", + "lane_to_serdes_map_nif_lane304": "rx304:tx304", + "lane_to_serdes_map_nif_lane305": "rx305:tx305", + "lane_to_serdes_map_nif_lane306": "rx306:tx306", + "lane_to_serdes_map_nif_lane307": "rx307:tx307", + "lane_to_serdes_map_nif_lane308": "rx308:tx308", + "lane_to_serdes_map_nif_lane309": "rx309:tx309", + "lane_to_serdes_map_nif_lane310": "rx310:tx310", + "lane_to_serdes_map_nif_lane311": "rx311:tx311", + "lane_to_serdes_map_nif_lane312": "rx312:tx312", + "lane_to_serdes_map_nif_lane313": "rx313:tx313", + "lane_to_serdes_map_nif_lane314": "rx314:tx314", + "lane_to_serdes_map_nif_lane315": "rx315:tx315", + "lane_to_serdes_map_nif_lane316": "rx316:tx316", + "lane_to_serdes_map_nif_lane317": "rx317:tx317", + "lane_to_serdes_map_nif_lane318": "rx318:tx318", + "lane_to_serdes_map_nif_lane319": "rx319:tx319", + "lane_to_serdes_map_nif_lane320": "rx320:tx320", + "lane_to_serdes_map_nif_lane321": "rx321:tx321", + "lane_to_serdes_map_nif_lane322": "rx322:tx322", + "lane_to_serdes_map_nif_lane323": "rx323:tx323", + "lane_to_serdes_map_nif_lane324": "rx324:tx324", + "lane_to_serdes_map_nif_lane325": "rx325:tx325", + "lane_to_serdes_map_nif_lane326": "rx326:tx326", + "lane_to_serdes_map_nif_lane327": "rx327:tx327", + "lane_to_serdes_map_nif_lane328": "rx328:tx328", + "lane_to_serdes_map_nif_lane329": "rx329:tx329", + "lane_to_serdes_map_nif_lane330": "rx330:tx330", + "lane_to_serdes_map_nif_lane331": "rx331:tx331", + "lane_to_serdes_map_nif_lane332": "rx332:tx332", + "lane_to_serdes_map_nif_lane333": "rx333:tx333", + "lane_to_serdes_map_nif_lane334": "rx334:tx334", + "lane_to_serdes_map_nif_lane335": "rx335:tx335", + "lane_to_serdes_map_nif_lane336": "rx336:tx336", + "lane_to_serdes_map_nif_lane337": "rx337:tx337", + "lane_to_serdes_map_nif_lane338": "rx338:tx338", + "lane_to_serdes_map_nif_lane339": "rx339:tx339", + "lane_to_serdes_map_nif_lane340": "rx340:tx340", + "lane_to_serdes_map_nif_lane341": "rx341:tx341", + "lane_to_serdes_map_nif_lane342": "rx342:tx342", + "lane_to_serdes_map_nif_lane343": "rx343:tx343", + "lane_to_serdes_map_nif_lane344": "rx344:tx344", + "lane_to_serdes_map_nif_lane345": "rx345:tx345", + "lane_to_serdes_map_nif_lane346": "rx346:tx346", + "lane_to_serdes_map_nif_lane347": "rx347:tx347", + "lane_to_serdes_map_nif_lane348": "rx348:tx348", + "lane_to_serdes_map_nif_lane349": "rx349:tx349", + "lane_to_serdes_map_nif_lane350": "rx350:tx350", + "lane_to_serdes_map_nif_lane351": "rx351:tx351", + "lane_to_serdes_map_nif_lane352": "rx352:tx352", + "lane_to_serdes_map_nif_lane353": "rx353:tx353", + "lane_to_serdes_map_nif_lane354": "rx354:tx354", + "lane_to_serdes_map_nif_lane355": "rx355:tx355", + "lane_to_serdes_map_nif_lane356": "rx356:tx356", + "lane_to_serdes_map_nif_lane357": "rx357:tx357", + "lane_to_serdes_map_nif_lane358": "rx358:tx358", + "lane_to_serdes_map_nif_lane359": "rx359:tx359", + "lane_to_serdes_map_nif_lane360": "rx360:tx360", + "lane_to_serdes_map_nif_lane361": "rx361:tx361", + "lane_to_serdes_map_nif_lane362": "rx362:tx362", + "lane_to_serdes_map_nif_lane363": "rx363:tx363", + "lane_to_serdes_map_nif_lane364": "rx364:tx364", + "lane_to_serdes_map_nif_lane365": "rx365:tx365", + "lane_to_serdes_map_nif_lane366": "rx366:tx366", + "lane_to_serdes_map_nif_lane367": "rx367:tx367", + "lane_to_serdes_map_nif_lane368": "rx368:tx368", + "lane_to_serdes_map_nif_lane369": "rx369:tx369", + "lane_to_serdes_map_nif_lane370": "rx370:tx370", + "lane_to_serdes_map_nif_lane371": "rx371:tx371", + "lane_to_serdes_map_nif_lane372": "rx372:tx372", + "lane_to_serdes_map_nif_lane373": "rx373:tx373", + "lane_to_serdes_map_nif_lane374": "rx374:tx374", + "lane_to_serdes_map_nif_lane375": "rx375:tx375", + "lane_to_serdes_map_nif_lane376": "rx376:tx376", + "lane_to_serdes_map_nif_lane377": "rx377:tx377", + "lane_to_serdes_map_nif_lane378": "rx378:tx378", + "lane_to_serdes_map_nif_lane379": "rx379:tx379", + "lane_to_serdes_map_nif_lane380": "rx380:tx380", + "lane_to_serdes_map_nif_lane381": "rx381:tx381", + "lane_to_serdes_map_nif_lane382": "rx382:tx382", + "lane_to_serdes_map_nif_lane383": "rx383:tx383", + "lane_to_serdes_map_nif_lane384": "rx384:tx384", + "lane_to_serdes_map_nif_lane385": "rx385:tx385", + "lane_to_serdes_map_nif_lane386": "rx386:tx386", + "lane_to_serdes_map_nif_lane387": "rx387:tx387", + "lane_to_serdes_map_nif_lane388": "rx388:tx388", + "lane_to_serdes_map_nif_lane389": "rx389:tx389", + "lane_to_serdes_map_nif_lane390": "rx390:tx390", + "lane_to_serdes_map_nif_lane391": "rx391:tx391", + "lane_to_serdes_map_nif_lane392": "rx392:tx392", + "lane_to_serdes_map_nif_lane393": "rx393:tx393", + "lane_to_serdes_map_nif_lane394": "rx394:tx394", + "lane_to_serdes_map_nif_lane395": "rx395:tx395", + "lane_to_serdes_map_nif_lane396": "rx396:tx396", + "lane_to_serdes_map_nif_lane397": "rx397:tx397", + "lane_to_serdes_map_nif_lane398": "rx398:tx398", + "lane_to_serdes_map_nif_lane399": "rx399:tx399", + "lane_to_serdes_map_nif_lane400": "rx400:tx400", + "lane_to_serdes_map_nif_lane401": "rx401:tx401", + "lane_to_serdes_map_nif_lane402": "rx402:tx402", + "lane_to_serdes_map_nif_lane403": "rx403:tx403", + "lane_to_serdes_map_nif_lane404": "rx404:tx404", + "lane_to_serdes_map_nif_lane405": "rx405:tx405", + "lane_to_serdes_map_nif_lane406": "rx406:tx406", + "lane_to_serdes_map_nif_lane407": "rx407:tx407", + "lane_to_serdes_map_nif_lane408": "rx408:tx408", + "lane_to_serdes_map_nif_lane409": "rx409:tx409", + "lane_to_serdes_map_nif_lane410": "rx410:tx410", + "lane_to_serdes_map_nif_lane411": "rx411:tx411", + "lane_to_serdes_map_nif_lane412": "rx412:tx412", + "lane_to_serdes_map_nif_lane413": "rx413:tx413", + "lane_to_serdes_map_nif_lane414": "rx414:tx414", + "lane_to_serdes_map_nif_lane415": "rx415:tx415", + "lane_to_serdes_map_nif_lane416": "rx416:tx416", + "lane_to_serdes_map_nif_lane417": "rx417:tx417", + "lane_to_serdes_map_nif_lane418": "rx418:tx418", + "lane_to_serdes_map_nif_lane419": "rx419:tx419", + "lane_to_serdes_map_nif_lane420": "rx420:tx420", + "lane_to_serdes_map_nif_lane421": "rx421:tx421", + "lane_to_serdes_map_nif_lane422": "rx422:tx422", + "lane_to_serdes_map_nif_lane423": "rx423:tx423", + "lane_to_serdes_map_nif_lane424": "rx424:tx424", + "lane_to_serdes_map_nif_lane425": "rx425:tx425", + "lane_to_serdes_map_nif_lane426": "rx426:tx426", + "lane_to_serdes_map_nif_lane427": "rx427:tx427", + "lane_to_serdes_map_nif_lane428": "rx428:tx428", + "lane_to_serdes_map_nif_lane429": "rx429:tx429", + "lane_to_serdes_map_nif_lane430": "rx430:tx430", + "lane_to_serdes_map_nif_lane431": "rx431:tx431", + "lane_to_serdes_map_nif_lane432": "rx432:tx432", + "lane_to_serdes_map_nif_lane433": "rx433:tx433", + "lane_to_serdes_map_nif_lane434": "rx434:tx434", + "lane_to_serdes_map_nif_lane435": "rx435:tx435", + "lane_to_serdes_map_nif_lane436": "rx436:tx436", + "lane_to_serdes_map_nif_lane437": "rx437:tx437", + "lane_to_serdes_map_nif_lane438": "rx438:tx438", + "lane_to_serdes_map_nif_lane439": "rx439:tx439", + "lane_to_serdes_map_nif_lane440": "rx440:tx440", + "lane_to_serdes_map_nif_lane441": "rx441:tx441", + "lane_to_serdes_map_nif_lane442": "rx442:tx442", + "lane_to_serdes_map_nif_lane443": "rx443:tx443", + "lane_to_serdes_map_nif_lane444": "rx444:tx444", + "lane_to_serdes_map_nif_lane445": "rx445:tx445", + "lane_to_serdes_map_nif_lane446": "rx446:tx446", + "lane_to_serdes_map_nif_lane447": "rx447:tx447", + "lane_to_serdes_map_nif_lane448": "rx448:tx448", + "lane_to_serdes_map_nif_lane449": "rx449:tx449", + "lane_to_serdes_map_nif_lane450": "rx450:tx450", + "lane_to_serdes_map_nif_lane451": "rx451:tx451", + "lane_to_serdes_map_nif_lane452": "rx452:tx452", + "lane_to_serdes_map_nif_lane453": "rx453:tx453", + "lane_to_serdes_map_nif_lane454": "rx454:tx454", + "lane_to_serdes_map_nif_lane455": "rx455:tx455", + "lane_to_serdes_map_nif_lane456": "rx456:tx456", + "lane_to_serdes_map_nif_lane457": "rx457:tx457", + "lane_to_serdes_map_nif_lane458": "rx458:tx458", + "lane_to_serdes_map_nif_lane459": "rx459:tx459", + "lane_to_serdes_map_nif_lane460": "rx460:tx460", + "lane_to_serdes_map_nif_lane461": "rx461:tx461", + "lane_to_serdes_map_nif_lane462": "rx462:tx462", + "lane_to_serdes_map_nif_lane463": "rx463:tx463", + "lane_to_serdes_map_nif_lane464": "rx464:tx464", + "lane_to_serdes_map_nif_lane465": "rx465:tx465", + "lane_to_serdes_map_nif_lane466": "rx466:tx466", + "lane_to_serdes_map_nif_lane467": "rx467:tx467", + "lane_to_serdes_map_nif_lane468": "rx468:tx468", + "lane_to_serdes_map_nif_lane469": "rx469:tx469", + "lane_to_serdes_map_nif_lane470": "rx470:tx470", + "lane_to_serdes_map_nif_lane471": "rx471:tx471", + "lane_to_serdes_map_nif_lane472": "rx472:tx472", + "lane_to_serdes_map_nif_lane473": "rx473:tx473", + "lane_to_serdes_map_nif_lane474": "rx474:tx474", + "lane_to_serdes_map_nif_lane475": "rx475:tx475", + "lane_to_serdes_map_nif_lane476": "rx476:tx476", + "lane_to_serdes_map_nif_lane477": "rx477:tx477", + "lane_to_serdes_map_nif_lane478": "rx478:tx478", + "lane_to_serdes_map_nif_lane479": "rx479:tx479", + "lane_to_serdes_map_nif_lane480": "rx480:tx480", + "lane_to_serdes_map_nif_lane481": "rx481:tx481", + "lane_to_serdes_map_nif_lane482": "rx482:tx482", + "lane_to_serdes_map_nif_lane483": "rx483:tx483", + "lane_to_serdes_map_nif_lane484": "rx484:tx484", + "lane_to_serdes_map_nif_lane485": "rx485:tx485", + "lane_to_serdes_map_nif_lane486": "rx486:tx486", + "lane_to_serdes_map_nif_lane487": "rx487:tx487", + "lane_to_serdes_map_nif_lane488": "rx488:tx488", + "lane_to_serdes_map_nif_lane489": "rx489:tx489", + "lane_to_serdes_map_nif_lane490": "rx490:tx490", + "lane_to_serdes_map_nif_lane491": "rx491:tx491", + "lane_to_serdes_map_nif_lane492": "rx492:tx492", + "lane_to_serdes_map_nif_lane493": "rx493:tx493", + "lane_to_serdes_map_nif_lane494": "rx494:tx494", + "lane_to_serdes_map_nif_lane495": "rx495:tx495", + "lane_to_serdes_map_nif_lane496": "rx496:tx496", + "lane_to_serdes_map_nif_lane497": "rx497:tx497", + "lane_to_serdes_map_nif_lane498": "rx498:tx498", + "lane_to_serdes_map_nif_lane499": "rx499:tx499", + "lane_to_serdes_map_nif_lane500": "rx500:tx500", + "lane_to_serdes_map_nif_lane501": "rx501:tx501", + "lane_to_serdes_map_nif_lane502": "rx502:tx502", + "lane_to_serdes_map_nif_lane503": "rx503:tx503", + "lane_to_serdes_map_nif_lane504": "rx504:tx504", + "lane_to_serdes_map_nif_lane505": "rx505:tx505", + "lane_to_serdes_map_nif_lane506": "rx506:tx506", + "lane_to_serdes_map_nif_lane507": "rx507:tx507", + "lane_to_serdes_map_nif_lane508": "rx508:tx508", + "lane_to_serdes_map_nif_lane509": "rx509:tx509", + "lane_to_serdes_map_nif_lane510": "rx510:tx510", + "lane_to_serdes_map_nif_lane511": "rx511:tx511", + "warmboot_support.BCM994EX": "on", + "warmboot_support.BCM994EX_ADAPTER": "on" + } + } + } + } + }, + "thriftApiToRateLimitInQps": {} +} diff --git a/fboss/platform/configs/j4sim/platform_manager.json b/fboss/platform/configs/j4sim/platform_manager.json index 1caaee14efa3c..eb6d3f97dbf1a 100644 --- a/fboss/platform/configs/j4sim/platform_manager.json +++ b/fboss/platform/configs/j4sim/platform_manager.json @@ -102,7 +102,16 @@ }, "SMB": { "pluggedInSlotType": "SMB_SLOT", - "i2cDeviceConfigs": [], + "i2cDeviceConfigs": [ + { + "busName": "INCOMING@1", + "address": "0x50", + "kernelDeviceName": "24c512", + "pmUnitScopedName": "CHASSIS_EEPROM", + "isEeprom": true, + "eepromOffset": 15360 + } + ], "outgoingSlotConfigs": {}, "pciDeviceConfigs": [ { @@ -111,7 +120,24 @@ "deviceId": "0x0001", "subSystemVendorId": "0x3475", "subSystemDeviceId": "0x0015", - "i2cAdapterBlockConfigs": [], + "i2cAdapterBlockConfigs": [ + { + "pmUnitScopedNamePrefix": "SMB_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8000 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 0, + "numAdapters": 2, + "numBusesPerAdapter": 6 + }, + { + "pmUnitScopedNamePrefix": "SMB_I2C_MASTER", + "deviceName": "i2c_master", + "csrOffsetCalc": "0x8100 + ({adapterIndex} - {startAdapterIndex})*0x80", + "startAdapterIndex": 2, + "numAdapters": 8, + "numBusesPerAdapter": 8 + } + ], "spiMasterConfigs": [], "ledCtrlBlockConfigs": [ { @@ -174,8 +200,246 @@ "i2cAdaptersFromCpu": [ "SMBus I801 adapter at 1000" ], - "symbolicLinkToDevicePath": {}, - "chassisEepromDevicePath": "/SMB_SLOT@0/[IDPROM]", + "symbolicLinkToDevicePath": { + "/run/devmap/fpgas/MERU_SCM_CPLD": "/[SCM_FPGA]", + "/run/devmap/fpgas/MERU_SCM_CPLD_INFO_ROM": "/[SCM_FPGA_INFO_ROM]", + "/run/devmap/inforoms/MERU_SCM_CPLD_INFO_ROM": "/[SCM_FPGA_INFO_ROM]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH0": "/[SCM_I2C_MASTER_0@0]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH1": "/[SCM_I2C_MASTER_0@1]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH2": "/[SCM_I2C_MASTER_0@2]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH3": "/[SCM_I2C_MASTER_0@3]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH4": "/[SCM_I2C_MASTER_0@4]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH5": "/[SCM_I2C_MASTER_0@5]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH6": "/[SCM_I2C_MASTER_0@6]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS0_CH7": "/[SCM_I2C_MASTER_0@7]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH0": "/[SCM_I2C_MASTER_1@0]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH1": "/[SCM_I2C_MASTER_1@1]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH2": "/[SCM_I2C_MASTER_1@2]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH3": "/[SCM_I2C_MASTER_1@3]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH4": "/[SCM_I2C_MASTER_1@4]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH5": "/[SCM_I2C_MASTER_1@5]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH6": "/[SCM_I2C_MASTER_1@6]", + "/run/devmap/i2c-busses/MERU_SCM_CPLD_SMBUS1_CH7": "/[SCM_I2C_MASTER_1@7]", + "/run/devmap/eeproms/SMB_EEPROM": "/SMB_SLOT@0/[IDPROM]", + "/run/devmap/sensors/CPU_MPS_PMBUS": "/[SCM_MPS_PMBUS]", + "/run/devmap/sensors/CPU_CORE_TEMP": "/[CPU_CORE_TEMP]", + "/run/devmap/sensors/NVME_TEMP": "/[NVME_TEMP]", + "/run/devmap/fpgas/SMB_FPGA": "/SMB_SLOT@0/[SMB_FPGA]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS0_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_0@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS1_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS2_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS3_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS4_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS5_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS6_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS7_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS8_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@7]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH0": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@0]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH1": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@1]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH2": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@2]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH3": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@3]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH4": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@4]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH5": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@5]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH6": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@6]", + "/run/devmap/i2c-busses/SMB_FPGA_SMBUS9_CH7": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@7]", + "/run/devmap/eeproms/CHASSIS_EEPROM": "/SMB_SLOT@0/[CHASSIS_EEPROM]", + "/run/devmap/xcvrs/xcvr_io_1": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@0]", + "/run/devmap/xcvrs/xcvr_ctrl_1": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_1]", + "/run/devmap/xcvrs/xcvr_io_2": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@1]", + "/run/devmap/xcvrs/xcvr_ctrl_2": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_2]", + "/run/devmap/xcvrs/xcvr_io_3": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@2]", + "/run/devmap/xcvrs/xcvr_ctrl_3": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_3]", + "/run/devmap/xcvrs/xcvr_io_4": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@3]", + "/run/devmap/xcvrs/xcvr_ctrl_4": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_4]", + "/run/devmap/xcvrs/xcvr_io_5": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@4]", + "/run/devmap/xcvrs/xcvr_ctrl_5": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_5]", + "/run/devmap/xcvrs/xcvr_io_6": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@5]", + "/run/devmap/xcvrs/xcvr_ctrl_6": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_6]", + "/run/devmap/xcvrs/xcvr_io_7": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@6]", + "/run/devmap/xcvrs/xcvr_ctrl_7": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_7]", + "/run/devmap/xcvrs/xcvr_io_8": "/SMB_SLOT@0/[SMB_I2C_MASTER_2@7]", + "/run/devmap/xcvrs/xcvr_ctrl_8": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_8]", + "/run/devmap/xcvrs/xcvr_io_9": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@0]", + "/run/devmap/xcvrs/xcvr_ctrl_9": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_9]", + "/run/devmap/xcvrs/xcvr_io_10": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@1]", + "/run/devmap/xcvrs/xcvr_ctrl_10": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_10]", + "/run/devmap/xcvrs/xcvr_io_11": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@2]", + "/run/devmap/xcvrs/xcvr_ctrl_11": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_11]", + "/run/devmap/xcvrs/xcvr_io_12": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@3]", + "/run/devmap/xcvrs/xcvr_ctrl_12": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_12]", + "/run/devmap/xcvrs/xcvr_io_13": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@4]", + "/run/devmap/xcvrs/xcvr_ctrl_13": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_13]", + "/run/devmap/xcvrs/xcvr_io_14": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@5]", + "/run/devmap/xcvrs/xcvr_ctrl_14": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_14]", + "/run/devmap/xcvrs/xcvr_io_15": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@6]", + "/run/devmap/xcvrs/xcvr_ctrl_15": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_15]", + "/run/devmap/xcvrs/xcvr_io_16": "/SMB_SLOT@0/[SMB_I2C_MASTER_3@7]", + "/run/devmap/xcvrs/xcvr_ctrl_16": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_16]", + "/run/devmap/xcvrs/xcvr_io_17": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@0]", + "/run/devmap/xcvrs/xcvr_ctrl_17": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_17]", + "/run/devmap/xcvrs/xcvr_io_18": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@1]", + "/run/devmap/xcvrs/xcvr_ctrl_18": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_18]", + "/run/devmap/xcvrs/xcvr_io_19": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@2]", + "/run/devmap/xcvrs/xcvr_ctrl_19": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_19]", + "/run/devmap/xcvrs/xcvr_io_20": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@3]", + "/run/devmap/xcvrs/xcvr_ctrl_20": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_20]", + "/run/devmap/xcvrs/xcvr_io_21": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@4]", + "/run/devmap/xcvrs/xcvr_ctrl_21": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_21]", + "/run/devmap/xcvrs/xcvr_io_22": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@5]", + "/run/devmap/xcvrs/xcvr_ctrl_22": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_22]", + "/run/devmap/xcvrs/xcvr_io_23": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@6]", + "/run/devmap/xcvrs/xcvr_ctrl_23": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_23]", + "/run/devmap/xcvrs/xcvr_io_24": "/SMB_SLOT@0/[SMB_I2C_MASTER_4@7]", + "/run/devmap/xcvrs/xcvr_ctrl_24": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_24]", + "/run/devmap/xcvrs/xcvr_io_25": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@0]", + "/run/devmap/xcvrs/xcvr_ctrl_25": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_25]", + "/run/devmap/xcvrs/xcvr_io_26": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@1]", + "/run/devmap/xcvrs/xcvr_ctrl_26": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_26]", + "/run/devmap/xcvrs/xcvr_io_27": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@2]", + "/run/devmap/xcvrs/xcvr_ctrl_27": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_27]", + "/run/devmap/xcvrs/xcvr_io_28": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@3]", + "/run/devmap/xcvrs/xcvr_ctrl_28": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_28]", + "/run/devmap/xcvrs/xcvr_io_29": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@4]", + "/run/devmap/xcvrs/xcvr_ctrl_29": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_29]", + "/run/devmap/xcvrs/xcvr_io_30": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@5]", + "/run/devmap/xcvrs/xcvr_ctrl_30": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_30]", + "/run/devmap/xcvrs/xcvr_io_31": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@6]", + "/run/devmap/xcvrs/xcvr_ctrl_31": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_31]", + "/run/devmap/xcvrs/xcvr_io_32": "/SMB_SLOT@0/[SMB_I2C_MASTER_5@7]", + "/run/devmap/xcvrs/xcvr_ctrl_32": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_32]", + "/run/devmap/xcvrs/xcvr_io_33": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@0]", + "/run/devmap/xcvrs/xcvr_ctrl_33": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_33]", + "/run/devmap/xcvrs/xcvr_io_34": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@1]", + "/run/devmap/xcvrs/xcvr_ctrl_34": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_34]", + "/run/devmap/xcvrs/xcvr_io_35": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@2]", + "/run/devmap/xcvrs/xcvr_ctrl_35": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_35]", + "/run/devmap/xcvrs/xcvr_io_36": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@3]", + "/run/devmap/xcvrs/xcvr_ctrl_36": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_36]", + "/run/devmap/xcvrs/xcvr_io_37": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@4]", + "/run/devmap/xcvrs/xcvr_ctrl_37": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_37]", + "/run/devmap/xcvrs/xcvr_io_38": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@5]", + "/run/devmap/xcvrs/xcvr_ctrl_38": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_38]", + "/run/devmap/xcvrs/xcvr_io_39": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@6]", + "/run/devmap/xcvrs/xcvr_ctrl_39": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_39]", + "/run/devmap/xcvrs/xcvr_io_40": "/SMB_SLOT@0/[SMB_I2C_MASTER_6@7]", + "/run/devmap/xcvrs/xcvr_ctrl_40": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_40]", + "/run/devmap/xcvrs/xcvr_io_41": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@0]", + "/run/devmap/xcvrs/xcvr_ctrl_41": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_41]", + "/run/devmap/xcvrs/xcvr_io_42": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@1]", + "/run/devmap/xcvrs/xcvr_ctrl_42": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_42]", + "/run/devmap/xcvrs/xcvr_io_43": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@2]", + "/run/devmap/xcvrs/xcvr_ctrl_43": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_43]", + "/run/devmap/xcvrs/xcvr_io_44": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@3]", + "/run/devmap/xcvrs/xcvr_ctrl_44": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_44]", + "/run/devmap/xcvrs/xcvr_io_45": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@4]", + "/run/devmap/xcvrs/xcvr_ctrl_45": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_45]", + "/run/devmap/xcvrs/xcvr_io_46": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@5]", + "/run/devmap/xcvrs/xcvr_ctrl_46": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_46]", + "/run/devmap/xcvrs/xcvr_io_47": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@6]", + "/run/devmap/xcvrs/xcvr_ctrl_47": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_47]", + "/run/devmap/xcvrs/xcvr_io_48": "/SMB_SLOT@0/[SMB_I2C_MASTER_7@7]", + "/run/devmap/xcvrs/xcvr_ctrl_48": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_48]", + "/run/devmap/xcvrs/xcvr_io_49": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@0]", + "/run/devmap/xcvrs/xcvr_ctrl_49": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_49]", + "/run/devmap/xcvrs/xcvr_io_50": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@1]", + "/run/devmap/xcvrs/xcvr_ctrl_50": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_50]", + "/run/devmap/xcvrs/xcvr_io_51": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@2]", + "/run/devmap/xcvrs/xcvr_ctrl_51": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_51]", + "/run/devmap/xcvrs/xcvr_io_52": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@3]", + "/run/devmap/xcvrs/xcvr_ctrl_52": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_52]", + "/run/devmap/xcvrs/xcvr_io_53": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@4]", + "/run/devmap/xcvrs/xcvr_ctrl_53": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_53]", + "/run/devmap/xcvrs/xcvr_io_54": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@5]", + "/run/devmap/xcvrs/xcvr_ctrl_54": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_54]", + "/run/devmap/xcvrs/xcvr_io_55": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@6]", + "/run/devmap/xcvrs/xcvr_ctrl_55": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_55]", + "/run/devmap/xcvrs/xcvr_io_56": "/SMB_SLOT@0/[SMB_I2C_MASTER_8@7]", + "/run/devmap/xcvrs/xcvr_ctrl_56": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_56]", + "/run/devmap/xcvrs/xcvr_io_57": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@0]", + "/run/devmap/xcvrs/xcvr_ctrl_57": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_57]", + "/run/devmap/xcvrs/xcvr_io_58": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@1]", + "/run/devmap/xcvrs/xcvr_ctrl_58": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_58]", + "/run/devmap/xcvrs/xcvr_io_59": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@2]", + "/run/devmap/xcvrs/xcvr_ctrl_59": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_59]", + "/run/devmap/xcvrs/xcvr_io_60": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@3]", + "/run/devmap/xcvrs/xcvr_ctrl_60": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_60]", + "/run/devmap/xcvrs/xcvr_io_61": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@4]", + "/run/devmap/xcvrs/xcvr_ctrl_61": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_61]", + "/run/devmap/xcvrs/xcvr_io_62": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@5]", + "/run/devmap/xcvrs/xcvr_ctrl_62": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_62]", + "/run/devmap/xcvrs/xcvr_io_63": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@6]", + "/run/devmap/xcvrs/xcvr_ctrl_63": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_63]", + "/run/devmap/xcvrs/xcvr_io_64": "/SMB_SLOT@0/[SMB_I2C_MASTER_9@7]", + "/run/devmap/xcvrs/xcvr_ctrl_64": "/SMB_SLOT@0/[OSFP_XCVR_CTRL_PORT_64]", + "/run/devmap/xcvrs/xcvr_io_65": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@2]", + "/run/devmap/xcvrs/xcvr_ctrl_65": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_65]", + "/run/devmap/xcvrs/xcvr_io_66": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@3]", + "/run/devmap/xcvrs/xcvr_ctrl_66": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_66]", + "/run/devmap/xcvrs/xcvr_io_67": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@4]", + "/run/devmap/xcvrs/xcvr_ctrl_67": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_67]", + "/run/devmap/xcvrs/xcvr_io_68": "/SMB_SLOT@0/[SMB_I2C_MASTER_1@5]", + "/run/devmap/xcvrs/xcvr_ctrl_68": "/SMB_SLOT@0/[QSFP_XCVR_CTRL_PORT_68]" + }, + "chassisEepromDevicePath": "/SMB_SLOT@0/[CHASSIS_EEPROM]", "numXcvrs": 68, "bspKmodsRpmName": "arista_bsp_kmods", "bspKmodsRpmVersion": "0.7.17-1", From eeb147f320bcc0089e3b699c10f16fab8194bea2 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Thu, 19 Feb 2026 11:46:20 -0800 Subject: [PATCH 13/16] Taking more changes from Satish's diff, still failing -- j4 cmodel is actually j4l? --- fboss/agent/hw/bcm/BcmPlatform.cpp | 1 + .../hw/sai/switch/tests/ManagerTestBase.cpp | 3 ++- fboss/agent/hw/switch_asics/Jericho3Asic.cpp | 7 ++++++- fboss/agent/hw/switch_asics/Jericho4Asic.h | 3 +++ .../common/j4sim/J4SimPlatformMapping.cpp | 17 +++++++++++++++++ .../common/j4sim/J4SimPlatformMapping.h | 4 ++++ .../agent/platforms/sai/SaiBcmJ4SimPlatform.cpp | 3 ++- fboss/agent/platforms/sai/SaiBcmPlatform.cpp | 1 + fboss/agent/platforms/sai/SaiPlatform.cpp | 13 +++++++++++-- 9 files changed, 47 insertions(+), 5 deletions(-) diff --git a/fboss/agent/hw/bcm/BcmPlatform.cpp b/fboss/agent/hw/bcm/BcmPlatform.cpp index bb6be42a59d29..ee3efd20db383 100644 --- a/fboss/agent/hw/bcm/BcmPlatform.cpp +++ b/fboss/agent/hw/bcm/BcmPlatform.cpp @@ -114,6 +114,7 @@ phy::VCOFrequency BcmPlatform::getVCOFrequency( case cfg::PortSpeed::GIGE: [[fallthrough]]; case cfg::PortSpeed::EIGHTHUNDREDG: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: case cfg::PortSpeed::DEFAULT: return phy::VCOFrequency::UNKNOWN; diff --git a/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp b/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp index 8c081fe283c39..d8e9d746e2391 100644 --- a/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp +++ b/fboss/agent/hw/sai/switch/tests/ManagerTestBase.cpp @@ -253,8 +253,9 @@ std::shared_ptr ManagerTestBase::makePort( swPort->setProfileId(cfg::PortProfileID::PROFILE_DEFAULT); break; case cfg::PortSpeed::GIGE: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: - throw FbossError("profile gig and 3.2T ethernet is not available"); + throw FbossError("profile gig, 1.6T and 3.2T ethernet is not available"); case cfg::PortSpeed::XG: swPort->setProfileId(cfg::PortProfileID::PROFILE_10G_1_NRZ_NOFEC_OPTICAL); break; diff --git a/fboss/agent/hw/switch_asics/Jericho3Asic.cpp b/fboss/agent/hw/switch_asics/Jericho3Asic.cpp index 51600870bdaf4..a826ae851d1f8 100644 --- a/fboss/agent/hw/switch_asics/Jericho3Asic.cpp +++ b/fboss/agent/hw/switch_asics/Jericho3Asic.cpp @@ -74,7 +74,6 @@ bool Jericho3Asic::isSupported(Feature feature) const { case HwAsic::Feature::WARMBOOT: case HwAsic::Feature::PQP_ERROR_EGRESS_DROP_COUNTER: case HwAsic::Feature::FABRIC_LINK_DOWN_CELL_DROP_COUNTER: - case HwAsic::Feature::SAI_FEC_CODEWORDS_STATS: case HwAsic::Feature::CRC_ERROR_DETECT: case HwAsic::Feature::ACL_METADATA_QUALIFER: case HwAsic::Feature::EVENTOR_PORT_FOR_SFLOW: @@ -250,6 +249,12 @@ bool Jericho3Asic::isSupported(Feature feature) const { case HwAsic::Feature::VIRTUAL_ARS_GROUP: case HwAsic::Feature::ECN_PROBABILISTIC_MARKING: case HwAsic::Feature::SWITCH_DROP_DEBUG_COUNTER: + // Disabling some counters for the time being. + // This will result in an early return in + // SaiDebugCounterManager::setupTrapDropCounter(), which is currently + // failing with SAI 14.x + case HwAsic::Feature::ANY_TRAP_DROP_COUNTER: + case HwAsic::Feature::SAI_FEC_CODEWORDS_STATS: return false; } return false; diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h index 0c1df66398630..e4b60e5d81426 100644 --- a/fboss/agent/hw/switch_asics/Jericho4Asic.h +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -29,6 +29,9 @@ class Jericho4Asic : public Jericho3Asic { return false; } return Jericho3Asic::isSupported(feature); + + uint32_t getNumCores() const override { + return 8; } }; diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp index dc3a73cafaacb..c0755579d3ee2 100644 --- a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -18,4 +18,21 @@ J4SimPlatformMapping::J4SimPlatformMapping( const std::string& platformMappingStr) : PlatformMapping(platformMappingStr) {} +std::map> +J4SimPlatformMapping::getCpuPortsCoreAndPortIdx() const { + static const std::map> + kSingleStageCpuPortsCoreAndPortIdx = { + // {CPU System Port, {Core ID, Port ID/PP_DSP}} + {0, {0, 0}}, + {1, {1, 0}}, + {2, {2, 0}}, + {3, {3, 0}}, + {4, {4, 0}}, + {5, {5, 0}}, + {6, {6, 0}}, + {7, {7, 0}}, + }; + return kSingleStageCpuPortsCoreAndPortIdx; +} + } // namespace facebook::fboss diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h index 69a404c5f7452..628c540cdfef4 100644 --- a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h @@ -17,6 +17,10 @@ class J4SimPlatformMapping : public PlatformMapping { public: J4SimPlatformMapping(); explicit J4SimPlatformMapping(const std::string& platformMappingStr); + // For CPU system port number as key, get the core for CPU port and + // the port ID within the core. + std::map> getCpuPortsCoreAndPortIdx() + const override; private: // Forbidden copy constructor and assignment operator diff --git a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp index c3a4776d2cc1f..be70889d35754 100644 --- a/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiBcmJ4SimPlatform.cpp @@ -57,7 +57,8 @@ SaiBcmJ4SimPlatform::getInternalSystemPortConfig() const { getPlatformMapping()->getCpuPortsCoreAndPortIdx(); CHECK( - cpuPortsCoreAndPortIdx.size() == 1 || cpuPortsCoreAndPortIdx.size() == 4) + cpuPortsCoreAndPortIdx.size() == 1 || + cpuPortsCoreAndPortIdx.size() == 4 || cpuPortsCoreAndPortIdx.size() == 8) << "Create one CPU port for the ASIC or one CPU port for each core"; std::vector sysPortConfig; diff --git a/fboss/agent/platforms/sai/SaiBcmPlatform.cpp b/fboss/agent/platforms/sai/SaiBcmPlatform.cpp index b402ea8db8b6e..ac259067668ad 100644 --- a/fboss/agent/platforms/sai/SaiBcmPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiBcmPlatform.cpp @@ -227,6 +227,7 @@ phy::VCOFrequency SaiBcmPlatform::getPortVcoFrequency( case cfg::PortSpeed::GIGE: [[fallthrough]]; case cfg::PortSpeed::EIGHTHUNDREDG: + case cfg::PortSpeed::ONEPOINTSIXT: case cfg::PortSpeed::THREEPOINTTWOT: case cfg::PortSpeed::DEFAULT: return phy::VCOFrequency::UNKNOWN; diff --git a/fboss/agent/platforms/sai/SaiPlatform.cpp b/fboss/agent/platforms/sai/SaiPlatform.cpp index 9e42ab5326d30..b4f930f4a423e 100644 --- a/fboss/agent/platforms/sai/SaiPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiPlatform.cpp @@ -17,6 +17,7 @@ #include "fboss/agent/hw/sai/switch/SaiSwitch.h" #include "fboss/agent/hw/switch_asics/HwAsic.h" #include "fboss/agent/hw/switch_asics/Jericho3Asic.h" +#include "fboss/agent/hw/switch_asics/Jericho4Asic.h" #include "fboss/agent/platforms/sai/SaiBcmDarwinPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmElbertPlatformPort.h" #include "fboss/agent/platforms/sai/SaiBcmFujiPlatformPort.h" @@ -559,19 +560,24 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( swInfo.switchType() = cfg::SwitchType::VOQ; swInfo.switchMac() = localMac.toString(); const Jericho3Asic j3(0, swInfo); + const Jericho4Asic j4(0, swInfo); for (const auto& [id, dsfNode] : *agentCfg->thrift.sw()->dsfNodes()) { if (dsfNode.type() != cfg::DsfNodeType::INTERFACE_NODE) { continue; } switch (*dsfNode.asicType()) { case cfg::AsicType::ASIC_TYPE_JERICHO3: - case cfg::AsicType::ASIC_TYPE_JERICHO4: // for directly connected interface nodes we don't expect // asic type to change across dsf nodes maxCoreCount = std::max(j3.getNumCores(), maxCoreCount); maxSystemCoreCount = std::max(maxSystemCoreCount, uint32_t(id + j3.getNumCores())); break; + case cfg::AsicType::ASIC_TYPE_JERICHO4: + maxCoreCount = std::max(j4.getNumCores(), maxCoreCount); + maxSystemCoreCount = + std::max(maxSystemCoreCount, uint32_t(id + j4.getNumCores())); + break; default: throw FbossError("Unexpected asic type: ", *dsfNode.asicType()); } @@ -914,6 +920,9 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( mapToValueList}; } #endif + maxSystemPorts = 1024; + maxVoqs = 8 * 1024; + maxSystemPortId = 1024 - 1; return { initSwitch, @@ -960,7 +969,7 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( #endif dllPath, std::nullopt, // Restart Issu - switchIsolate, + std::nullopt, // switchIsolate, #if SAI_API_VERSION >= SAI_VERSION(1, 12, 0) creditWd, // Credit Watchdog creditWdMs, // Credit Watchdog Timer From 20e23a9950a3f3c8f97156739e8d744640819138 Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Thu, 19 Feb 2026 16:24:44 -0800 Subject: [PATCH 14/16] Changes to all the J4Sim to work with J4L instead (4 cores). Used config-j4l.bcm in j4 cmodel tarball to figure out values to use and stuff --- fboss/agent/hw/switch_asics/Jericho4Asic.h | 3 +- .../common/j4sim/J4SimPlatformMapping.cpp | 4 - .../j4sim_platform_mapping.json | 35131 ++-------------- .../j4sim/j4sim_port_profile_mapping.csv | 194 +- .../j4sim/j4sim_profile_settings.csv | 11 - .../platforms/j4sim/j4sim_static_mapping.csv | 64 - .../j4sim.agent.materialized_JSON | 892 +- 7 files changed, 2788 insertions(+), 33511 deletions(-) diff --git a/fboss/agent/hw/switch_asics/Jericho4Asic.h b/fboss/agent/hw/switch_asics/Jericho4Asic.h index e4b60e5d81426..d4b4e477e5c05 100644 --- a/fboss/agent/hw/switch_asics/Jericho4Asic.h +++ b/fboss/agent/hw/switch_asics/Jericho4Asic.h @@ -30,8 +30,9 @@ class Jericho4Asic : public Jericho3Asic { } return Jericho3Asic::isSupported(feature); + // Jericho4 cModel bringup is using Jericho4L (99410) which only has 4 cores uint32_t getNumCores() const override { - return 8; + return 4; } }; diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp index c0755579d3ee2..dc89e27fd9bbc 100644 --- a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -27,10 +27,6 @@ J4SimPlatformMapping::getCpuPortsCoreAndPortIdx() const { {1, {1, 0}}, {2, {2, 0}}, {3, {3, 0}}, - {4, {4, 0}}, - {5, {5, 0}}, - {6, {6, 0}}, - {7, {7, 0}}, }; return kSingleStageCpuPortsCoreAndPortIdx; } diff --git a/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json index bf3bdaa90e768..454ec80958e8f 100644 --- a/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json +++ b/fboss/lib/platform_mapping_v2/generated_platform_mappings/j4sim_platform_mapping.json @@ -333,16 +333,7 @@ ] } }, - "35": { - "subsumedPorts": [ - 2, - 3, - 4, - 5, - 6, - 7, - 8 - ], + "49": { "pins": { "iphy": [ { @@ -350,48 +341,6 @@ "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", "lane": 0 } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 - } } ], "transceiver": [ @@ -400,139 +349,128 @@ "chip": "TRANSCEIVER-OSFP-slot1/chip1", "lane": 0 } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 - } } ] } - }, - "45": { - "subsumedPorts": [ - 2, - 3, - 4 - ], + } + } + }, + "2": { + "mapping": { + "id": 2, + "name": "eth1/1/2", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", "lane": 1 } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - } } ], "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", "lane": 1 } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } } ] } - }, - "38": { - "subsumedPorts": [ - 2, - 3, - 4 - ], + } + } + }, + "3": { + "mapping": { + "id": 3, + "name": "eth1/1/3", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 + "lane": 2 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "TRANSCEIVER-OSFP-slot1/chip1", "lane": 2 } - }, + } + ] + } + } + } + }, + "4": { + "mapping": { + "id": 4, + "name": "eth1/1/4", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", @@ -544,60 +482,44 @@ { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "lane": 3 } } ] } - }, - "24": { - "subsumedPorts": [ - 2, - 3, - 4 - ], + } + } + }, + "5": { + "mapping": { + "id": 5, + "name": "eth1/1/5", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "lane": 4 } } ], @@ -605,60 +527,44 @@ { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "lane": 4 } } ] } - }, - "25": { - "subsumedPorts": [ - 2, - 3, - 4 - ], + } + } + }, + "6": { + "mapping": { + "id": 6, + "name": "eth1/1/6", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "lane": 5 } } ], @@ -666,46 +572,44 @@ { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "lane": 5 } } ] } - }, - "54": { - "subsumedPorts": [ - 2 - ], + } + } + }, + "7": { + "mapping": { + "id": 7, + "name": "eth1/1/7", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 + "lane": 6 } } ], @@ -713,48 +617,44 @@ { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 + "lane": 6 } } ] } - }, - "22": { - "subsumedPorts": [ - 2, - 3, - 4 - ], + } + } + }, + "8": { + "mapping": { + "id": 8, + "name": "eth1/1/8", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "lane": 7 } } ], @@ -762,232 +662,343 @@ { "id": { "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "lane": 7 } } ] } - }, - "23": { + } + } + }, + "9": { + "mapping": { + "id": 9, + "name": "eth1/2/1", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { "subsumedPorts": [ - 2, - 3, - 4 + 10, + 11, + 12, + 13, + 14, + 15, + 16 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 3 } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 7 + } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 3 } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 5 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 6 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 7 } } ] } }, - "49": { + "39": { + "subsumedPorts": [ + 10, + 11, + 12, + 13, + 14, + 15, + 16 + ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 0 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 1 } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 2 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 3 } - } - ] - } - } - } - }, - "2": { - "mapping": { - "id": 2, - "name": "eth1/1/2", - "controllingPort": 1, - "pins": [ - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 - } - } - } - ], - "portType": 0, - "scope": 0 - }, - "supportedProfiles": { - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 5 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 1 } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 7 + } } ] } @@ -997,27 +1008,52 @@ "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 0 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 0 } } ] } - }, - "43": { + } + } + }, + "10": { + "mapping": { + "id": 10, + "name": "eth1/2/2", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 1 } } @@ -1025,7 +1061,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 1 } } @@ -1034,151 +1070,179 @@ } } }, - "3": { + "11": { "mapping": { - "id": 3, - "name": "eth1/1/3", - "controllingPort": 1, + "id": 11, + "name": "eth1/2/3", + "controllingPort": 9, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 2 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 2 } } - }, - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } - } } ], "portType": 0, "scope": 0 }, "supportedProfiles": { - "54": { - "subsumedPorts": [ - 4 - ], + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", "lane": 2 } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip2", "lane": 2 } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } } ] } - }, - "56": { + } + } + }, + "12": { + "mapping": { + "id": 12, + "name": "eth1/2/4", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 3 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 3 } } ] } - }, - "47": { + } + } + }, + "13": { + "mapping": { + "id": 13, + "name": "eth1/2/5", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 4 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 4 } } ] } - }, - "49": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 - } - } - ] + } + } + }, + "14": { + "mapping": { + "id": 14, + "name": "eth1/2/6", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 5 + } } - }, - "43": { + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 5 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 5 } } ] @@ -1186,21 +1250,21 @@ } } }, - "4": { + "15": { "mapping": { - "id": 4, - "name": "eth1/1/4", - "controllingPort": 3, + "id": 15, + "name": "eth1/2/7", + "controllingPort": 9, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 6 } } } @@ -1209,81 +1273,66 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 6 } } ] } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } - } - ] + } + } + }, + "16": { + "mapping": { + "id": 16, + "name": "eth1/2/8", + "controllingPort": 9, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 7 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core1", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip2", + "lane": 7 } } ] @@ -1291,56 +1340,104 @@ } } }, - "5": { + "17": { "mapping": { - "id": 5, - "name": "eth1/1/5", - "controllingPort": 1, + "id": 17, + "name": "eth1/3/1", + "controllingPort": 17, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 4 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 4 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 5 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 5 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 6 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 7 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 7 } } @@ -1350,473 +1447,418 @@ "scope": 0 }, "supportedProfiles": { - "45": { + "50": { "subsumedPorts": [ - 6, - 7, - 8 + 18, + 19, + 20, + 21, + 22, + 23, + 24 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 7 } } - ] - } - }, - "38": { - "subsumedPorts": [ - 6, - 7, - 8 - ], - "pins": { - "iphy": [ + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 7 } } ] } }, - "24": { + "39": { "subsumedPorts": [ - 6, - 7, - 8 + 18, + 19, + 20, + 21, + 22, + 23, + 24 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 7 } } - ] - } - }, - "25": { - "subsumedPorts": [ - 6, - 7, - 8 - ], - "pins": { - "iphy": [ + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 7 } } ] } }, - "54": { - "subsumedPorts": [ - 6 - ], + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 0 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 0 } } ] } - }, - "22": { - "subsumedPorts": [ - 6, - 7, - 8 - ], + } + } + }, + "18": { + "mapping": { + "id": 18, + "name": "eth1/3/2", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 1 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 1 } - }, + } + ] + } + } + } + }, + "19": { + "mapping": { + "id": 19, + "name": "eth1/3/3", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 2 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 2 } } ] } - }, - "23": { - "subsumedPorts": [ - 6, - 7, - 8 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 - } - } - ] + } + } + }, + "20": { + "mapping": { + "id": 20, + "name": "eth1/3/4", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 3 + } } - }, - "56": { + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 3 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 3 } } ] } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - } - ] + } + } + }, + "21": { + "mapping": { + "id": 21, + "name": "eth1/3/5", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 4 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 4 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 4 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 4 } } @@ -1824,7 +1866,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 4 } } @@ -1833,20 +1875,20 @@ } } }, - "6": { + "22": { "mapping": { - "id": 6, - "name": "eth1/1/6", - "controllingPort": 5, + "id": 22, + "name": "eth1/3/6", + "controllingPort": 17, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 5 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 5 } } @@ -1856,12 +1898,12 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", "lane": 5 } } @@ -1869,68 +1911,98 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip3", "lane": 5 } } ] } - }, - "47": { + } + } + }, + "23": { + "mapping": { + "id": 23, + "name": "eth1/3/7", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 6 } } ] } - }, + } + } + }, + "24": { + "mapping": { + "id": 24, + "name": "eth1/3/8", + "controllingPort": 17, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core2", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip3", + "lane": 7 } } ] @@ -1938,32 +2010,104 @@ } } }, - "7": { + "25": { "mapping": { - "id": 7, - "name": "eth1/1/7", - "controllingPort": 5, + "id": 25, + "name": "eth1/4/1", + "controllingPort": 25, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip4", "lane": 6 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", "lane": 7 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "chip": "TRANSCEIVER-OSFP-slot1/chip4", "lane": 7 } } @@ -1973,392 +2117,176 @@ "scope": 0 }, "supportedProfiles": { - "54": { + "50": { "subsumedPorts": [ - 8 + 26, + 27, + 28, + 29, + 30, + 31, + 32 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 1 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 3 } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 5 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", "lane": 6 } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 7 + } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 0 } - } - ] - } - }, - "49": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 1 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 } - } - ] - } - } - } - }, - "8": { - "mapping": { - "id": 8, - "name": "eth1/1/8", - "controllingPort": 7, - "pins": [ - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 - } - } - } - ], - "portType": 0, - "scope": 0 - }, - "supportedProfiles": { - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 6 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip1", - "lane": 7 - } - } - ] - } - }, - "49": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - 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27, + "name": "eth1/4/3", + "controllingPort": 25, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 2 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 } } } @@ -31682,81 +2433,21 @@ "scope": 0 }, "supportedProfiles": { - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 1 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 1 - } - } - ] - } - }, "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 1 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 2 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 2 } } ] @@ -31764,32 +2455,20 @@ } } }, - "115": { + "28": { "mapping": { - "id": 115, - "name": "eth1/15/3", - "controllingPort": 113, + "id": 28, + "name": "eth1/4/4", + "controllingPort": 25, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 - } - } - }, - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", "lane": 3 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip4", "lane": 3 } } @@ -31799,21 +2478,12 @@ "scope": 0 }, "supportedProfiles": { - "54": { - "subsumedPorts": [ - 116 - ], + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", "lane": 3 } } @@ -31821,94 +2491,98 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip4", "lane": 3 } } ] } - }, - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 - } - } - ] + } + } + }, + "29": { + "mapping": { + "id": 29, + "name": "eth1/4/5", + "controllingPort": 25, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 4 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 4 } } ] } - }, - "43": { + } + } + }, + "30": { + "mapping": { + "id": 30, + "name": "eth1/4/6", + "controllingPort": 25, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 5 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 5 } } ] @@ -31916,21 +2590,21 @@ } } }, - "116": { + "31": { "mapping": { - "id": 116, - "name": "eth1/15/4", - "controllingPort": 115, + "id": 31, + "name": "eth1/4/7", + "controllingPort": 25, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 6 } } } @@ -31939,138 +2613,171 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 6 } } ] } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 3 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 3 - } - } - ] + } + } + }, + "32": { + "mapping": { + "id": 32, + "name": "eth1/4/8", + "controllingPort": 25, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 7 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core3", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip4", + "lane": 7 } } ] } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 3 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 3 - } - } - ] + } + } + }, + "33": { + "mapping": { + "id": 33, + "name": "eth1/5/1", + "controllingPort": 33, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 2 + } } - } - } - }, - "117": { - "mapping": { - "id": 117, - "name": "eth1/15/5", - "controllingPort": 113, - "pins": [ + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 3 + } + } + }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 4 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 4 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 5 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 5 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 6 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 7 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 7 } } @@ -32080,157 +2787,63 @@ "scope": 0 }, "supportedProfiles": { - "45": { - "subsumedPorts": [ - 118, - 119, - 120 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 - } - } - ] - } - }, - "38": { + "50": { "subsumedPorts": [ - 118, - 119, - 120 + 34, + 35, + 36, + 37, + 38, + 39, + 40 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 - } - } - ] - } - }, - "24": { - "subsumedPorts": [ - 118, - 119, - 120 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 7 } } @@ -32238,217 +2851,112 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 - } - } - ] - } - }, - "25": { - "subsumedPorts": [ - 118, - 119, - 120 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 3 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 7 } } ] } }, - "54": { - "subsumedPorts": [ - 118 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - } - ] - } - }, - "22": { + "39": { "subsumedPorts": [ - 118, - 119, - 120 + 34, + 35, + 36, + 37, + 38, + 39, + 40 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 - } - } - ] - } - }, - "23": { - "subsumedPorts": [ - 118, - 119, - 120 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 7 } } @@ -32456,66 +2964,50 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 3 } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 5 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 6 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 7 } } ] @@ -32526,36 +3018,16 @@ "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 0 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 0 } } ] @@ -32563,21 +3035,21 @@ } } }, - "118": { + "34": { "mapping": { - "id": 118, - "name": "eth1/15/6", - "controllingPort": 117, + "id": 34, + "name": "eth1/5/2", + "controllingPort": 33, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 1 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 1 } } } @@ -32586,81 +3058,21 @@ "scope": 0 }, "supportedProfiles": { - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - } - ] - } - }, "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 1 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 1 } } ] @@ -32668,33 +3080,21 @@ } } }, - "119": { + "35": { "mapping": { - "id": 119, - "name": "eth1/15/7", - "controllingPort": 117, + "id": 35, + "name": "eth1/5/3", + "controllingPort": 33, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 - } - } - }, - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 2 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 2 } } } @@ -32703,116 +3103,66 @@ "scope": 0 }, "supportedProfiles": { - "54": { - "subsumedPorts": [ - 120 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 - } - } - ] - } - }, - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 2 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 2 } } ] } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 - } - } - ] + } + } + }, + "36": { + "mapping": { + "id": 36, + "name": "eth1/5/4", + "controllingPort": 33, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 3 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 3 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 3 } } ] @@ -32820,21 +3170,21 @@ } } }, - "120": { + "37": { "mapping": { - "id": 120, - "name": "eth1/15/8", - "controllingPort": 119, + "id": 37, + "name": "eth1/5/5", + "controllingPort": 33, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 4 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 4 } } } @@ -32843,72 +3193,147 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 4 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 4 } } ] } - }, - "47": { + } + } + }, + "38": { + "mapping": { + "id": 38, + "name": "eth1/5/6", + "controllingPort": 33, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 5 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 5 } } ] } - }, + } + } + }, + "39": { + "mapping": { + "id": 39, + "name": "eth1/5/7", + "controllingPort": 33, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 6 } } ] } - }, - "43": { + } + } + }, + "40": { + "mapping": { + "id": 40, + "name": "eth1/5/8", + "controllingPort": 33, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip5", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core14", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core4", "lane": 7 } } @@ -32916,7 +3341,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip15", + "chip": "TRANSCEIVER-OSFP-slot1/chip5", "lane": 7 } } @@ -32925,104 +3350,104 @@ } } }, - "121": { + "41": { "mapping": { - "id": 121, - "name": "eth1/16/1", - "controllingPort": 121, + "id": 41, + "name": "eth1/6/1", + "controllingPort": 41, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 0 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 0 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 1 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 1 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 2 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 2 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 3 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 3 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 4 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 4 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 5 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 5 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 6 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 6 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 7 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 7 } } @@ -33034,61 +3459,61 @@ "supportedProfiles": { "50": { "subsumedPorts": [ - 122, - 123, - 124, - 125, - 126, - 127, - 128 + 42, + 43, + 44, + 45, + 46, + 47, + 48 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 3 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 7 } } @@ -33096,49 +3521,49 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 7 } } @@ -33147,61 +3572,61 @@ }, "39": { "subsumedPorts": [ - 122, - 123, - 124, - 125, - 126, - 127, - 128 + 42, + 43, + 44, + 45, + 46, + 47, + 48 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 3 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 7 } } @@ -33209,604 +3634,720 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 7 } } ] } }, - "35": { - "subsumedPorts": [ - 122, - 123, - 124, - 125, - 126, - 127, - 128 - ], + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 0 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 0 } } ] } - }, - "45": { - "subsumedPorts": [ - 122, - 123, - 124 - ], + } + } + }, + "42": { + "mapping": { + "id": 42, + "name": "eth1/6/2", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 1 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 1 } - }, + } + ] + } + } + } + }, + "43": { + "mapping": { + "id": 43, + "name": "eth1/6/3", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", "lane": 2 } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 - } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 2 } - }, + } + ] + } + } + } + }, + "44": { + "mapping": { + "id": 44, + "name": "eth1/6/4", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 3 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip6", "lane": 3 } } ] } - }, - "38": { - "subsumedPorts": [ - 122, - 123, - 124 - ], + } + } + }, + "45": { + "mapping": { + "id": 45, + "name": "eth1/6/5", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 4 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 4 } - }, + } + ] + } + } + } + }, + "46": { + "mapping": { + "id": 46, + "name": "eth1/6/6", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 5 } - }, + } + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 5 + } + } + ] + } + } + } + }, + "47": { + "mapping": { + "id": 47, + "name": "eth1/6/7", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 6 } } ] } - }, - "24": { - "subsumedPorts": [ - 122, - 123, - 124 - ], + } + } + }, + "48": { + "mapping": { + "id": 48, + "name": "eth1/6/8", + "controllingPort": 41, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core5", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip6", + "lane": 7 } } ] } - }, - "25": { + } + } + }, + "49": { + "mapping": { + "id": 49, + "name": "eth1/7/1", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { "subsumedPorts": [ - 122, - 123, - 124 + 50, + 51, + 52, + 53, + 54, + 55, + 56 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 3 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 } } - ] - } - }, - "54": { - "subsumedPorts": [ - 122 - ], - "pins": { - "iphy": [ + ], + "transceiver": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 1 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 } - } - ] - } - }, - "22": { - "subsumedPorts": [ - 122, - 123, - 124 - ], - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 } } - ], - "transceiver": [ + ] + } + }, + "39": { + "subsumedPorts": [ + 50, + 51, + 52, + 53, + 54, + 55, + 56 + ], + "pins": { + "iphy": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 3 } - } - ] - } - }, - "23": { - "subsumedPorts": [ - 122, - 123, - 124 - ], - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 3 } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 } } ] @@ -33817,27 +4358,7 @@ "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 0 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 0 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 0 } } @@ -33845,7 +4366,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 0 } } @@ -33854,20 +4375,20 @@ } } }, - "122": { + "50": { "mapping": { - "id": 122, - "name": "eth1/16/2", - "controllingPort": 121, + "id": 50, + "name": "eth1/7/2", + "controllingPort": 49, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 1 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 1 } } @@ -33877,72 +4398,12 @@ "scope": 0 }, "supportedProfiles": { - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - } - ] - } - }, "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 1 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 1 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 1 } } @@ -33950,7 +4411,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 1 } } @@ -33959,122 +4420,35 @@ } } }, - "123": { + "51": { "mapping": { - "id": 123, - "name": "eth1/16/3", - "controllingPort": 121, + "id": 51, + "name": "eth1/7/3", + "controllingPort": 49, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - } - }, - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 - } - } - } - ], - "portType": 0, - "scope": 0 - }, - "supportedProfiles": { - "54": { - "subsumedPorts": [ - 124 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 - } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 - } - } - ] + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 2 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", "lane": 2 } } @@ -34082,28 +4456,53 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip7", "lane": 2 } } ] } - }, - "43": { + } + } + }, + "52": { + "mapping": { + "id": 52, + "name": "eth1/7/4", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 2 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 3 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 2 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 } } ] @@ -34111,21 +4510,21 @@ } } }, - "124": { + "53": { "mapping": { - "id": 124, - "name": "eth1/16/4", - "controllingPort": 123, + "id": 53, + "name": "eth1/7/5", + "controllingPort": 49, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 } } } @@ -34134,81 +4533,156 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 } } ] } - }, - "47": { + } + } + }, + "54": { + "mapping": { + "id": 54, + "name": "eth1/7/6", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 } } ] } - }, + } + } + }, + "55": { + "mapping": { + "id": 55, + "name": "eth1/7/7", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 } } ] } - }, - "43": { + } + } + }, + "56": { + "mapping": { + "id": 56, + "name": "eth1/7/8", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 3 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 3 + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 } } ] @@ -34216,216 +4690,170 @@ } } }, - "125": { + "57": { "mapping": { - "id": 125, - "name": "eth1/16/5", - "controllingPort": 121, + "id": 57, + "name": "eth1/8/1", + "controllingPort": 57, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 } } }, { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 } } - } - ], - "portType": 0, - "scope": 0 - }, - "supportedProfiles": { - "45": { - "subsumedPorts": [ - 126, - 127, - 128 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } } - }, - "38": { + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { "subsumedPorts": [ - 126, - 127, - 128 + 58, + 59, + 60, + 61, + 62, + 63, + 64 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "24": { - "subsumedPorts": [ - 126, - 127, - 128 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 7 } } @@ -34433,217 +4861,112 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "25": { - "subsumedPorts": [ - 126, - 127, - 128 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 4 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 5 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 6 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 7 } } ] } }, - "54": { - "subsumedPorts": [ - 126 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - } - ] - } - }, - "22": { + "39": { "subsumedPorts": [ - 126, - 127, - 128 + 58, + 59, + 60, + 61, + 62, + 63, + 64 ], "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "23": { - "subsumedPorts": [ - 126, - 127, - 128 - ], - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 4 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 5 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 6 } }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 7 } } @@ -34651,106 +4974,70 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 } }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 4 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 } - } - ] - } - }, - "49": { - "pins": { - "iphy": [ + }, { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 } - } - ], - "transceiver": [ + }, { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 } } ] } }, - "43": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 4 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 4 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 } } ] @@ -34758,21 +5045,21 @@ } } }, - "126": { + "58": { "mapping": { - "id": 126, - "name": "eth1/16/6", - "controllingPort": 125, + "id": 58, + "name": "eth1/8/2", + "controllingPort": 57, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 } } } @@ -34781,81 +5068,66 @@ "scope": 0 }, "supportedProfiles": { - "56": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 } } ] } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - } - ] + } + } + }, + "59": { + "mapping": { + "id": 59, + "name": "eth1/8/3", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } } - }, + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 5 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 5 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 } } ] @@ -34863,33 +5135,21 @@ } } }, - "127": { + "60": { "mapping": { - "id": 127, - "name": "eth1/16/7", - "controllingPort": 125, + "id": 60, + "name": "eth1/8/4", + "controllingPort": 57, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 - }, - "z": { - "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 - } - } - }, - { - "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 } } } @@ -34898,107 +5158,147 @@ "scope": 0 }, "supportedProfiles": { - "54": { - "subsumedPorts": [ - 128 - ], + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 - } - }, - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 - } - }, - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 } } ] } - }, - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 - } - } - ] + } + } + }, + "61": { + "mapping": { + "id": 61, + "name": "eth1/8/5", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } } - }, - "47": { + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 } } ] } - }, + } + } + }, + "62": { + "mapping": { + "id": 62, + "name": "eth1/8/6", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 6 + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 } } ], "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 6 + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 } } ] } - }, - "43": { + } + } + }, + "63": { + "mapping": { + "id": 63, + "name": "eth1/8/7", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 6 } } @@ -35006,7 +5306,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 6 } } @@ -35015,20 +5315,20 @@ } } }, - "128": { + "64": { "mapping": { - "id": 128, - "name": "eth1/16/8", - "controllingPort": 127, + "id": 64, + "name": "eth1/8/8", + "controllingPort": 57, "pins": [ { "a": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 7 }, "z": { "end": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 7 } } @@ -35038,72 +5338,12 @@ "scope": 0 }, "supportedProfiles": { - "56": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "47": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, "49": { "pins": { "iphy": [ { "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", - "lane": 7 - } - } - ], - "transceiver": [ - { - "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", - "lane": 7 - } - } - ] - } - }, - "43": { - "pins": { - "iphy": [ - { - "id": { - "chip": "NPU-J4SIM_NIF-slot1/chip1/core15", + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", "lane": 7 } } @@ -35111,7 +5351,7 @@ "transceiver": [ { "id": { - "chip": "TRANSCEIVER-OSFP-slot1/chip16", + "chip": "TRANSCEIVER-OSFP-slot1/chip8", "lane": 7 } } @@ -35162,46 +5402,6 @@ "type": 1, "physicalID": 7 }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core8", - "type": 1, - "physicalID": 8 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core9", - "type": 1, - "physicalID": 9 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core10", - "type": 1, - "physicalID": 10 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core11", - "type": 1, - "physicalID": 11 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core12", - "type": 1, - "physicalID": 12 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core13", - "type": 1, - "physicalID": 13 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core14", - "type": 1, - "physicalID": 14 - }, - { - "name": "NPU-J4SIM_NIF-slot1/chip1/core15", - "type": 1, - "physicalID": 15 - }, { "name": "TRANSCEIVER-OSFP-slot1/chip1", "type": 3, @@ -35241,139 +5441,9 @@ "name": "TRANSCEIVER-OSFP-slot1/chip8", "type": 3, "physicalID": 7 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip9", - "type": 3, - "physicalID": 8 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip10", - "type": 3, - "physicalID": 9 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip11", - "type": 3, - "physicalID": 10 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip12", - "type": 3, - "physicalID": 11 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip13", - "type": 3, - "physicalID": 12 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip14", - "type": 3, - "physicalID": 13 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip15", - "type": 3, - "physicalID": 14 - }, - { - "name": "TRANSCEIVER-OSFP-slot1/chip16", - "type": 3, - "physicalID": 15 } ], "platformSupportedProfiles": [ - { - "factor": { - "profileID": 35 - }, - "profile": { - "speed": 400000, - "iphy": { - "numLanes": 8, - "modulation": 2, - "fec": 11, - "medium": 1, - "interfaceType": 13 - } - } - }, - { - "factor": { - "profileID": 38 - }, - "profile": { - "speed": 400000, - "iphy": { - "numLanes": 4, - "modulation": 2, - "fec": 11, - "medium": 2, - "interfaceType": 21 - } - } - }, - { - "factor": { - "profileID": 39 - }, - "profile": { - "speed": 800000, - "iphy": { - "numLanes": 8, - "modulation": 2, - "fec": 11, - "medium": 2, - "interfaceType": 23 - } - } - }, - { - "factor": { - "profileID": 43 - }, - "profile": { - "speed": 50000, - "iphy": { - "numLanes": 1, - "modulation": 2, - "fec": 544, - "medium": 1, - "interfaceType": 10 - } - } - }, - { - "factor": { - "profileID": 45 - }, - "profile": { - "speed": 400000, - "iphy": { - "numLanes": 4, - "modulation": 2, - "fec": 11, - "medium": 1, - "interfaceType": 12 - } - } - }, - { - "factor": { - "profileID": 47 - }, - "profile": { - "speed": 100000, - "iphy": { - "numLanes": 1, - "modulation": 2, - "fec": 544, - "medium": 2, - "interfaceType": 20 - } - } - }, { "factor": { "profileID": 49 @@ -35406,91 +5476,16 @@ }, { "factor": { - "profileID": 23 - }, - "profile": { - "speed": 100000, - "iphy": { - "numLanes": 4, - "modulation": 1, - "fec": 528, - "medium": 2, - "interfaceType": 21 - } - } - }, - { - "factor": { - "profileID": 54 - }, - "profile": { - "speed": 200000, - "iphy": { - "numLanes": 2, - "modulation": 2, - "fec": 544, - "medium": 1, - "interfaceType": 11 - } - } - }, - { - "factor": { - "profileID": 22 - }, - "profile": { - "speed": 100000, - "iphy": { - "numLanes": 4, - "modulation": 1, - "fec": 528, - "medium": 1, - "interfaceType": 12 - } - } - }, - { - "factor": { - "profileID": 24 - }, - "profile": { - "speed": 200000, - "iphy": { - "numLanes": 4, - "modulation": 2, - "fec": 11, - "medium": 1, - "interfaceType": 12 - } - } - }, - { - "factor": { - "profileID": 25 + "profileID": 39 }, "profile": { - "speed": 200000, + "speed": 800000, "iphy": { - "numLanes": 4, + "numLanes": 8, "modulation": 2, "fec": 11, "medium": 2, - "interfaceType": 21 - } - } - }, - { - "factor": { - "profileID": 56 - }, - "profile": { - "speed": 100000, - "iphy": { - "numLanes": 1, - "modulation": 2, - "fec": 544, - "medium": 1, - "interfaceType": 10 + "interfaceType": 23 } } } diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv index fa5757e5a1721..0e743858d3792 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_port_profile_mapping.csv @@ -1,129 +1,65 @@ -Global_PortID,Logical_PortID,Port_Name,Supported_Port_Profiles,Attached_CoreID,Attached_Core_PortID,Virtual_Device_ID,Port_Type,Scope -1,1,eth1/1/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -2,2,eth1/1/2,56-47-49-43,,,,0,0 -3,3,eth1/1/3,54-56-47-49-43,,,,0,0 -4,4,eth1/1/4,56-47-49-43,,,,0,0 -5,5,eth1/1/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -6,6,eth1/1/6,56-47-49-43,,,,0,0 -7,7,eth1/1/7,54-56-47-49-43,,,,0,0 -8,8,eth1/1/8,56-47-49-43,,,,0,0 -9,9,eth1/2/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -10,10,eth1/2/2,56-47-49-43,,,,0,0 -11,11,eth1/2/3,54-56-47-49-43,,,,0,0 -12,12,eth1/2/4,56-47-49-43,,,,0,0 -13,13,eth1/2/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -14,14,eth1/2/6,56-47-49-43,,,,0,0 -15,15,eth1/2/7,54-56-47-49-43,,,,0,0 -16,16,eth1/2/8,56-47-49-43,,,,0,0 -17,17,eth1/3/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -18,18,eth1/3/2,56-47-49-43,,,,0,0 -19,19,eth1/3/3,54-56-47-49-43,,,,0,0 -20,20,eth1/3/4,56-47-49-43,,,,0,0 -21,21,eth1/3/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -22,22,eth1/3/6,56-47-49-43,,,,0,0 -23,23,eth1/3/7,54-56-47-49-43,,,,0,0 -24,24,eth1/3/8,56-47-49-43,,,,0,0 -25,25,eth1/4/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -26,26,eth1/4/2,56-47-49-43,,,,0,0 -27,27,eth1/4/3,54-56-47-49-43,,,,0,0 -28,28,eth1/4/4,56-47-49-43,,,,0,0 -29,29,eth1/4/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -30,30,eth1/4/6,56-47-49-43,,,,0,0 -31,31,eth1/4/7,54-56-47-49-43,,,,0,0 -32,32,eth1/4/8,56-47-49-43,,,,0,0 -33,33,eth1/5/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -34,34,eth1/5/2,56-47-49-43,,,,0,0 -35,35,eth1/5/3,54-56-47-49-43,,,,0,0 -36,36,eth1/5/4,56-47-49-43,,,,0,0 -37,37,eth1/5/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -38,38,eth1/5/6,56-47-49-43,,,,0,0 -39,39,eth1/5/7,54-56-47-49-43,,,,0,0 -40,40,eth1/5/8,56-47-49-43,,,,0,0 -41,41,eth1/6/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -42,42,eth1/6/2,56-47-49-43,,,,0,0 -43,43,eth1/6/3,54-56-47-49-43,,,,0,0 -44,44,eth1/6/4,56-47-49-43,,,,0,0 -45,45,eth1/6/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -46,46,eth1/6/6,56-47-49-43,,,,0,0 -47,47,eth1/6/7,54-56-47-49-43,,,,0,0 -48,48,eth1/6/8,56-47-49-43,,,,0,0 -49,49,eth1/7/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -50,50,eth1/7/2,56-47-49-43,,,,0,0 -51,51,eth1/7/3,54-56-47-49-43,,,,0,0 -52,52,eth1/7/4,56-47-49-43,,,,0,0 -53,53,eth1/7/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -54,54,eth1/7/6,56-47-49-43,,,,0,0 -55,55,eth1/7/7,54-56-47-49-43,,,,0,0 -56,56,eth1/7/8,56-47-49-43,,,,0,0 -57,57,eth1/8/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -58,58,eth1/8/2,56-47-49-43,,,,0,0 -59,59,eth1/8/3,54-56-47-49-43,,,,0,0 -60,60,eth1/8/4,56-47-49-43,,,,0,0 -61,61,eth1/8/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -62,62,eth1/8/6,56-47-49-43,,,,0,0 -63,63,eth1/8/7,54-56-47-49-43,,,,0,0 -64,64,eth1/8/8,56-47-49-43,,,,0,0 -65,65,eth1/9/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -66,66,eth1/9/2,56-47-49-43,,,,0,0 -67,67,eth1/9/3,54-56-47-49-43,,,,0,0 -68,68,eth1/9/4,56-47-49-43,,,,0,0 -69,69,eth1/9/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -70,70,eth1/9/6,56-47-49-43,,,,0,0 -71,71,eth1/9/7,54-56-47-49-43,,,,0,0 -72,72,eth1/9/8,56-47-49-43,,,,0,0 -73,73,eth1/10/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -74,74,eth1/10/2,56-47-49-43,,,,0,0 -75,75,eth1/10/3,54-56-47-49-43,,,,0,0 -76,76,eth1/10/4,56-47-49-43,,,,0,0 -77,77,eth1/10/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -78,78,eth1/10/6,56-47-49-43,,,,0,0 -79,79,eth1/10/7,54-56-47-49-43,,,,0,0 -80,80,eth1/10/8,56-47-49-43,,,,0,0 -81,81,eth1/11/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -82,82,eth1/11/2,56-47-49-43,,,,0,0 -83,83,eth1/11/3,54-56-47-49-43,,,,0,0 -84,84,eth1/11/4,56-47-49-43,,,,0,0 -85,85,eth1/11/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -86,86,eth1/11/6,56-47-49-43,,,,0,0 -87,87,eth1/11/7,54-56-47-49-43,,,,0,0 -88,88,eth1/11/8,56-47-49-43,,,,0,0 -89,89,eth1/12/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -90,90,eth1/12/2,56-47-49-43,,,,0,0 -91,91,eth1/12/3,54-56-47-49-43,,,,0,0 -92,92,eth1/12/4,56-47-49-43,,,,0,0 -93,93,eth1/12/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -94,94,eth1/12/6,56-47-49-43,,,,0,0 -95,95,eth1/12/7,54-56-47-49-43,,,,0,0 -96,96,eth1/12/8,56-47-49-43,,,,0,0 -97,97,eth1/13/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -98,98,eth1/13/2,56-47-49-43,,,,0,0 -99,99,eth1/13/3,54-56-47-49-43,,,,0,0 -100,100,eth1/13/4,56-47-49-43,,,,0,0 -101,101,eth1/13/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -102,102,eth1/13/6,56-47-49-43,,,,0,0 -103,103,eth1/13/7,54-56-47-49-43,,,,0,0 -104,104,eth1/13/8,56-47-49-43,,,,0,0 -105,105,eth1/14/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -106,106,eth1/14/2,56-47-49-43,,,,0,0 -107,107,eth1/14/3,54-56-47-49-43,,,,0,0 -108,108,eth1/14/4,56-47-49-43,,,,0,0 -109,109,eth1/14/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -110,110,eth1/14/6,56-47-49-43,,,,0,0 -111,111,eth1/14/7,54-56-47-49-43,,,,0,0 -112,112,eth1/14/8,56-47-49-43,,,,0,0 -113,113,eth1/15/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -114,114,eth1/15/2,56-47-49-43,,,,0,0 -115,115,eth1/15/3,54-56-47-49-43,,,,0,0 -116,116,eth1/15/4,56-47-49-43,,,,0,0 -117,117,eth1/15/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -118,118,eth1/15/6,56-47-49-43,,,,0,0 -119,119,eth1/15/7,54-56-47-49-43,,,,0,0 -120,120,eth1/15/8,56-47-49-43,,,,0,0 -121,121,eth1/16/1,50-39-35-45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -122,122,eth1/16/2,56-47-49-43,,,,0,0 -123,123,eth1/16/3,54-56-47-49-43,,,,0,0 -124,124,eth1/16/4,56-47-49-43,,,,0,0 -125,125,eth1/16/5,45-38-24-25-54-22-23-56-47-49-43,,,,0,0 -126,126,eth1/16/6,56-47-49-43,,,,0,0 -127,127,eth1/16/7,54-56-47-49-43,,,,0,0 -128,128,eth1/16/8,56-47-49-43,,,,0,0 +Global_PortID,Logical_PortID,Port_Name,Supported_Port_Profiles,Attached_CoreID,Attached_Core_PortID,Virtual_Device_ID,Port_Type,Scope,Parent_Port,Controlling_Port +1,1,eth1/1/1,50-39-49,,,,0,0,,1 +2,2,eth1/1/2,49,,,,0,0,,1 +3,3,eth1/1/3,49,,,,0,0,,1 +4,4,eth1/1/4,49,,,,0,0,,1 +5,5,eth1/1/5,49,,,,0,0,,1 +6,6,eth1/1/6,49,,,,0,0,,1 +7,7,eth1/1/7,49,,,,0,0,,1 +8,8,eth1/1/8,49,,,,0,0,,1 +9,9,eth1/2/1,50-39-49,,,,0,0,,9 +10,10,eth1/2/2,49,,,,0,0,,9 +11,11,eth1/2/3,49,,,,0,0,,9 +12,12,eth1/2/4,49,,,,0,0,,9 +13,13,eth1/2/5,49,,,,0,0,,9 +14,14,eth1/2/6,49,,,,0,0,,9 +15,15,eth1/2/7,49,,,,0,0,,9 +16,16,eth1/2/8,49,,,,0,0,,9 +17,17,eth1/3/1,50-39-49,,,,0,0,,17 +18,18,eth1/3/2,49,,,,0,0,,17 +19,19,eth1/3/3,49,,,,0,0,,17 +20,20,eth1/3/4,49,,,,0,0,,17 +21,21,eth1/3/5,49,,,,0,0,,17 +22,22,eth1/3/6,49,,,,0,0,,17 +23,23,eth1/3/7,49,,,,0,0,,17 +24,24,eth1/3/8,49,,,,0,0,,17 +25,25,eth1/4/1,50-39-49,,,,0,0,,25 +26,26,eth1/4/2,49,,,,0,0,,25 +27,27,eth1/4/3,49,,,,0,0,,25 +28,28,eth1/4/4,49,,,,0,0,,25 +29,29,eth1/4/5,49,,,,0,0,,25 +30,30,eth1/4/6,49,,,,0,0,,25 +31,31,eth1/4/7,49,,,,0,0,,25 +32,32,eth1/4/8,49,,,,0,0,,25 +33,33,eth1/5/1,50-39-49,,,,0,0,,33 +34,34,eth1/5/2,49,,,,0,0,,33 +35,35,eth1/5/3,49,,,,0,0,,33 +36,36,eth1/5/4,49,,,,0,0,,33 +37,37,eth1/5/5,49,,,,0,0,,33 +38,38,eth1/5/6,49,,,,0,0,,33 +39,39,eth1/5/7,49,,,,0,0,,33 +40,40,eth1/5/8,49,,,,0,0,,33 +41,41,eth1/6/1,50-39-49,,,,0,0,,41 +42,42,eth1/6/2,49,,,,0,0,,41 +43,43,eth1/6/3,49,,,,0,0,,41 +44,44,eth1/6/4,49,,,,0,0,,41 +45,45,eth1/6/5,49,,,,0,0,,41 +46,46,eth1/6/6,49,,,,0,0,,41 +47,47,eth1/6/7,49,,,,0,0,,41 +48,48,eth1/6/8,49,,,,0,0,,41 +49,49,eth1/7/1,50-39-49,,,,0,0,,49 +50,50,eth1/7/2,49,,,,0,0,,49 +51,51,eth1/7/3,49,,,,0,0,,49 +52,52,eth1/7/4,49,,,,0,0,,49 +53,53,eth1/7/5,49,,,,0,0,,49 +54,54,eth1/7/6,49,,,,0,0,,49 +55,55,eth1/7/7,49,,,,0,0,,49 +56,56,eth1/7/8,49,,,,0,0,,49 +57,57,eth1/8/1,50-39-49,,,,0,0,,57 +58,58,eth1/8/2,49,,,,0,0,,57 +59,59,eth1/8/3,49,,,,0,0,,57 +60,60,eth1/8/4,49,,,,0,0,,57 +61,61,eth1/8/5,49,,,,0,0,,57 +62,62,eth1/8/6,49,,,,0,0,,57 +63,63,eth1/8/7,49,,,,0,0,,57 +64,64,eth1/8/8,49,,,,0,0,,57 diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv index de57fb84804f9..21e1941b33437 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_profile_settings.csv @@ -1,15 +1,4 @@ Port_Speed(mbps),A_CHIP_TYPE,Z_CHIP_TYPE,NUM_LANES,Modulation,A_FEC,Z_FEC,MEDIA_TYPE,A_Interface_Type,Z_Interface_Type -100000,NPU,TRANSCEIVER,1,PAM4,RS544,,OPTICAL,SR, 100000,NPU,TRANSCEIVER,1,PAM4,NONE,,COPPER,CR, -100000,NPU,TRANSCEIVER,1,PAM4,RS544,,COPPER,CR, -100000,NPU,TRANSCEIVER,4,NRZ,RS528,,COPPER,CR4, -100000,NPU,TRANSCEIVER,4,NRZ,RS528,,OPTICAL,SR4, -200000,NPU,TRANSCEIVER,2,PAM4,RS544,,COPPER,CR2, -200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, -200000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,SR4, -400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,OPTICAL,SR4, -400000,NPU,TRANSCEIVER,4,PAM4,RS544_2N,,COPPER,CR4, -400000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, -50000,NPU,TRANSCEIVER,1,PAM4,RS544,,COPPER,CR, 800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,OPTICAL,SR8, 800000,NPU,TRANSCEIVER,8,PAM4,RS544_2N,,COPPER,CR8, diff --git a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv index cb4736d04c2e0..c5e42320a4bba 100644 --- a/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv +++ b/fboss/lib/platform_mapping_v2/platforms/j4sim/j4sim_static_mapping.csv @@ -63,67 +63,3 @@ A_SLOT_ID,A_CHIP_ID,A_CHIP_TYPE,A_CORE_ID,A_CORE_TYPE,A_CORE_LANE,A_PHYSICAL_TX_ 1,1,NPU,7,J4SIM_NIF,5,5,5,N,N,1,8,TRANSCEIVER,0,OSFP,5,5,5,N,N 1,1,NPU,7,J4SIM_NIF,6,6,6,N,N,1,8,TRANSCEIVER,0,OSFP,6,6,6,N,N 1,1,NPU,7,J4SIM_NIF,7,7,7,N,N,1,8,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,8,J4SIM_NIF,0,0,0,N,N,1,9,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,8,J4SIM_NIF,1,1,1,N,N,1,9,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,8,J4SIM_NIF,2,2,2,N,N,1,9,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,8,J4SIM_NIF,3,3,3,N,N,1,9,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,8,J4SIM_NIF,4,4,4,N,N,1,9,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,8,J4SIM_NIF,5,5,5,N,N,1,9,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,8,J4SIM_NIF,6,6,6,N,N,1,9,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,8,J4SIM_NIF,7,7,7,N,N,1,9,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,9,J4SIM_NIF,0,0,0,N,N,1,10,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,9,J4SIM_NIF,1,1,1,N,N,1,10,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,9,J4SIM_NIF,2,2,2,N,N,1,10,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,9,J4SIM_NIF,3,3,3,N,N,1,10,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,9,J4SIM_NIF,4,4,4,N,N,1,10,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,9,J4SIM_NIF,5,5,5,N,N,1,10,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,9,J4SIM_NIF,6,6,6,N,N,1,10,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,9,J4SIM_NIF,7,7,7,N,N,1,10,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,10,J4SIM_NIF,0,0,0,N,N,1,11,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,10,J4SIM_NIF,1,1,1,N,N,1,11,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,10,J4SIM_NIF,2,2,2,N,N,1,11,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,10,J4SIM_NIF,3,3,3,N,N,1,11,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,10,J4SIM_NIF,4,4,4,N,N,1,11,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,10,J4SIM_NIF,5,5,5,N,N,1,11,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,10,J4SIM_NIF,6,6,6,N,N,1,11,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,10,J4SIM_NIF,7,7,7,N,N,1,11,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,11,J4SIM_NIF,0,0,0,N,N,1,12,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,11,J4SIM_NIF,1,1,1,N,N,1,12,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,11,J4SIM_NIF,2,2,2,N,N,1,12,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,11,J4SIM_NIF,3,3,3,N,N,1,12,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,11,J4SIM_NIF,4,4,4,N,N,1,12,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,11,J4SIM_NIF,5,5,5,N,N,1,12,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,11,J4SIM_NIF,6,6,6,N,N,1,12,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,11,J4SIM_NIF,7,7,7,N,N,1,12,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,12,J4SIM_NIF,0,0,0,N,N,1,13,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,12,J4SIM_NIF,1,1,1,N,N,1,13,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,12,J4SIM_NIF,2,2,2,N,N,1,13,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,12,J4SIM_NIF,3,3,3,N,N,1,13,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,12,J4SIM_NIF,4,4,4,N,N,1,13,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,12,J4SIM_NIF,5,5,5,N,N,1,13,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,12,J4SIM_NIF,6,6,6,N,N,1,13,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,12,J4SIM_NIF,7,7,7,N,N,1,13,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,13,J4SIM_NIF,0,0,0,N,N,1,14,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,13,J4SIM_NIF,1,1,1,N,N,1,14,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,13,J4SIM_NIF,2,2,2,N,N,1,14,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,13,J4SIM_NIF,3,3,3,N,N,1,14,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,13,J4SIM_NIF,4,4,4,N,N,1,14,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,13,J4SIM_NIF,5,5,5,N,N,1,14,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,13,J4SIM_NIF,6,6,6,N,N,1,14,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,13,J4SIM_NIF,7,7,7,N,N,1,14,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,14,J4SIM_NIF,0,0,0,N,N,1,15,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,14,J4SIM_NIF,1,1,1,N,N,1,15,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,14,J4SIM_NIF,2,2,2,N,N,1,15,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,14,J4SIM_NIF,3,3,3,N,N,1,15,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,14,J4SIM_NIF,4,4,4,N,N,1,15,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,14,J4SIM_NIF,5,5,5,N,N,1,15,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,14,J4SIM_NIF,6,6,6,N,N,1,15,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,14,J4SIM_NIF,7,7,7,N,N,1,15,TRANSCEIVER,0,OSFP,7,7,7,N,N -1,1,NPU,15,J4SIM_NIF,0,0,0,N,N,1,16,TRANSCEIVER,0,OSFP,0,0,0,N,N -1,1,NPU,15,J4SIM_NIF,1,1,1,N,N,1,16,TRANSCEIVER,0,OSFP,1,1,1,N,N -1,1,NPU,15,J4SIM_NIF,2,2,2,N,N,1,16,TRANSCEIVER,0,OSFP,2,2,2,N,N -1,1,NPU,15,J4SIM_NIF,3,3,3,N,N,1,16,TRANSCEIVER,0,OSFP,3,3,3,N,N -1,1,NPU,15,J4SIM_NIF,4,4,4,N,N,1,16,TRANSCEIVER,0,OSFP,4,4,4,N,N -1,1,NPU,15,J4SIM_NIF,5,5,5,N,N,1,16,TRANSCEIVER,0,OSFP,5,5,5,N,N -1,1,NPU,15,J4SIM_NIF,6,6,6,N,N,1,16,TRANSCEIVER,0,OSFP,6,6,6,N,N -1,1,NPU,15,J4SIM_NIF,7,7,7,N,N,1,16,TRANSCEIVER,0,OSFP,7,7,7,N,N diff --git a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON index 838a64b69f4da..fa992d0ddbf4f 100644 --- a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON +++ b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON @@ -190,110 +190,164 @@ "asicConfig": { "common": { "config": { - "appl_param_multi_cpu_agents": "0", - "dram_temperature_monitor_enable.BCM994EX": "0", - "ext_ram_enabled_bitmap.BCM994EX": "0", - "appl_param_oam_enable.BCM994EX": "0", - "appl_param_rcy_mirror_ports_range.BCM994EX": "100-170", - "bcm_stat_interval": "1000000", - "custom_feature_adapter_do_collect_enable.BCM994EX_ADAPTER": "1", - "custom_feature_cmicx_gen2_pdma_interface_optimization": "1", - "custom_feature_fabric_cgm_ddc_th_tune.BCM994EX": "1", - "custom_feature_programmability_standard_image_name.BCM994EX": "AI23", - "custom_feature_rx_fifo_monitoring_interval_ms": "200", - "custom_feature_ser_event_generate": "1", - "custom_feature_shel_arm_enable": "0", - "custom_feature_statdma_enable": "0", - "custom_feature_use_new_access.BCM994EX": "1", - "custom_feature_use_new_access.BCM994EX_ADAPTER": "1", - "custom_feature_vsqd_lossless_reject_enable": "1", - "customer_x_fap_ss": "1", - "deleted_buffers_file_path": "/tmp/dram_quarantine_deleted_buffers_file", - "dpp_db_path": "/root/brcmsim/tools/sand/db", - "dram_temperature_monitor_enable.BCM994EX_ADAPTER": "0", - "dtm_flow_mapping_mode_region_97.BCM994EX": "0", - "dtm_flow_mapping_mode_region_98.BCM994EX": "0", - "dtm_flow_mapping_mode_region_99.BCM994EX": "0", - "dtm_flow_mapping_mode_region_100.BCM994EX": "0", - "dtm_flow_mapping_mode_region_101.BCM994EX": "0", - "dtm_flow_mapping_mode_region_102.BCM994EX": "0", - "dtm_flow_mapping_mode_region_103.BCM994EX": "0", - "dtm_flow_mapping_mode_region_104.BCM994EX": "0", - "dtm_flow_mapping_mode_region_105.BCM994EX": "0", - "dtm_flow_mapping_mode_region_106.BCM994EX": "0", - "dtm_flow_mapping_mode_region_107.BCM994EX": "0", - "dtm_flow_mapping_mode_region_108.BCM994EX": "0", - "dtm_flow_mapping_mode_region_109.BCM994EX": "0", - "dtm_flow_mapping_mode_region_110.BCM994EX": "0", - "dtm_flow_mapping_mode_region_111.BCM994EX": "0", - "dtm_flow_mapping_mode_region_112.BCM994EX": "0", - "dtm_flow_mapping_mode_region_113.BCM994EX": "0", - "dtm_flow_mapping_mode_region_114.BCM994EX": "0", - "dtm_flow_mapping_mode_region_115.BCM994EX": "0", - "dtm_flow_mapping_mode_region_116.BCM994EX": "0", - "dtm_flow_mapping_mode_region_117.BCM994EX": "0", - "dtm_flow_mapping_mode_region_118.BCM994EX": "0", - "dtm_flow_mapping_mode_region_119.BCM994EX": "0", - "dtm_flow_mapping_mode_region_120.BCM994EX": "0", - "dtm_flow_nof_remote_cores_region.BCM994EX": "8", - "eventor_sbus_dma_channels.BCM994EX": "0,6,0,7", + "appl_param_rcy_mirror_ports_range.BCM9941X": "100-139", + "custom_feature_stop_on_access_init_error.BCM9941X": "0", + "port_priorities_cpu.BCM9941X": "1", + "ucode_port_0.BCM9941X": "CPU.0:core_0.0", + "ucode_port_200.BCM9941X": "CPU.8:core_1.200", + "ucode_port_201.BCM9941X": "CPU.16:core_0.201", + "ucode_port_202.BCM9941X": "CPU.24:core_2.202", + "ucode_port_203.BCM9941X": "CPU.32:core_3.203", + "ucode_port_204.BCM9941X": "CPU.10:core_1.204:datapath_1", + "ucode_port_205.BCM9941X": "CPU.18:core_0.205:datapath_1", + "ucode_port_206.BCM9941X": "CPU.26:core_2.206:datapath_1", + "ucode_port_207.BCM9941X": "CPU.34:core_3.207:datapath_1", + "ucode_port_1.BCM9941X": "D3CE1:core_0.1:datapath_0", + "ucode_port_13.BCM9941X": "XE128:core_3.13:datapath_0", + "ucode_port_14.BCM9941X": "XE129:core_0.14:datapath_0", + "ucode_port_15.BCM9941X": "XE130:core_1.15:datapath_0", + "ucode_port_16.BCM9941X": "XE131:core_1.16:datapath_0", + "ucode_port_17.BCM9941X": "CGE18:core_2.17", + "ucode_port_19.BCM9941X": "CCGE10:core_1.19", + "ucode_port_20.BCM9941X": "CDGE4_26:core_3.20", + "port_init_cl72_1.BCM9941X": "0", + "port_init_cl72_17.BCM9941X": "0", + "ucode_port_230.BCM9941X": "EVENTOR:core_0.230", + "ucode_port_240.BCM9941X": "OLP0:core_0.240", + "ucode_port_241.BCM9941X": "OLP1:core_0.241", + "ucode_port_221.BCM9941X": "RCY.21:core_0.221", + "ucode_port_222.BCM9941X": "RCY.22:core_1.222", + "ucode_port_223.BCM9941X": "RCY.23:core_2.223", + "ucode_port_224.BCM9941X": "RCY.24:core_3.224", + "tm_port_header_type_in_221.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_222.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_223.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_224.BCM9941X": "IBCH1_MODE", + "ucode_port_225.BCM9941X": "RCY.33:core_0.244:datapath_1", + "ucode_port_226.BCM9941X": "RCY.34:core_1.244:datapath_1", + "ucode_port_227.BCM9941X": "RCY.35:core_2.244:datapath_1", + "ucode_port_228.BCM9941X": "RCY.36:core_3.244:datapath_1", + "tm_port_header_type_in_225.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_226.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_227.BCM9941X": "IBCH1_MODE", + "tm_port_header_type_in_228.BCM9941X": "IBCH1_MODE", + "ucode_port_216.BCM9941X": "SAT:core_2.216", + "ucode_port_217.BCM9941X": "SAT:core_3.217", + "ucode_port_218.BCM9941X": "SAT:core_0.218", + "ucode_port_219.BCM9941X": "SAT:core_1.219", + "tm_port_header_type_in_216.BCM9941X": "INJECTED", + "tm_port_header_type_in_217.BCM9941X": "INJECTED", + "tm_port_header_type_in_218.BCM9941X": "INJECTED", + "tm_port_header_type_in_219.BCM9941X": "INJECTED", + "tm_port_header_type_out_216.BCM9941X": "CPU", + "tm_port_header_type_out_217.BCM9941X": "CPU", + "tm_port_header_type_out_218.BCM9941X": "CPU", + "tm_port_header_type_out_219.BCM9941X": "CPU", + "port_init_speed_sat.BCM9941X": "400000", + "warmboot_support.BCM9941X": "on", + "warmboot_support.BCM9941X_ADAPTER": "on", + "sw_state_max_size.BCM9941X": "1400000000", + "sw_state_max_size.BCM9941X_ADAPTER": "1400000000", + "stable_location.BCM9941X": "4", + "stable_location.BCM9941X_ADAPTER": "3", + "stable_filename.BCM9941X_ADAPTER": "warmboot_data_0", + "stable_filename.BCM9941X": "/dev/shm/warmboot_data_0", + "stable_filename.1.BCM9941X": "/dev/shm/warmboot_data_1", + "stable_filename.2.BCM9941X": "/dev/shm/warmboot_data_2", + "stable_size.BCM9941X": "1450000000", + "stable_size.BCM9941X_ADAPTER": "1450000000", + "dma_desc_aggregator_chain_length_max.BCM9941X": "256", + "dma_desc_aggregator_buff_size_kb.BCM9941X": "32", + "dma_desc_aggregator_enable_specific_MDB_LPM.BCM9941X": "1", + "dma_desc_aggregator_enable_specific_MDB_FEC.BCM9941X": "1", + "outlif_physical_phase_data_granularity_1.BCM9941X": "60", + "outlif_physical_phase_data_granularity_2.BCM9941X": "60", + "outlif_physical_phase_data_granularity_3.BCM9941X": "60", + "outlif_physical_phase_data_granularity_4.BCM9941X": "60", + "outlif_physical_phase_data_granularity_5.BCM9941X": "60", + "outlif_physical_phase_data_granularity_6.BCM9941X": "60", + "outlif_physical_phase_data_granularity_7.BCM9941X": "60", + "outlif_physical_phase_data_granularity_8.BCM9941X": "60", + "pmf_maps_payload_size.BCM9941X": "30", + "pmf_nexem2_stage.BCM9941X": "IPMF3", + "tm_port_header_type_in_0.BCM9941X": "INJECTED", + "tm_port_header_type_out_0.BCM9941X": "CPU", + "tm_port_header_type_in_200.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_200.BCM9941X": "ETH", + "tm_port_header_type_in_201.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_201.BCM9941X": "ETH", + "tm_port_header_type_in_202.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_202.BCM9941X": "ETH", + "tm_port_header_type_in_203.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_203.BCM9941X": "ETH", + "tm_port_header_type_in_204.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_204.BCM9941X": "ETH", + "tm_port_header_type_in_205.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_205.BCM9941X": "ETH", + "tm_port_header_type_in_206.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_206.BCM9941X": "ETH", + "tm_port_header_type_in_207.BCM9941X": "INJECTED_PP", + "tm_port_header_type_out_207.BCM9941X": "ETH", + "tm_port_header_type_in_230.BCM9941X": "INJECTED", + "tm_port_header_type_in_240.BCM9941X": "TM", + "tm_port_header_type_out_240.BCM9941X": "ETH", + "tm_port_header_type_in_241.BCM9941X": "TM", + "tm_port_header_type_out_241.BCM9941X": "ETH", + "fabric_connect_mode.BCM9941X": "SINGLE_FAP", + "fabric_distributed_system_enable.BCM9941X": "0", + "port_init_speed_fabric.BCM9941X": "212500", + "port_init_speed_xe13.BCM9941X": "10000", + "port_init_speed_xe14.BCM9941X": "10000", + "port_init_speed_xe15.BCM9941X": "10000", + "port_init_speed_xe16.BCM9941X": "10000", + "port_init_speed_xe.BCM9941X": "25000", + "port_init_speed_xl.BCM9941X": "40000", + "port_init_speed_le.BCM9941X": "50000", + "port_init_speed_ce.BCM9941X": "100000", + "port_init_speed_cc.BCM9941X": "200000", + "port_init_speed_cd.BCM9941X": "400000", + "port_init_speed_d3c.BCM9941X": "800000", + "port_init_speed_mdc.BCM9941X": "1600000", + "custom_feature_adapter_do_collect_enable.BCM9941X_ADAPTER": "1", + "mem_cache_enable_all.BCM9941X_ADAPTER": "1", + "custom_feature_use_new_access.BCM9941X": "1", + "custom_feature_use_new_access.BCM9941X_ADAPTER": "1", + "maximal_port_bandwidth.BCM9941X": "1800000", + "dtm_flow_mapping_mode_region_97.BCM9941X": "3", + "dtm_flow_mapping_mode_region_98.BCM9941X": "3", + "dtm_flow_mapping_mode_region_99.BCM9941X": "3", + "dtm_flow_mapping_mode_region_100.BCM9941X": "3", + "dtm_flow_mapping_mode_region_101.BCM9941X": "3", + "dtm_flow_mapping_mode_region_102.BCM9941X": "3", + "dtm_flow_mapping_mode_region_103.BCM9941X": "3", + "dtm_flow_mapping_mode_region_104.BCM9941X": "3", + "dtm_flow_mapping_mode_region_105.BCM9941X": "3", + "dtm_flow_mapping_mode_region_106.BCM9941X": "7", + "dtm_flow_mapping_mode_region_107.BCM9941X": "3", + "dtm_flow_mapping_mode_region_108.BCM9941X": "3", + "dtm_flow_mapping_mode_region_109.BCM9941X": "3", + "dtm_flow_mapping_mode_region_110.BCM9941X": "3", + "dtm_flow_mapping_mode_region_111.BCM9941X": "3", + "dtm_flow_mapping_mode_region_112.BCM9941X": "3", + "dtm_flow_mapping_mode_region_113.BCM9941X": "3", + "dtm_flow_mapping_mode_region_114.BCM9941X": "3", + "dtm_flow_mapping_mode_region_115.BCM9941X": "3", + "dtm_flow_mapping_mode_region_116.BCM9941X": "3", + "dtm_flow_mapping_mode_region_117.BCM9941X": "3", + "dtm_flow_mapping_mode_region_118.BCM9941X": "3", + "dtm_flow_mapping_mode_region_119.BCM9941X": "3", + "dtm_flow_mapping_mode_region_120.BCM9941X": "3", + "dtm_flow_nof_remote_cores_region.BCM9941X": "4", + "polled_irq_mode.BCM9941X_ADAPTER": "1", + "polled_irq_delay.BCM9941X_ADAPTER": "200000", + "dram_temperature_monitor_enable.BCM9941X_ADAPTER": "0", + "custom_feature_statdma_enable.BCM9941X_ADAPTER": "0", + "bcm_stat_interval.BCM9941X_ADAPTER": "0", + "bcm_stat_interval.BCM9941X": "0", + "pktio_driver_type.BCM9941X": "1", + "pktio_driver_type.BCM9941X_ADAPTER": "1", + "pci_override_dev": "0x9410", "fail_on_unsupported_attribute": "1", - "l3_ecmp_max_group_size": "512", - "macro_flow_hash_shuffle_random_seed": "34345645", - "maximal_port_bandwidth.BCM994EX": "1000000", - "mdb_profile.BCM994EX": "Elastic-Balanced", - "mem_cache_enable_all.BCM994EX_ADAPTER": "1", - "outlif_logical_to_physical_phase_map_1.BCM994EX": "S1", - "outlif_logical_to_physical_phase_map_2.BCM994EX": "L1", - "outlif_logical_to_physical_phase_map_3.BCM994EX": "S2", - "outlif_logical_to_physical_phase_map_4.BCM994EX": "L2", - "outlif_logical_to_physical_phase_map_5.BCM994EX": "M1", - "outlif_logical_to_physical_phase_map_6.BCM994EX": "M2", - "outlif_logical_to_physical_phase_map_7.BCM994EX": "M3", - "outlif_logical_to_physical_phase_map_8.BCM994EX": "XL", - "outlif_physical_phase_data_granularity_L1.BCM994EX": "60", - "outlif_physical_phase_data_granularity_L2.BCM994EX": "60", - "outlif_physical_phase_data_granularity_M1.BCM994EX": "60", - "outlif_physical_phase_data_granularity_M2.BCM994EX": "60", - "outlif_physical_phase_data_granularity_M3.BCM994EX": "60", - "outlif_physical_phase_data_granularity_S1.BCM994EX": "60", - "outlif_physical_phase_data_granularity_S2.BCM994EX": "60", - "outlif_physical_phase_data_granularity_XL.BCM994EX": "60", - "pci_override_dev": "0x94E0", - "AI23_mode": "4", - "pcie_host_intf_timeout_purge_enable": "0", - "perform_system_reset_when_needed": "1", - "phy_rx_polarity_flip.BCM994EX": "0", - "phy_tx_polarity_flip.BCM994EX": "0", - "pktio_driver_type": "1", - "pmf_maps_payload_size.BCM994EX": "30", - "pmf_nexem2_stage": "IPMF3", - "polled_irq_delay.BCM994EX_ADAPTER": "200000", - "polled_irq_mode.BCM994EX_ADAPTER": "1", - "port_fec_cc": "9", - "port_init_speed_cc.BCM994EX": "200000", - "port_init_speed_cd.BCM994EX": "400000", - "port_init_speed_ce.BCM994EX": "100000", - "port_init_speed_d3c.BCM994EX": "800000", - "port_init_speed_eventor.BCM994EX": "100000", - "port_init_speed_fabric.BCM994EX": "212500", - "port_init_speed_le.BCM994EX": "50000", - "port_init_speed_rcy.BCM994EX": "100000", - "port_init_speed_sat.BCM994EX": "400000", - "port_init_speed_xe.BCM994EX": "25000", - "port_init_speed_xe13.BCM994EX": "10000", - "port_init_speed_xe14.BCM994EX": "10000", - "port_init_speed_xe15.BCM994EX": "10000", - "port_init_speed_xe16.BCM994EX": "10000", - "port_init_speed_xl.BCM994EX": "40000", - "port_priorities": "8", - "port_priorities_cpu": "2", - "port_priorities_rcy": "2", - "port_priorities_sch.BCM994EX": "8", - "programmability_image_name.BCM994EX": "AI23", - "programmability_ucode_relative_path.BCM994EX": "pemla/ucode/AI23/jr3native/u_code_db2pem.txt", - "qos_map_multi_get_mode": "1", - "rif_id_max": "0x2000", "sai_dis_ctr_incr_on_port_ln_dn": "0", "sai_disable_srcmacqedstmac_ctrl": "0x1", "sai_eventor_port_lane_base": "1000", @@ -306,637 +360,7 @@ "sai_trigger_linkscan_remote_local_faults": "1", "sai_uncached_port_stats": "0x1", "sai_voq_wm_latency_enable": "1", - "sat_enable.BCM994EX_ADAPTER": "1", - "soc_family.BCM994EX": "BCM994EX", - "stable_location.BCM994EX": "4", - "stable_location.BCM994EX_ADAPTER": "4", - "stable_size": "1450000000", - "sw_state_max_size": "1400000000", - "tm_port_header_type_in_0.BCM994EX": "INJECTED", - "tm_port_header_type_in_1.BCM994EX": "INJECTED", - "tm_port_header_type_in_2.BCM994EX": "INJECTED", - "tm_port_header_type_in_3.BCM994EX": "INJECTED", - "tm_port_header_type_in_4.BCM994EX": "INJECTED", - "tm_port_header_type_in_5.BCM994EX": "INJECTED", - "tm_port_header_type_in_6.BCM994EX": "INJECTED", - "tm_port_header_type_in_7.BCM994EX": "INJECTED", - "tm_port_header_type_in_9.BCM994EX": "INJECTED", - "tm_port_header_type_in_10.BCM994EX": "INJECTED", - "ucode_port_240.BCM994EX": "OLP0:core_0.240", - "ucode_port_241.BCM994EX": "OLP1:core_0.241", - "ucode_port_0.BCM994EX": "CPU.0:core_0.0:datapath_0", - "ucode_port_1.BCM994EX": "CPU.8:core_0.1:datapath_1", - "ucode_port_2.BCM994EX": "CPU.16:core_0.2:datapath_0", - "ucode_port_3.BCM994EX": "CPU.24:core_1.0:datapath_0", - "ucode_port_4.BCM994EX": "CPU.32:core_1.1:datapath_1", - "ucode_port_5.BCM994EX": "CPU.40:core_2.0:datapath_0", - "ucode_port_6.BCM994EX": "CPU.48:core_2.1:datapath_1", - "ucode_port_7.BCM994EX": "CPU.56:core_3.0:datapath_0", - "ucode_port_8.BCM994EX": "CPU.64:core_3.1:datapath_1", - "ucode_port_9.BCM994EX": "CPU.72:core_4.0:datapath_0", - "ucode_port_10.BCM994EX": "CPU.80:core_4.1:datapath_1", - "ucode_port_11.BCM994EX": "CPU.88:core_5.0:datapath_0", - "ucode_port_12.BCM994EX": "CPU.96:core_5.1:datapath_1", - "ucode_port_13.BCM994EX": "CPU.104:core_6.0:datapath_0", - "ucode_port_14.BCM994EX": "CPU.112:core_6.1:datapath_1", - "ucode_port_15.BCM994EX": "CPU.120:core_7.0:datapath_0", - "ucode_port_16.BCM994EX": "CPU.128:core_7.1:datapath_1", - "ucode_port_17.BCM994EX": "RCY.0:core_0.3:datapath_0", - "ucode_port_18.BCM994EX": "RCY.8:core_0.4:datapath_1", - "ucode_port_19.BCM994EX": "RCY.16:core_1.2:datapath_0", - "ucode_port_20.BCM994EX": "RCY.24:core_1.3:datapath_1", - "ucode_port_21.BCM994EX": "RCY.32:core_2.2:datapath_0", - "ucode_port_22.BCM994EX": "RCY.40:core_2.3:datapath_1", - "ucode_port_23.BCM994EX": "RCY.48:core_3.2:datapath_0", - "ucode_port_24.BCM994EX": "RCY.56:core_3.3:datapath_1", - "ucode_port_25.BCM994EX": "RCY.64:core_4.2:datapath_0", - "ucode_port_26.BCM994EX": "RCY.72:core_4.3:datapath_1", - "ucode_port_27.BCM994EX": "RCY.80:core_5.2:datapath_0", - "ucode_port_28.BCM994EX": "RCY.88:core_5.3:datapath_1", - "ucode_port_29.BCM994EX": "RCY.96:core_6.2:datapath_0", - "ucode_port_30.BCM994EX": "RCY.104:core_6.3:datapath_1", - "ucode_port_31.BCM994EX": "RCY.112:core_7.2:datapath_0", - "ucode_port_32.BCM994EX": "RCY.120:core_7.3:datapath_1", - "ucode_port_33.BCM994EX": "EVENTOR:core_0.6:datapath_0", - "ucode_port_34.BCM994EX": "EVENTOR:core_4.4:datapath_0", - "ucode_port_35.BCM994EX": "D3CE.0:core_0.7:datapath_0", - "ucode_port_36.BCM994EX": "D3CE.1:core_0.8:datapath_0", - "ucode_port_37.BCM994EX": "D3CE.2:core_0.9:datapath_0", - "ucode_port_38.BCM994EX": "D3CE.3:core_0.10:datapath_0", - "ucode_port_39.BCM994EX": "D3CE.4:core_0.11:datapath_1", - "ucode_port_40.BCM994EX": "D3CE.5:core_0.12:datapath_1", - "ucode_port_41.BCM994EX": "D3CE.6:core_0.13:datapath_1", - "ucode_port_42.BCM994EX": "D3CE.7:core_0.14:datapath_1", - "ucode_port_43.BCM994EX": "D3CE.8:core_1.4:datapath_0", - "ucode_port_44.BCM994EX": "D3CE.9:core_1.5:datapath_0", - "ucode_port_45.BCM994EX": "D3CE.10:core_1.6:datapath_0", - "ucode_port_46.BCM994EX": "D3CE.11:core_1.7:datapath_0", - "ucode_port_47.BCM994EX": "D3CE.12:core_1.8:datapath_1", - "ucode_port_48.BCM994EX": "D3CE.13:core_1.9:datapath_1", - "ucode_port_49.BCM994EX": "D3CE.14:core_1.10:datapath_1", - "ucode_port_50.BCM994EX": "D3CE.15:core_1.11:datapath_1", - "ucode_port_51.BCM994EX": "D3CE.16:core_2.4:datapath_0", - "ucode_port_52.BCM994EX": "D3CE.17:core_2.5:datapath_0", - "ucode_port_53.BCM994EX": "D3CE.18:core_2.6:datapath_0", - "ucode_port_54.BCM994EX": "D3CE.19:core_2.7:datapath_0", - "ucode_port_55.BCM994EX": "D3CE.20:core_2.8:datapath_1", - "ucode_port_56.BCM994EX": "D3CE.21:core_2.9:datapath_1", - "ucode_port_57.BCM994EX": "D3CE.22:core_2.10:datapath_1", - "ucode_port_58.BCM994EX": "D3CE.23:core_2.11:datapath_1", - "ucode_port_59.BCM994EX": "D3CE.24:core_3.4:datapath_0", - "ucode_port_60.BCM994EX": "D3CE.25:core_3.5:datapath_0", - "ucode_port_61.BCM994EX": "D3CE.26:core_3.6:datapath_0", - "ucode_port_62.BCM994EX": "D3CE.27:core_3.7:datapath_0", - "ucode_port_63.BCM994EX": "D3CE.28:core_3.8:datapath_1", - "ucode_port_64.BCM994EX": "D3CE.29:core_3.9:datapath_1", - "ucode_port_65.BCM994EX": "D3CE.30:core_3.10:datapath_1", - "ucode_port_66.BCM994EX": "D3CE.31:core_3.11:datapath_1", - "ucode_port_67.BCM994EX": "D3CE.32:core_4.5:datapath_0", - "ucode_port_68.BCM994EX": "D3CE.33:core_4.6:datapath_0", - "ucode_port_69.BCM994EX": "D3CE.34:core_4.7:datapath_0", - "ucode_port_70.BCM994EX": "D3CE.35:core_4.8:datapath_0", - "ucode_port_71.BCM994EX": "D3CE.36:core_4.9:datapath_1", - "ucode_port_72.BCM994EX": "D3CE.37:core_4.10:datapath_1", - "ucode_port_73.BCM994EX": "D3CE.38:core_4.11:datapath_1", - "ucode_port_74.BCM994EX": "D3CE.39:core_4.12:datapath_1", - "ucode_port_75.BCM994EX": "D3CE.40:core_5.4:datapath_0", - "ucode_port_76.BCM994EX": "D3CE.41:core_5.5:datapath_0", - "ucode_port_77.BCM994EX": "D3CE.42:core_5.6:datapath_0", - "ucode_port_78.BCM994EX": "D3CE.43:core_5.7:datapath_0", - "ucode_port_79.BCM994EX": "D3CE.44:core_5.8:datapath_1", - "ucode_port_80.BCM994EX": "D3CE.45:core_5.9:datapath_1", - "ucode_port_81.BCM994EX": "D3CE.46:core_5.10:datapath_1", - "ucode_port_82.BCM994EX": "D3CE.47:core_5.11:datapath_1", - "ucode_port_83.BCM994EX": "D3CE.48:core_6.4:datapath_0", - "ucode_port_84.BCM994EX": "D3CE.49:core_6.5:datapath_0", - "ucode_port_85.BCM994EX": "D3CE.50:core_6.6:datapath_0", - "ucode_port_86.BCM994EX": "D3CE.51:core_6.7:datapath_0", - "ucode_port_87.BCM994EX": "D3CE.52:core_6.8:datapath_1", - "ucode_port_88.BCM994EX": "D3CE.53:core_6.9:datapath_1", - "ucode_port_89.BCM994EX": "D3CE.54:core_6.10:datapath_1", - "ucode_port_90.BCM994EX": "D3CE.55:core_6.11:datapath_1", - "ucode_port_91.BCM994EX": "D3CE.56:core_7.4:datapath_0", - "ucode_port_92.BCM994EX": "D3CE.57:core_7.5:datapath_0", - "ucode_port_93.BCM994EX": "D3CE.58:core_7.6:datapath_0", - "ucode_port_94.BCM994EX": "D3CE.59:core_7.7:datapath_0", - "ucode_port_95.BCM994EX": "D3CE.60:core_7.8:datapath_1", - "ucode_port_96.BCM994EX": "D3CE.61:core_7.9:datapath_1", - "ucode_port_97.BCM994EX": "D3CE.62:core_7.10:datapath_1", - "ucode_port_98.BCM994EX": "D3CE.63:core_7.11:datapath_1", - "lane_to_serdes_map_nif_lane0": "rx0:tx0", - "lane_to_serdes_map_nif_lane1": "rx1:tx1", - "lane_to_serdes_map_nif_lane2": "rx2:tx2", - "lane_to_serdes_map_nif_lane3": "rx3:tx3", - "lane_to_serdes_map_nif_lane4": "rx4:tx4", - "lane_to_serdes_map_nif_lane5": "rx5:tx5", - "lane_to_serdes_map_nif_lane6": "rx6:tx6", - "lane_to_serdes_map_nif_lane7": "rx7:tx7", - "lane_to_serdes_map_nif_lane8": "rx8:tx8", - "lane_to_serdes_map_nif_lane9": "rx9:tx9", - "lane_to_serdes_map_nif_lane10": "rx10:tx10", - "lane_to_serdes_map_nif_lane11": "rx11:tx11", - "lane_to_serdes_map_nif_lane12": "rx12:tx12", - "lane_to_serdes_map_nif_lane13": "rx13:tx13", - "lane_to_serdes_map_nif_lane14": "rx14:tx14", - "lane_to_serdes_map_nif_lane15": "rx15:tx15", - "lane_to_serdes_map_nif_lane16": "rx16:tx16", - "lane_to_serdes_map_nif_lane17": "rx17:tx17", - "lane_to_serdes_map_nif_lane18": "rx18:tx18", - "lane_to_serdes_map_nif_lane19": "rx19:tx19", - "lane_to_serdes_map_nif_lane20": "rx20:tx20", - "lane_to_serdes_map_nif_lane21": "rx21:tx21", - "lane_to_serdes_map_nif_lane22": "rx22:tx22", - "lane_to_serdes_map_nif_lane23": "rx23:tx23", - "lane_to_serdes_map_nif_lane24": "rx24:tx24", - "lane_to_serdes_map_nif_lane25": "rx25:tx25", - "lane_to_serdes_map_nif_lane26": "rx26:tx26", - "lane_to_serdes_map_nif_lane27": "rx27:tx27", - "lane_to_serdes_map_nif_lane28": "rx28:tx28", - "lane_to_serdes_map_nif_lane29": "rx29:tx29", - "lane_to_serdes_map_nif_lane30": "rx30:tx30", - "lane_to_serdes_map_nif_lane31": "rx31:tx31", - "lane_to_serdes_map_nif_lane32": "rx32:tx32", - "lane_to_serdes_map_nif_lane33": "rx33:tx33", - "lane_to_serdes_map_nif_lane34": "rx34:tx34", - "lane_to_serdes_map_nif_lane35": "rx35:tx35", - "lane_to_serdes_map_nif_lane36": "rx36:tx36", - "lane_to_serdes_map_nif_lane37": "rx37:tx37", - "lane_to_serdes_map_nif_lane38": "rx38:tx38", - "lane_to_serdes_map_nif_lane39": "rx39:tx39", - "lane_to_serdes_map_nif_lane40": "rx40:tx40", - "lane_to_serdes_map_nif_lane41": "rx41:tx41", - "lane_to_serdes_map_nif_lane42": "rx42:tx42", - "lane_to_serdes_map_nif_lane43": "rx43:tx43", - "lane_to_serdes_map_nif_lane44": "rx44:tx44", - "lane_to_serdes_map_nif_lane45": "rx45:tx45", - "lane_to_serdes_map_nif_lane46": "rx46:tx46", - "lane_to_serdes_map_nif_lane47": "rx47:tx47", - "lane_to_serdes_map_nif_lane48": "rx48:tx48", - "lane_to_serdes_map_nif_lane49": "rx49:tx49", - "lane_to_serdes_map_nif_lane50": "rx50:tx50", - "lane_to_serdes_map_nif_lane51": "rx51:tx51", - "lane_to_serdes_map_nif_lane52": "rx52:tx52", - "lane_to_serdes_map_nif_lane53": "rx53:tx53", - "lane_to_serdes_map_nif_lane54": "rx54:tx54", - "lane_to_serdes_map_nif_lane55": "rx55:tx55", - "lane_to_serdes_map_nif_lane56": "rx56:tx56", - "lane_to_serdes_map_nif_lane57": "rx57:tx57", - "lane_to_serdes_map_nif_lane58": "rx58:tx58", - "lane_to_serdes_map_nif_lane59": "rx59:tx59", - "lane_to_serdes_map_nif_lane60": "rx60:tx60", - "lane_to_serdes_map_nif_lane61": "rx61:tx61", - "lane_to_serdes_map_nif_lane62": "rx62:tx62", - "lane_to_serdes_map_nif_lane63": "rx63:tx63", - "lane_to_serdes_map_nif_lane64": "rx64:tx64", - "lane_to_serdes_map_nif_lane65": "rx65:tx65", - "lane_to_serdes_map_nif_lane66": "rx66:tx66", - "lane_to_serdes_map_nif_lane67": "rx67:tx67", - "lane_to_serdes_map_nif_lane68": "rx68:tx68", - "lane_to_serdes_map_nif_lane69": "rx69:tx69", - "lane_to_serdes_map_nif_lane70": "rx70:tx70", - "lane_to_serdes_map_nif_lane71": "rx71:tx71", - "lane_to_serdes_map_nif_lane72": "rx72:tx72", - "lane_to_serdes_map_nif_lane73": "rx73:tx73", - "lane_to_serdes_map_nif_lane74": "rx74:tx74", - "lane_to_serdes_map_nif_lane75": "rx75:tx75", - "lane_to_serdes_map_nif_lane76": "rx76:tx76", - "lane_to_serdes_map_nif_lane77": "rx77:tx77", - "lane_to_serdes_map_nif_lane78": "rx78:tx78", - "lane_to_serdes_map_nif_lane79": "rx79:tx79", - "lane_to_serdes_map_nif_lane80": "rx80:tx80", - "lane_to_serdes_map_nif_lane81": "rx81:tx81", - "lane_to_serdes_map_nif_lane82": "rx82:tx82", - "lane_to_serdes_map_nif_lane83": "rx83:tx83", - "lane_to_serdes_map_nif_lane84": "rx84:tx84", - "lane_to_serdes_map_nif_lane85": "rx85:tx85", - "lane_to_serdes_map_nif_lane86": "rx86:tx86", - "lane_to_serdes_map_nif_lane87": "rx87:tx87", - "lane_to_serdes_map_nif_lane88": "rx88:tx88", - "lane_to_serdes_map_nif_lane89": "rx89:tx89", - "lane_to_serdes_map_nif_lane90": "rx90:tx90", - "lane_to_serdes_map_nif_lane91": "rx91:tx91", - "lane_to_serdes_map_nif_lane92": "rx92:tx92", - "lane_to_serdes_map_nif_lane93": "rx93:tx93", - "lane_to_serdes_map_nif_lane94": "rx94:tx94", - "lane_to_serdes_map_nif_lane95": "rx95:tx95", - "lane_to_serdes_map_nif_lane96": "rx96:tx96", - "lane_to_serdes_map_nif_lane97": "rx97:tx97", - "lane_to_serdes_map_nif_lane98": "rx98:tx98", - "lane_to_serdes_map_nif_lane99": "rx99:tx99", - "lane_to_serdes_map_nif_lane100": "rx100:tx100", - "lane_to_serdes_map_nif_lane101": "rx101:tx101", - "lane_to_serdes_map_nif_lane102": "rx102:tx102", - "lane_to_serdes_map_nif_lane103": "rx103:tx103", - "lane_to_serdes_map_nif_lane104": "rx104:tx104", - "lane_to_serdes_map_nif_lane105": "rx105:tx105", - "lane_to_serdes_map_nif_lane106": "rx106:tx106", - "lane_to_serdes_map_nif_lane107": "rx107:tx107", - "lane_to_serdes_map_nif_lane108": "rx108:tx108", - "lane_to_serdes_map_nif_lane109": "rx109:tx109", - "lane_to_serdes_map_nif_lane110": "rx110:tx110", - "lane_to_serdes_map_nif_lane111": "rx111:tx111", - "lane_to_serdes_map_nif_lane112": "rx112:tx112", - "lane_to_serdes_map_nif_lane113": "rx113:tx113", - "lane_to_serdes_map_nif_lane114": "rx114:tx114", - "lane_to_serdes_map_nif_lane115": "rx115:tx115", - "lane_to_serdes_map_nif_lane116": "rx116:tx116", - "lane_to_serdes_map_nif_lane117": "rx117:tx117", - "lane_to_serdes_map_nif_lane118": "rx118:tx118", - "lane_to_serdes_map_nif_lane119": "rx119:tx119", - "lane_to_serdes_map_nif_lane120": "rx120:tx120", - "lane_to_serdes_map_nif_lane121": "rx121:tx121", - "lane_to_serdes_map_nif_lane122": "rx122:tx122", - "lane_to_serdes_map_nif_lane123": "rx123:tx123", - "lane_to_serdes_map_nif_lane124": "rx124:tx124", - "lane_to_serdes_map_nif_lane125": "rx125:tx125", - "lane_to_serdes_map_nif_lane126": "rx126:tx126", - "lane_to_serdes_map_nif_lane127": "rx127:tx127", - "lane_to_serdes_map_nif_lane128": "rx128:tx128", - "lane_to_serdes_map_nif_lane129": "rx129:tx129", - "lane_to_serdes_map_nif_lane130": "rx130:tx130", - "lane_to_serdes_map_nif_lane131": "rx131:tx131", - "lane_to_serdes_map_nif_lane132": "rx132:tx132", - "lane_to_serdes_map_nif_lane133": "rx133:tx133", - "lane_to_serdes_map_nif_lane134": "rx134:tx134", - "lane_to_serdes_map_nif_lane135": "rx135:tx135", - "lane_to_serdes_map_nif_lane136": "rx136:tx136", - "lane_to_serdes_map_nif_lane137": "rx137:tx137", - "lane_to_serdes_map_nif_lane138": "rx138:tx138", - "lane_to_serdes_map_nif_lane139": "rx139:tx139", - "lane_to_serdes_map_nif_lane140": "rx140:tx140", - "lane_to_serdes_map_nif_lane141": "rx141:tx141", - "lane_to_serdes_map_nif_lane142": "rx142:tx142", - "lane_to_serdes_map_nif_lane143": "rx143:tx143", - "lane_to_serdes_map_nif_lane144": "rx144:tx144", - "lane_to_serdes_map_nif_lane145": "rx145:tx145", - "lane_to_serdes_map_nif_lane146": "rx146:tx146", - "lane_to_serdes_map_nif_lane147": "rx147:tx147", - "lane_to_serdes_map_nif_lane148": "rx148:tx148", - "lane_to_serdes_map_nif_lane149": "rx149:tx149", - "lane_to_serdes_map_nif_lane150": "rx150:tx150", - "lane_to_serdes_map_nif_lane151": "rx151:tx151", - "lane_to_serdes_map_nif_lane152": "rx152:tx152", - "lane_to_serdes_map_nif_lane153": "rx153:tx153", - "lane_to_serdes_map_nif_lane154": "rx154:tx154", - "lane_to_serdes_map_nif_lane155": "rx155:tx155", - "lane_to_serdes_map_nif_lane156": "rx156:tx156", - "lane_to_serdes_map_nif_lane157": "rx157:tx157", - "lane_to_serdes_map_nif_lane158": "rx158:tx158", - "lane_to_serdes_map_nif_lane159": "rx159:tx159", - "lane_to_serdes_map_nif_lane160": "rx160:tx160", - "lane_to_serdes_map_nif_lane161": "rx161:tx161", - "lane_to_serdes_map_nif_lane162": "rx162:tx162", - "lane_to_serdes_map_nif_lane163": "rx163:tx163", - "lane_to_serdes_map_nif_lane164": "rx164:tx164", - "lane_to_serdes_map_nif_lane165": "rx165:tx165", - "lane_to_serdes_map_nif_lane166": "rx166:tx166", - "lane_to_serdes_map_nif_lane167": "rx167:tx167", - "lane_to_serdes_map_nif_lane168": "rx168:tx168", - "lane_to_serdes_map_nif_lane169": "rx169:tx169", - "lane_to_serdes_map_nif_lane170": "rx170:tx170", - "lane_to_serdes_map_nif_lane171": "rx171:tx171", - "lane_to_serdes_map_nif_lane172": "rx172:tx172", - "lane_to_serdes_map_nif_lane173": "rx173:tx173", - "lane_to_serdes_map_nif_lane174": "rx174:tx174", - "lane_to_serdes_map_nif_lane175": "rx175:tx175", - "lane_to_serdes_map_nif_lane176": "rx176:tx176", - "lane_to_serdes_map_nif_lane177": "rx177:tx177", - "lane_to_serdes_map_nif_lane178": "rx178:tx178", - "lane_to_serdes_map_nif_lane179": "rx179:tx179", - "lane_to_serdes_map_nif_lane180": "rx180:tx180", - "lane_to_serdes_map_nif_lane181": "rx181:tx181", - "lane_to_serdes_map_nif_lane182": "rx182:tx182", - "lane_to_serdes_map_nif_lane183": "rx183:tx183", - "lane_to_serdes_map_nif_lane184": "rx184:tx184", - "lane_to_serdes_map_nif_lane185": "rx185:tx185", - "lane_to_serdes_map_nif_lane186": "rx186:tx186", - "lane_to_serdes_map_nif_lane187": "rx187:tx187", - "lane_to_serdes_map_nif_lane188": "rx188:tx188", - "lane_to_serdes_map_nif_lane189": "rx189:tx189", - "lane_to_serdes_map_nif_lane190": "rx190:tx190", - "lane_to_serdes_map_nif_lane191": "rx191:tx191", - "lane_to_serdes_map_nif_lane192": "rx192:tx192", - "lane_to_serdes_map_nif_lane193": "rx193:tx193", - "lane_to_serdes_map_nif_lane194": "rx194:tx194", - "lane_to_serdes_map_nif_lane195": "rx195:tx195", - "lane_to_serdes_map_nif_lane196": "rx196:tx196", - "lane_to_serdes_map_nif_lane197": "rx197:tx197", - "lane_to_serdes_map_nif_lane198": "rx198:tx198", - "lane_to_serdes_map_nif_lane199": "rx199:tx199", - "lane_to_serdes_map_nif_lane200": "rx200:tx200", - "lane_to_serdes_map_nif_lane201": "rx201:tx201", - "lane_to_serdes_map_nif_lane202": "rx202:tx202", - "lane_to_serdes_map_nif_lane203": "rx203:tx203", - "lane_to_serdes_map_nif_lane204": "rx204:tx204", - "lane_to_serdes_map_nif_lane205": "rx205:tx205", - "lane_to_serdes_map_nif_lane206": "rx206:tx206", - "lane_to_serdes_map_nif_lane207": "rx207:tx207", - "lane_to_serdes_map_nif_lane208": "rx208:tx208", - "lane_to_serdes_map_nif_lane209": "rx209:tx209", - "lane_to_serdes_map_nif_lane210": "rx210:tx210", - "lane_to_serdes_map_nif_lane211": "rx211:tx211", - "lane_to_serdes_map_nif_lane212": "rx212:tx212", - "lane_to_serdes_map_nif_lane213": "rx213:tx213", - "lane_to_serdes_map_nif_lane214": "rx214:tx214", - "lane_to_serdes_map_nif_lane215": "rx215:tx215", - "lane_to_serdes_map_nif_lane216": "rx216:tx216", - "lane_to_serdes_map_nif_lane217": "rx217:tx217", - "lane_to_serdes_map_nif_lane218": "rx218:tx218", - "lane_to_serdes_map_nif_lane219": "rx219:tx219", - "lane_to_serdes_map_nif_lane220": "rx220:tx220", - "lane_to_serdes_map_nif_lane221": "rx221:tx221", - "lane_to_serdes_map_nif_lane222": "rx222:tx222", - "lane_to_serdes_map_nif_lane223": "rx223:tx223", - "lane_to_serdes_map_nif_lane224": "rx224:tx224", - "lane_to_serdes_map_nif_lane225": "rx225:tx225", - "lane_to_serdes_map_nif_lane226": "rx226:tx226", - "lane_to_serdes_map_nif_lane227": "rx227:tx227", - "lane_to_serdes_map_nif_lane228": "rx228:tx228", - "lane_to_serdes_map_nif_lane229": "rx229:tx229", - "lane_to_serdes_map_nif_lane230": "rx230:tx230", - "lane_to_serdes_map_nif_lane231": "rx231:tx231", - "lane_to_serdes_map_nif_lane232": "rx232:tx232", - "lane_to_serdes_map_nif_lane233": "rx233:tx233", - "lane_to_serdes_map_nif_lane234": "rx234:tx234", - "lane_to_serdes_map_nif_lane235": "rx235:tx235", - "lane_to_serdes_map_nif_lane236": "rx236:tx236", - "lane_to_serdes_map_nif_lane237": "rx237:tx237", - "lane_to_serdes_map_nif_lane238": "rx238:tx238", - "lane_to_serdes_map_nif_lane239": "rx239:tx239", - "lane_to_serdes_map_nif_lane240": "rx240:tx240", - "lane_to_serdes_map_nif_lane241": "rx241:tx241", - "lane_to_serdes_map_nif_lane242": "rx242:tx242", - "lane_to_serdes_map_nif_lane243": "rx243:tx243", - "lane_to_serdes_map_nif_lane244": "rx244:tx244", - "lane_to_serdes_map_nif_lane245": "rx245:tx245", - "lane_to_serdes_map_nif_lane246": "rx246:tx246", - "lane_to_serdes_map_nif_lane247": "rx247:tx247", - "lane_to_serdes_map_nif_lane248": "rx248:tx248", - "lane_to_serdes_map_nif_lane249": "rx249:tx249", - "lane_to_serdes_map_nif_lane250": "rx250:tx250", - "lane_to_serdes_map_nif_lane251": "rx251:tx251", - "lane_to_serdes_map_nif_lane252": "rx252:tx252", - "lane_to_serdes_map_nif_lane253": "rx253:tx253", - "lane_to_serdes_map_nif_lane254": "rx254:tx254", - "lane_to_serdes_map_nif_lane255": "rx255:tx255", - "lane_to_serdes_map_nif_lane256": "rx256:tx256", - "lane_to_serdes_map_nif_lane257": "rx257:tx257", - "lane_to_serdes_map_nif_lane258": "rx258:tx258", - "lane_to_serdes_map_nif_lane259": "rx259:tx259", - "lane_to_serdes_map_nif_lane260": "rx260:tx260", - "lane_to_serdes_map_nif_lane261": "rx261:tx261", - "lane_to_serdes_map_nif_lane262": "rx262:tx262", - "lane_to_serdes_map_nif_lane263": "rx263:tx263", - "lane_to_serdes_map_nif_lane264": "rx264:tx264", - "lane_to_serdes_map_nif_lane265": "rx265:tx265", - "lane_to_serdes_map_nif_lane266": "rx266:tx266", - "lane_to_serdes_map_nif_lane267": "rx267:tx267", - "lane_to_serdes_map_nif_lane268": "rx268:tx268", - "lane_to_serdes_map_nif_lane269": "rx269:tx269", - "lane_to_serdes_map_nif_lane270": "rx270:tx270", - "lane_to_serdes_map_nif_lane271": "rx271:tx271", - "lane_to_serdes_map_nif_lane272": "rx272:tx272", - "lane_to_serdes_map_nif_lane273": "rx273:tx273", - "lane_to_serdes_map_nif_lane274": "rx274:tx274", - "lane_to_serdes_map_nif_lane275": "rx275:tx275", - "lane_to_serdes_map_nif_lane276": "rx276:tx276", - "lane_to_serdes_map_nif_lane277": "rx277:tx277", - "lane_to_serdes_map_nif_lane278": "rx278:tx278", - "lane_to_serdes_map_nif_lane279": "rx279:tx279", - "lane_to_serdes_map_nif_lane280": "rx280:tx280", - "lane_to_serdes_map_nif_lane281": "rx281:tx281", - "lane_to_serdes_map_nif_lane282": "rx282:tx282", - "lane_to_serdes_map_nif_lane283": "rx283:tx283", - "lane_to_serdes_map_nif_lane284": "rx284:tx284", - "lane_to_serdes_map_nif_lane285": "rx285:tx285", - "lane_to_serdes_map_nif_lane286": "rx286:tx286", - "lane_to_serdes_map_nif_lane287": "rx287:tx287", - "lane_to_serdes_map_nif_lane288": "rx288:tx288", - "lane_to_serdes_map_nif_lane289": "rx289:tx289", - "lane_to_serdes_map_nif_lane290": "rx290:tx290", - "lane_to_serdes_map_nif_lane291": "rx291:tx291", - "lane_to_serdes_map_nif_lane292": "rx292:tx292", - "lane_to_serdes_map_nif_lane293": "rx293:tx293", - "lane_to_serdes_map_nif_lane294": "rx294:tx294", - "lane_to_serdes_map_nif_lane295": "rx295:tx295", - "lane_to_serdes_map_nif_lane296": "rx296:tx296", - "lane_to_serdes_map_nif_lane297": "rx297:tx297", - "lane_to_serdes_map_nif_lane298": "rx298:tx298", - "lane_to_serdes_map_nif_lane299": "rx299:tx299", - "lane_to_serdes_map_nif_lane300": "rx300:tx300", - "lane_to_serdes_map_nif_lane301": "rx301:tx301", - "lane_to_serdes_map_nif_lane302": "rx302:tx302", - "lane_to_serdes_map_nif_lane303": "rx303:tx303", - "lane_to_serdes_map_nif_lane304": "rx304:tx304", - "lane_to_serdes_map_nif_lane305": "rx305:tx305", - "lane_to_serdes_map_nif_lane306": "rx306:tx306", - "lane_to_serdes_map_nif_lane307": "rx307:tx307", - "lane_to_serdes_map_nif_lane308": "rx308:tx308", - "lane_to_serdes_map_nif_lane309": "rx309:tx309", - "lane_to_serdes_map_nif_lane310": "rx310:tx310", - "lane_to_serdes_map_nif_lane311": "rx311:tx311", - "lane_to_serdes_map_nif_lane312": "rx312:tx312", - "lane_to_serdes_map_nif_lane313": "rx313:tx313", - "lane_to_serdes_map_nif_lane314": "rx314:tx314", - "lane_to_serdes_map_nif_lane315": "rx315:tx315", - "lane_to_serdes_map_nif_lane316": "rx316:tx316", - "lane_to_serdes_map_nif_lane317": "rx317:tx317", - "lane_to_serdes_map_nif_lane318": "rx318:tx318", - "lane_to_serdes_map_nif_lane319": "rx319:tx319", - "lane_to_serdes_map_nif_lane320": "rx320:tx320", - "lane_to_serdes_map_nif_lane321": "rx321:tx321", - "lane_to_serdes_map_nif_lane322": "rx322:tx322", - "lane_to_serdes_map_nif_lane323": "rx323:tx323", - "lane_to_serdes_map_nif_lane324": "rx324:tx324", - "lane_to_serdes_map_nif_lane325": "rx325:tx325", - "lane_to_serdes_map_nif_lane326": "rx326:tx326", - "lane_to_serdes_map_nif_lane327": "rx327:tx327", - "lane_to_serdes_map_nif_lane328": "rx328:tx328", - "lane_to_serdes_map_nif_lane329": "rx329:tx329", - "lane_to_serdes_map_nif_lane330": "rx330:tx330", - "lane_to_serdes_map_nif_lane331": "rx331:tx331", - "lane_to_serdes_map_nif_lane332": "rx332:tx332", - "lane_to_serdes_map_nif_lane333": "rx333:tx333", - "lane_to_serdes_map_nif_lane334": "rx334:tx334", - "lane_to_serdes_map_nif_lane335": "rx335:tx335", - "lane_to_serdes_map_nif_lane336": "rx336:tx336", - "lane_to_serdes_map_nif_lane337": "rx337:tx337", - "lane_to_serdes_map_nif_lane338": "rx338:tx338", - "lane_to_serdes_map_nif_lane339": "rx339:tx339", - "lane_to_serdes_map_nif_lane340": "rx340:tx340", - "lane_to_serdes_map_nif_lane341": "rx341:tx341", - "lane_to_serdes_map_nif_lane342": "rx342:tx342", - "lane_to_serdes_map_nif_lane343": "rx343:tx343", - "lane_to_serdes_map_nif_lane344": "rx344:tx344", - "lane_to_serdes_map_nif_lane345": "rx345:tx345", - "lane_to_serdes_map_nif_lane346": "rx346:tx346", - "lane_to_serdes_map_nif_lane347": "rx347:tx347", - "lane_to_serdes_map_nif_lane348": "rx348:tx348", - "lane_to_serdes_map_nif_lane349": "rx349:tx349", - "lane_to_serdes_map_nif_lane350": "rx350:tx350", - "lane_to_serdes_map_nif_lane351": "rx351:tx351", - "lane_to_serdes_map_nif_lane352": "rx352:tx352", - "lane_to_serdes_map_nif_lane353": "rx353:tx353", - "lane_to_serdes_map_nif_lane354": "rx354:tx354", - "lane_to_serdes_map_nif_lane355": "rx355:tx355", - "lane_to_serdes_map_nif_lane356": "rx356:tx356", - "lane_to_serdes_map_nif_lane357": "rx357:tx357", - "lane_to_serdes_map_nif_lane358": "rx358:tx358", - "lane_to_serdes_map_nif_lane359": "rx359:tx359", - "lane_to_serdes_map_nif_lane360": "rx360:tx360", - "lane_to_serdes_map_nif_lane361": "rx361:tx361", - "lane_to_serdes_map_nif_lane362": "rx362:tx362", - "lane_to_serdes_map_nif_lane363": "rx363:tx363", - "lane_to_serdes_map_nif_lane364": "rx364:tx364", - "lane_to_serdes_map_nif_lane365": "rx365:tx365", - "lane_to_serdes_map_nif_lane366": "rx366:tx366", - "lane_to_serdes_map_nif_lane367": "rx367:tx367", - "lane_to_serdes_map_nif_lane368": "rx368:tx368", - "lane_to_serdes_map_nif_lane369": "rx369:tx369", - "lane_to_serdes_map_nif_lane370": "rx370:tx370", - "lane_to_serdes_map_nif_lane371": "rx371:tx371", - "lane_to_serdes_map_nif_lane372": "rx372:tx372", - "lane_to_serdes_map_nif_lane373": "rx373:tx373", - "lane_to_serdes_map_nif_lane374": "rx374:tx374", - "lane_to_serdes_map_nif_lane375": "rx375:tx375", - "lane_to_serdes_map_nif_lane376": "rx376:tx376", - "lane_to_serdes_map_nif_lane377": "rx377:tx377", - "lane_to_serdes_map_nif_lane378": "rx378:tx378", - "lane_to_serdes_map_nif_lane379": "rx379:tx379", - "lane_to_serdes_map_nif_lane380": "rx380:tx380", - "lane_to_serdes_map_nif_lane381": "rx381:tx381", - "lane_to_serdes_map_nif_lane382": "rx382:tx382", - "lane_to_serdes_map_nif_lane383": "rx383:tx383", - "lane_to_serdes_map_nif_lane384": "rx384:tx384", - "lane_to_serdes_map_nif_lane385": "rx385:tx385", - "lane_to_serdes_map_nif_lane386": "rx386:tx386", - "lane_to_serdes_map_nif_lane387": "rx387:tx387", - "lane_to_serdes_map_nif_lane388": "rx388:tx388", - "lane_to_serdes_map_nif_lane389": "rx389:tx389", - "lane_to_serdes_map_nif_lane390": "rx390:tx390", - "lane_to_serdes_map_nif_lane391": "rx391:tx391", - "lane_to_serdes_map_nif_lane392": "rx392:tx392", - "lane_to_serdes_map_nif_lane393": "rx393:tx393", - "lane_to_serdes_map_nif_lane394": "rx394:tx394", - "lane_to_serdes_map_nif_lane395": "rx395:tx395", - "lane_to_serdes_map_nif_lane396": "rx396:tx396", - "lane_to_serdes_map_nif_lane397": "rx397:tx397", - "lane_to_serdes_map_nif_lane398": "rx398:tx398", - "lane_to_serdes_map_nif_lane399": "rx399:tx399", - "lane_to_serdes_map_nif_lane400": "rx400:tx400", - "lane_to_serdes_map_nif_lane401": "rx401:tx401", - "lane_to_serdes_map_nif_lane402": "rx402:tx402", - "lane_to_serdes_map_nif_lane403": "rx403:tx403", - "lane_to_serdes_map_nif_lane404": "rx404:tx404", - "lane_to_serdes_map_nif_lane405": "rx405:tx405", - "lane_to_serdes_map_nif_lane406": "rx406:tx406", - "lane_to_serdes_map_nif_lane407": "rx407:tx407", - "lane_to_serdes_map_nif_lane408": "rx408:tx408", - "lane_to_serdes_map_nif_lane409": "rx409:tx409", - "lane_to_serdes_map_nif_lane410": "rx410:tx410", - "lane_to_serdes_map_nif_lane411": "rx411:tx411", - "lane_to_serdes_map_nif_lane412": "rx412:tx412", - "lane_to_serdes_map_nif_lane413": "rx413:tx413", - "lane_to_serdes_map_nif_lane414": "rx414:tx414", - "lane_to_serdes_map_nif_lane415": "rx415:tx415", - "lane_to_serdes_map_nif_lane416": "rx416:tx416", - "lane_to_serdes_map_nif_lane417": "rx417:tx417", - "lane_to_serdes_map_nif_lane418": "rx418:tx418", - "lane_to_serdes_map_nif_lane419": "rx419:tx419", - "lane_to_serdes_map_nif_lane420": "rx420:tx420", - "lane_to_serdes_map_nif_lane421": "rx421:tx421", - "lane_to_serdes_map_nif_lane422": "rx422:tx422", - "lane_to_serdes_map_nif_lane423": "rx423:tx423", - "lane_to_serdes_map_nif_lane424": "rx424:tx424", - "lane_to_serdes_map_nif_lane425": "rx425:tx425", - "lane_to_serdes_map_nif_lane426": "rx426:tx426", - "lane_to_serdes_map_nif_lane427": "rx427:tx427", - "lane_to_serdes_map_nif_lane428": "rx428:tx428", - "lane_to_serdes_map_nif_lane429": "rx429:tx429", - "lane_to_serdes_map_nif_lane430": "rx430:tx430", - "lane_to_serdes_map_nif_lane431": "rx431:tx431", - "lane_to_serdes_map_nif_lane432": "rx432:tx432", - "lane_to_serdes_map_nif_lane433": "rx433:tx433", - "lane_to_serdes_map_nif_lane434": "rx434:tx434", - "lane_to_serdes_map_nif_lane435": "rx435:tx435", - "lane_to_serdes_map_nif_lane436": "rx436:tx436", - "lane_to_serdes_map_nif_lane437": "rx437:tx437", - "lane_to_serdes_map_nif_lane438": "rx438:tx438", - "lane_to_serdes_map_nif_lane439": "rx439:tx439", - "lane_to_serdes_map_nif_lane440": "rx440:tx440", - "lane_to_serdes_map_nif_lane441": "rx441:tx441", - "lane_to_serdes_map_nif_lane442": "rx442:tx442", - "lane_to_serdes_map_nif_lane443": "rx443:tx443", - "lane_to_serdes_map_nif_lane444": "rx444:tx444", - "lane_to_serdes_map_nif_lane445": "rx445:tx445", - "lane_to_serdes_map_nif_lane446": "rx446:tx446", - "lane_to_serdes_map_nif_lane447": "rx447:tx447", - "lane_to_serdes_map_nif_lane448": "rx448:tx448", - "lane_to_serdes_map_nif_lane449": "rx449:tx449", - "lane_to_serdes_map_nif_lane450": "rx450:tx450", - "lane_to_serdes_map_nif_lane451": "rx451:tx451", - "lane_to_serdes_map_nif_lane452": "rx452:tx452", - "lane_to_serdes_map_nif_lane453": "rx453:tx453", - "lane_to_serdes_map_nif_lane454": "rx454:tx454", - "lane_to_serdes_map_nif_lane455": "rx455:tx455", - "lane_to_serdes_map_nif_lane456": "rx456:tx456", - "lane_to_serdes_map_nif_lane457": "rx457:tx457", - "lane_to_serdes_map_nif_lane458": "rx458:tx458", - "lane_to_serdes_map_nif_lane459": "rx459:tx459", - "lane_to_serdes_map_nif_lane460": "rx460:tx460", - "lane_to_serdes_map_nif_lane461": "rx461:tx461", - "lane_to_serdes_map_nif_lane462": "rx462:tx462", - "lane_to_serdes_map_nif_lane463": "rx463:tx463", - "lane_to_serdes_map_nif_lane464": "rx464:tx464", - "lane_to_serdes_map_nif_lane465": "rx465:tx465", - "lane_to_serdes_map_nif_lane466": "rx466:tx466", - "lane_to_serdes_map_nif_lane467": "rx467:tx467", - "lane_to_serdes_map_nif_lane468": "rx468:tx468", - "lane_to_serdes_map_nif_lane469": "rx469:tx469", - "lane_to_serdes_map_nif_lane470": "rx470:tx470", - "lane_to_serdes_map_nif_lane471": "rx471:tx471", - "lane_to_serdes_map_nif_lane472": "rx472:tx472", - "lane_to_serdes_map_nif_lane473": "rx473:tx473", - "lane_to_serdes_map_nif_lane474": "rx474:tx474", - "lane_to_serdes_map_nif_lane475": "rx475:tx475", - "lane_to_serdes_map_nif_lane476": "rx476:tx476", - "lane_to_serdes_map_nif_lane477": "rx477:tx477", - "lane_to_serdes_map_nif_lane478": "rx478:tx478", - "lane_to_serdes_map_nif_lane479": "rx479:tx479", - "lane_to_serdes_map_nif_lane480": "rx480:tx480", - "lane_to_serdes_map_nif_lane481": "rx481:tx481", - "lane_to_serdes_map_nif_lane482": "rx482:tx482", - "lane_to_serdes_map_nif_lane483": "rx483:tx483", - "lane_to_serdes_map_nif_lane484": "rx484:tx484", - "lane_to_serdes_map_nif_lane485": "rx485:tx485", - "lane_to_serdes_map_nif_lane486": "rx486:tx486", - "lane_to_serdes_map_nif_lane487": "rx487:tx487", - "lane_to_serdes_map_nif_lane488": "rx488:tx488", - "lane_to_serdes_map_nif_lane489": "rx489:tx489", - "lane_to_serdes_map_nif_lane490": "rx490:tx490", - "lane_to_serdes_map_nif_lane491": "rx491:tx491", - "lane_to_serdes_map_nif_lane492": "rx492:tx492", - "lane_to_serdes_map_nif_lane493": "rx493:tx493", - "lane_to_serdes_map_nif_lane494": "rx494:tx494", - "lane_to_serdes_map_nif_lane495": "rx495:tx495", - "lane_to_serdes_map_nif_lane496": "rx496:tx496", - "lane_to_serdes_map_nif_lane497": "rx497:tx497", - "lane_to_serdes_map_nif_lane498": "rx498:tx498", - "lane_to_serdes_map_nif_lane499": "rx499:tx499", - "lane_to_serdes_map_nif_lane500": "rx500:tx500", - "lane_to_serdes_map_nif_lane501": "rx501:tx501", - "lane_to_serdes_map_nif_lane502": "rx502:tx502", - "lane_to_serdes_map_nif_lane503": "rx503:tx503", - "lane_to_serdes_map_nif_lane504": "rx504:tx504", - "lane_to_serdes_map_nif_lane505": "rx505:tx505", - "lane_to_serdes_map_nif_lane506": "rx506:tx506", - "lane_to_serdes_map_nif_lane507": "rx507:tx507", - "lane_to_serdes_map_nif_lane508": "rx508:tx508", - "lane_to_serdes_map_nif_lane509": "rx509:tx509", - "lane_to_serdes_map_nif_lane510": "rx510:tx510", - "lane_to_serdes_map_nif_lane511": "rx511:tx511", - "warmboot_support.BCM994EX": "on", - "warmboot_support.BCM994EX_ADAPTER": "on" + "dpp_db_path": "/root/brcmsim/tools/sand/db" } } } From d4810838b339a9dc493006660609a58a0e123a5e Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Thu, 19 Feb 2026 21:36:49 -0800 Subject: [PATCH 15/16] Add JSON to J4SimPlatformMapping.cpp so it gets loaded when we run cModel testing, also added j4sim mode to the hw_test_config --- .../common/j4sim/J4SimPlatformMapping.cpp | 5500 ++++++++++++++++- .../j4sim.agent.materialized_JSON | 1 + 2 files changed, 5500 insertions(+), 1 deletion(-) diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp index dc89e27fd9bbc..788edd560d967 100644 --- a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -11,8 +11,5506 @@ #include "fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.h" namespace facebook::fboss { +namespace { +constexpr auto kJsonPlatformMappingStr = R"( +{ + "ports": { + "1": { + "mapping": { + "id": 1, + "name": "eth1/1/1", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + ] + } + }, + "39": { + "subsumedPorts": [ + 2, + 3, + 4, + 5, + 6, + 7, + 8 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 7 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 0 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 0 + } + } + ] + } + } + } + }, + "2": { + "mapping": { + "id": 2, + "name": "eth1/1/2", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 1 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 1 + } + } + ] + } + } + } + }, + "3": { + "mapping": { + "id": 3, + "name": "eth1/1/3", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 2 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 2 + } + } + ] + } + } + } + }, + "4": { + "mapping": { + "id": 4, + "name": "eth1/1/4", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 3 + } + } + ] + } + } + } + }, + "5": { + "mapping": { + "id": 5, + "name": "eth1/1/5", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 4 + } + } + ] + } + } + } + }, + "6": { + "mapping": { + "id": 6, + "name": "eth1/1/6", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 5 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 5 + } + } + ] + } + } + } + }, + "7": { + "mapping": { + "id": 7, + "name": "eth1/1/7", + "controllingPort": 1, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip1", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core0", + "lane": 6 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+ "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 0 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 0 + } + } + ] + } + } + } + }, + "50": { + "mapping": { + "id": 50, + "name": "eth1/7/2", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 1 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 1 + } + } + ] + } + } + } + }, + "51": { + "mapping": { + "id": 51, + "name": "eth1/7/3", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 2 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 2 + } + } + ] + } + } + } + }, + "52": { + "mapping": { + "id": 52, + "name": "eth1/7/4", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 3 + } + } + ] + } + } + } + }, + "53": { + "mapping": { + "id": 53, + "name": "eth1/7/5", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 4 + } + } + ] + } + } + } + }, + "54": { + "mapping": { + "id": 54, + "name": "eth1/7/6", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 5 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 5 + } + } + ] + } + } + } + }, + "55": { + "mapping": { + "id": 55, + "name": "eth1/7/7", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 6 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 6 + } + } + ] + } + } + } + }, + "56": { + "mapping": { + "id": 56, + "name": "eth1/7/8", + "controllingPort": 49, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core6", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip7", + "lane": 7 + } + } + ] + } + } + } + }, + "57": { + "mapping": { + "id": 57, + "name": "eth1/8/1", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + }, + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "50": { + "subsumedPorts": [ + 58, + 59, + 60, + 61, + 62, + 63, + 64 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + }, + "39": { + "subsumedPorts": [ + 58, + 59, + 60, + 61, + 62, + 63, + 64 + ], + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + }, + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + }, + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + }, + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 0 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 0 + } + } + ] + } + } + } + }, + "58": { + "mapping": { + "id": 58, + "name": "eth1/8/2", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 1 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 1 + } + } + ] + } + } + } + }, + "59": { + "mapping": { + "id": 59, + "name": "eth1/8/3", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 2 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 2 + } + } + ] + } + } + } + }, + "60": { + "mapping": { + "id": 60, + "name": "eth1/8/4", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 3 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 3 + } + } + ] + } + } + } + }, + "61": { + "mapping": { + "id": 61, + "name": "eth1/8/5", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 4 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 4 + } + } + ] + } + } + } + }, + "62": { + "mapping": { + "id": 62, + "name": "eth1/8/6", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 5 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 5 + } + } + ] + } + } + } + }, + "63": { + "mapping": { + "id": 63, + "name": "eth1/8/7", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 6 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 6 + } + } + ] + } + } + } + }, + "64": { + "mapping": { + "id": 64, + "name": "eth1/8/8", + "controllingPort": 57, + "pins": [ + { + "a": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + }, + "z": { + "end": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + } + ], + "portType": 0, + "scope": 0 + }, + "supportedProfiles": { + "49": { + "pins": { + "iphy": [ + { + "id": { + "chip": "NPU-J4SIM_NIF-slot1/chip1/core7", + "lane": 7 + } + } + ], + "transceiver": [ + { + "id": { + "chip": "TRANSCEIVER-OSFP-slot1/chip8", + "lane": 7 + } + } + ] + } + } + } + } + }, + "chips": [ + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core0", + "type": 1, + "physicalID": 0 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core1", + "type": 1, + "physicalID": 1 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core2", + "type": 1, + "physicalID": 2 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core3", + "type": 1, + "physicalID": 3 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core4", + "type": 1, + "physicalID": 4 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core5", + "type": 1, + "physicalID": 5 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core6", + "type": 1, + "physicalID": 6 + }, + { + "name": "NPU-J4SIM_NIF-slot1/chip1/core7", + "type": 1, + "physicalID": 7 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip1", + "type": 3, + "physicalID": 0 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip2", + "type": 3, + "physicalID": 1 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip3", + "type": 3, + "physicalID": 2 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip4", + "type": 3, + "physicalID": 3 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip5", + "type": 3, + "physicalID": 4 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip6", + "type": 3, + "physicalID": 5 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip7", + "type": 3, + "physicalID": 6 + }, + { + "name": "TRANSCEIVER-OSFP-slot1/chip8", + "type": 3, + "physicalID": 7 + } + ], + "platformSupportedProfiles": [ + { + "factor": { + "profileID": 49 + }, + "profile": { + "speed": 100000, + "iphy": { + "numLanes": 1, + "modulation": 2, + "fec": 1, + "medium": 1, + "interfaceType": 10 + } + } + }, + { + "factor": { + "profileID": 50 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 1, + "interfaceType": 13 + } + } + }, + { + "factor": { + "profileID": 39 + }, + "profile": { + "speed": 800000, + "iphy": { + "numLanes": 8, + "modulation": 2, + "fec": 11, + "medium": 2, + "interfaceType": 23 + } + } + } + ] +} +)"; +} // namespace -J4SimPlatformMapping::J4SimPlatformMapping() : PlatformMapping() {} +J4SimPlatformMapping::J4SimPlatformMapping() + : PlatformMapping(kJsonPlatformMappingStr) {} J4SimPlatformMapping::J4SimPlatformMapping( const std::string& platformMappingStr) diff --git a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON index fa992d0ddbf4f..dc5ddd3158d78 100644 --- a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON +++ b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON @@ -6,6 +6,7 @@ "enable_acl_table_group": "true", "intf_nbr_tables": "true", "log_variable_name": "true", + "mode": "j4sim", "sai_configure_six_tap": "true", "set_classid_for_my_subnet_and_ip_routes": "true", "skip_transceiver_programming": "true", From 63b926de496d311b46c5b74bb754983edc2d049c Mon Sep 17 00:00:00 2001 From: Justin Liu Date: Tue, 24 Feb 2026 10:09:26 -0800 Subject: [PATCH 16/16] Get past existing failures, hitting some brcm_sai_dnx_crps_database_create failure now --- .../common/j4sim/J4SimPlatformMapping.cpp | 6 +- fboss/agent/platforms/sai/SaiPlatform.cpp | 4 + .../j4sim.agent.materialized_JSON | 158 +++++++++++++++++- 3 files changed, 163 insertions(+), 5 deletions(-) diff --git a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp index 788edd560d967..5dd4210e3dfdb 100644 --- a/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp +++ b/fboss/agent/platforms/common/j4sim/J4SimPlatformMapping.cpp @@ -5522,9 +5522,9 @@ J4SimPlatformMapping::getCpuPortsCoreAndPortIdx() const { kSingleStageCpuPortsCoreAndPortIdx = { // {CPU System Port, {Core ID, Port ID/PP_DSP}} {0, {0, 0}}, - {1, {1, 0}}, - {2, {2, 0}}, - {3, {3, 0}}, + {1, {1, 200}}, + {2, {2, 202}}, + {3, {3, 203}}, }; return kSingleStageCpuPortsCoreAndPortIdx; } diff --git a/fboss/agent/platforms/sai/SaiPlatform.cpp b/fboss/agent/platforms/sai/SaiPlatform.cpp index b4f930f4a423e..3135624996b11 100644 --- a/fboss/agent/platforms/sai/SaiPlatform.cpp +++ b/fboss/agent/platforms/sai/SaiPlatform.cpp @@ -923,6 +923,10 @@ SaiSwitchTraits::CreateAttributes SaiPlatform::getSwitchAttributes( maxSystemPorts = 1024; maxVoqs = 8 * 1024; maxSystemPortId = 1024 - 1; + maxSwitchId = 2048; +#if defined(BRCM_SAI_SDK_XGS_AND_DNX) + localSystemPortIdRangeList = std::vector{{0, 53}}; +#endif return { initSwitch, diff --git a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON index dc5ddd3158d78..8ee601067c320 100644 --- a/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON +++ b/fboss/oss/hw_test_configs/j4sim.agent.materialized_JSON @@ -191,9 +191,15 @@ "asicConfig": { "common": { "config": { + "programmability_image_name.BCM9941X": "AI23", + "programmability_ucode_relative_path.BCM9941X": "pemla/ucode/AI23/jr3native/u_code_db2pem.txt", + "custom_feature_programmability_standard_image_name.BCM9941X": "AI23", "appl_param_rcy_mirror_ports_range.BCM9941X": "100-139", "custom_feature_stop_on_access_init_error.BCM9941X": "0", - "port_priorities_cpu.BCM9941X": "1", + "port_priorities": "8", + "port_priorities_cpu.BCM9941X": "2", + "port_priorities_rcy": "2", + "port_priorities_sch.BCM9941X": "8", "ucode_port_0.BCM9941X": "CPU.0:core_0.0", "ucode_port_200.BCM9941X": "CPU.8:core_1.200", "ucode_port_201.BCM9941X": "CPU.16:core_0.201", @@ -361,7 +367,155 @@ "sai_trigger_linkscan_remote_local_faults": "1", "sai_uncached_port_stats": "0x1", "sai_voq_wm_latency_enable": "1", - "dpp_db_path": "/root/brcmsim/tools/sand/db" + "dpp_db_path": "/root/brcmsim/tools/sand/db", + "lane_to_serdes_map_nif_lane0.BCM9941X": "rx0:tx0", + "lane_to_serdes_map_nif_lane1.BCM9941X": "rx1:tx1", + "lane_to_serdes_map_nif_lane2.BCM9941X": "rx2:tx2", + "lane_to_serdes_map_nif_lane3.BCM9941X": "rx3:tx3", + "lane_to_serdes_map_nif_lane4.BCM9941X": "rx4:tx4", + "lane_to_serdes_map_nif_lane5.BCM9941X": "rx5:tx5", + "lane_to_serdes_map_nif_lane6.BCM9941X": "rx6:tx6", + "lane_to_serdes_map_nif_lane7.BCM9941X": "rx7:tx7", + "lane_to_serdes_map_nif_lane8.BCM9941X": "rx8:tx8", + "lane_to_serdes_map_nif_lane9.BCM9941X": "rx9:tx9", + "lane_to_serdes_map_nif_lane10.BCM9941X": "rx10:tx10", + "lane_to_serdes_map_nif_lane11.BCM9941X": "rx11:tx11", + "lane_to_serdes_map_nif_lane12.BCM9941X": "rx12:tx12", + "lane_to_serdes_map_nif_lane13.BCM9941X": "rx13:tx13", + "lane_to_serdes_map_nif_lane14.BCM9941X": "rx14:tx14", + "lane_to_serdes_map_nif_lane15.BCM9941X": "rx15:tx15", + "lane_to_serdes_map_nif_lane16.BCM9941X": "rx16:tx16", + "lane_to_serdes_map_nif_lane17.BCM9941X": "rx17:tx17", + "lane_to_serdes_map_nif_lane18.BCM9941X": "rx18:tx18", + "lane_to_serdes_map_nif_lane19.BCM9941X": "rx19:tx19", + "lane_to_serdes_map_nif_lane20.BCM9941X": "rx20:tx20", + "lane_to_serdes_map_nif_lane21.BCM9941X": "rx21:tx21", + "lane_to_serdes_map_nif_lane22.BCM9941X": "rx22:tx22", + "lane_to_serdes_map_nif_lane23.BCM9941X": "rx23:tx23", + "lane_to_serdes_map_nif_lane24.BCM9941X": "rx24:tx24", + "lane_to_serdes_map_nif_lane25.BCM9941X": "rx25:tx25", + "lane_to_serdes_map_nif_lane26.BCM9941X": "rx26:tx26", + "lane_to_serdes_map_nif_lane27.BCM9941X": "rx27:tx27", + "lane_to_serdes_map_nif_lane28.BCM9941X": "rx28:tx28", + "lane_to_serdes_map_nif_lane29.BCM9941X": "rx29:tx29", + "lane_to_serdes_map_nif_lane30.BCM9941X": "rx30:tx30", + "lane_to_serdes_map_nif_lane31.BCM9941X": "rx31:tx31", + "lane_to_serdes_map_nif_lane32.BCM9941X": "rx32:tx32", + "lane_to_serdes_map_nif_lane33.BCM9941X": "rx33:tx33", + "lane_to_serdes_map_nif_lane34.BCM9941X": "rx34:tx34", + "lane_to_serdes_map_nif_lane35.BCM9941X": "rx35:tx35", + "lane_to_serdes_map_nif_lane36.BCM9941X": "rx36:tx36", + "lane_to_serdes_map_nif_lane37.BCM9941X": "rx37:tx37", + "lane_to_serdes_map_nif_lane38.BCM9941X": "rx38:tx38", + "lane_to_serdes_map_nif_lane39.BCM9941X": "rx39:tx39", + "lane_to_serdes_map_nif_lane40.BCM9941X": "rx40:tx40", + "lane_to_serdes_map_nif_lane41.BCM9941X": "rx41:tx41", + "lane_to_serdes_map_nif_lane42.BCM9941X": "rx42:tx42", + "lane_to_serdes_map_nif_lane43.BCM9941X": "rx43:tx43", + "lane_to_serdes_map_nif_lane44.BCM9941X": "rx44:tx44", + "lane_to_serdes_map_nif_lane45.BCM9941X": "rx45:tx45", + "lane_to_serdes_map_nif_lane46.BCM9941X": "rx46:tx46", + "lane_to_serdes_map_nif_lane47.BCM9941X": "rx47:tx47", + "lane_to_serdes_map_nif_lane48.BCM9941X": "rx48:tx48", + "lane_to_serdes_map_nif_lane49.BCM9941X": "rx49:tx49", + "lane_to_serdes_map_nif_lane50.BCM9941X": "rx50:tx50", + "lane_to_serdes_map_nif_lane51.BCM9941X": "rx51:tx51", + "lane_to_serdes_map_nif_lane52.BCM9941X": "rx52:tx52", + "lane_to_serdes_map_nif_lane53.BCM9941X": "rx53:tx53", + "lane_to_serdes_map_nif_lane54.BCM9941X": "rx54:tx54", + "lane_to_serdes_map_nif_lane55.BCM9941X": "rx55:tx55", + "lane_to_serdes_map_nif_lane56.BCM9941X": "rx56:tx56", + "lane_to_serdes_map_nif_lane57.BCM9941X": "rx57:tx57", + "lane_to_serdes_map_nif_lane58.BCM9941X": "rx58:tx58", + "lane_to_serdes_map_nif_lane59.BCM9941X": "rx59:tx59", + "lane_to_serdes_map_nif_lane60.BCM9941X": "rx60:tx60", + "lane_to_serdes_map_nif_lane61.BCM9941X": "rx61:tx61", + "lane_to_serdes_map_nif_lane62.BCM9941X": "rx62:tx62", + "lane_to_serdes_map_nif_lane63.BCM9941X": "rx63:tx63", + "lane_to_serdes_map_nif_lane64.BCM9941X": "rx64:tx64", + "lane_to_serdes_map_nif_lane65.BCM9941X": "rx65:tx65", + "lane_to_serdes_map_nif_lane66.BCM9941X": "rx66:tx66", + "lane_to_serdes_map_nif_lane67.BCM9941X": "rx67:tx67", + "lane_to_serdes_map_nif_lane68.BCM9941X": "rx68:tx68", + "lane_to_serdes_map_nif_lane69.BCM9941X": "rx69:tx69", + "lane_to_serdes_map_nif_lane70.BCM9941X": "rx70:tx70", + "lane_to_serdes_map_nif_lane71.BCM9941X": "rx71:tx71", + "lane_to_serdes_map_nif_lane72.BCM9941X": "rx72:tx72", + "lane_to_serdes_map_nif_lane73.BCM9941X": "rx73:tx73", + "lane_to_serdes_map_nif_lane74.BCM9941X": "rx74:tx74", + "lane_to_serdes_map_nif_lane75.BCM9941X": "rx75:tx75", + "lane_to_serdes_map_nif_lane76.BCM9941X": "rx76:tx76", + "lane_to_serdes_map_nif_lane77.BCM9941X": "rx77:tx77", + "lane_to_serdes_map_nif_lane78.BCM9941X": "rx78:tx78", + "lane_to_serdes_map_nif_lane79.BCM9941X": "rx79:tx79", + "lane_to_serdes_map_nif_lane80.BCM9941X": "rx80:tx80", + "lane_to_serdes_map_nif_lane81.BCM9941X": "rx81:tx81", + "lane_to_serdes_map_nif_lane82.BCM9941X": "rx82:tx82", + "lane_to_serdes_map_nif_lane83.BCM9941X": "rx83:tx83", + "lane_to_serdes_map_nif_lane84.BCM9941X": "rx84:tx84", + "lane_to_serdes_map_nif_lane85.BCM9941X": "rx85:tx85", + "lane_to_serdes_map_nif_lane86.BCM9941X": "rx86:tx86", + "lane_to_serdes_map_nif_lane87.BCM9941X": "rx87:tx87", + "lane_to_serdes_map_nif_lane88.BCM9941X": "rx88:tx88", + "lane_to_serdes_map_nif_lane89.BCM9941X": "rx89:tx89", + "lane_to_serdes_map_nif_lane90.BCM9941X": "rx90:tx90", + "lane_to_serdes_map_nif_lane91.BCM9941X": "rx91:tx91", + "lane_to_serdes_map_nif_lane92.BCM9941X": "rx92:tx92", + "lane_to_serdes_map_nif_lane93.BCM9941X": "rx93:tx93", + "lane_to_serdes_map_nif_lane94.BCM9941X": "rx94:tx94", + "lane_to_serdes_map_nif_lane95.BCM9941X": "rx95:tx95", + "lane_to_serdes_map_nif_lane96.BCM9941X": "rx96:tx96", + "lane_to_serdes_map_nif_lane97.BCM9941X": "rx97:tx97", + "lane_to_serdes_map_nif_lane98.BCM9941X": "rx98:tx98", + "lane_to_serdes_map_nif_lane99.BCM9941X": "rx99:tx99", + "lane_to_serdes_map_nif_lane100.BCM9941X": "rx100:tx100", + "lane_to_serdes_map_nif_lane101.BCM9941X": "rx101:tx101", + "lane_to_serdes_map_nif_lane102.BCM9941X": "rx102:tx102", + "lane_to_serdes_map_nif_lane103.BCM9941X": "rx103:tx103", + "lane_to_serdes_map_nif_lane104.BCM9941X": "rx104:tx104", + "lane_to_serdes_map_nif_lane105.BCM9941X": "rx105:tx105", + "lane_to_serdes_map_nif_lane106.BCM9941X": "rx106:tx106", + "lane_to_serdes_map_nif_lane107.BCM9941X": "rx107:tx107", + "lane_to_serdes_map_nif_lane108.BCM9941X": "rx108:tx108", + "lane_to_serdes_map_nif_lane109.BCM9941X": "rx109:tx109", + "lane_to_serdes_map_nif_lane110.BCM9941X": "rx110:tx110", + "lane_to_serdes_map_nif_lane111.BCM9941X": "rx111:tx111", + "lane_to_serdes_map_nif_lane112.BCM9941X": "rx112:tx112", + "lane_to_serdes_map_nif_lane113.BCM9941X": "rx113:tx113", + "lane_to_serdes_map_nif_lane114.BCM9941X": "rx114:tx114", + "lane_to_serdes_map_nif_lane115.BCM9941X": "rx115:tx115", + "lane_to_serdes_map_nif_lane116.BCM9941X": "rx116:tx116", + "lane_to_serdes_map_nif_lane117.BCM9941X": "rx117:tx117", + "lane_to_serdes_map_nif_lane118.BCM9941X": "rx118:tx118", + "lane_to_serdes_map_nif_lane119.BCM9941X": "rx119:tx119", + "lane_to_serdes_map_nif_lane120.BCM9941X": "rx120:tx120", + "lane_to_serdes_map_nif_lane121.BCM9941X": "rx121:tx121", + "lane_to_serdes_map_nif_lane122.BCM9941X": "rx122:tx122", + "lane_to_serdes_map_nif_lane123.BCM9941X": "rx123:tx123", + "lane_to_serdes_map_nif_lane124.BCM9941X": "rx124:tx124", + "lane_to_serdes_map_nif_lane125.BCM9941X": "rx125:tx125", + "lane_to_serdes_map_nif_lane126.BCM9941X": "rx126:tx126", + "lane_to_serdes_map_nif_lane127.BCM9941X": "rx127:tx127", + "lane_to_serdes_map_nif_lane128.BCM9941X": "rx128:tx128", + "lane_to_serdes_map_nif_lane129.BCM9941X": "rx129:tx129", + "lane_to_serdes_map_nif_lane130.BCM9941X": "rx130:tx130", + "lane_to_serdes_map_nif_lane131.BCM9941X": "rx131:tx131", + "lane_to_serdes_map_nif_lane132.BCM9941X": "rx132:tx132", + "lane_to_serdes_map_nif_lane133.BCM9941X": "rx133:tx133", + "lane_to_serdes_map_nif_lane134.BCM9941X": "rx134:tx134", + "lane_to_serdes_map_nif_lane135.BCM9941X": "rx135:tx135", + "lane_to_serdes_map_nif_lane136.BCM9941X": "rx136:tx136", + "lane_to_serdes_map_nif_lane137.BCM9941X": "rx137:tx137", + "lane_to_serdes_map_nif_lane138.BCM9941X": "rx138:tx138", + "lane_to_serdes_map_nif_lane139.BCM9941X": "rx139:tx139", + "lane_to_serdes_map_nif_lane140.BCM9941X": "rx140:tx140", + "lane_to_serdes_map_nif_lane141.BCM9941X": "rx141:tx141", + "lane_to_serdes_map_nif_lane142.BCM9941X": "rx142:tx142", + "lane_to_serdes_map_nif_lane143.BCM9941X": "rx143:tx143", + "lane_to_serdes_map_nif_lane144.BCM9941X": "rx144:tx144", + "lane_to_serdes_map_nif_lane145.BCM9941X": "rx145:tx145", + "lane_to_serdes_map_nif_lane146.BCM9941X": "rx146:tx146", + "lane_to_serdes_map_nif_lane147.BCM9941X": "rx147:tx147" } } }