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Commit 34e055f

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sagarksagark
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one clock gen with both sets of clocks that we frequently use (190, 175, 160), (90, 85, 75)
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11 files changed

+483
-228
lines changed

11 files changed

+483
-228
lines changed

‎hdk/cl/developer_designs/cl_firesim/design/cl_firesim.sv‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -96,9 +96,12 @@ always_ff @(negedge rst_main_n or posedge clk_extra_a1)
9696
// Output Output Phase Duty Cycle Pk-to-Pk Phase
9797
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
9898
//----------------------------------------------------------------------------
99-
// clk_out1___189.972______0.000______50.0______111.845____141.450
100-
// clk_out2___175.130______0.000______50.0______113.271____141.450
101-
// clk_out3___155.671______0.000______50.0______115.371____141.450
99+
// clk_out1___190.025______0.000______50.0______100.051____130.256
100+
// clk_out2___174.190______0.000______50.0______101.370____130.256
101+
// clk_out3___156.771______0.000______50.0______102.992____130.256
102+
// clk_out4____92.218______0.000______50.0______111.617____130.256
103+
// clk_out5____87.095______0.000______50.0______112.592____130.256
104+
// clk_out6____74.653______0.000______50.0______115.271____130.256
102105
//
103106
//----------------------------------------------------------------------------
104107
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -107,7 +110,10 @@ always_ff @(negedge rst_main_n or posedge clk_extra_a1)
107110

108111
logic clock_gend_190;
109112
logic clock_gend_175;
110-
logic clock_gend_160;
113+
logic clock_gend_160; // see above, really ~156
114+
logic clock_gend_90; // see above, really ~92
115+
logic clock_gend_85; // see above, really ~87
116+
logic clock_gend_75;
111117

112118
logic firesim_internal_clock;
113119
assign firesim_internal_clock = clock_gend_160;
@@ -118,6 +124,9 @@ clk_wiz_0_firesim firesim_clocking
118124
.clk_out1(clock_gend_190), // output clk_out1
119125
.clk_out2(clock_gend_175), // output clk_out2
120126
.clk_out3(clock_gend_160), // output clk_out3
127+
.clk_out4(clock_gend_90), // output clk_out4
128+
.clk_out5(clock_gend_85), // output clk_out5
129+
.clk_out6(clock_gend_75), // output clk_out6
121130
// Status and control signals
122131
.reset(!rst_extra1_n_sync), // input reset
123132
.locked(), // output locked

‎hdk/cl/developer_designs/cl_firesim/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.dcp‎

-2.66 KB
Binary file not shown.

‎hdk/cl/developer_designs/cl_firesim/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.v‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,12 @@
5656
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5757
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5858
//----------------------------------------------------------------------------
59-
// clk_out1___189.972______0.000______50.0______111.845____141.450
60-
// clk_out2___175.130______0.000______50.0______113.271____141.450
61-
// clk_out3___155.671______0.000______50.0______115.371____141.450
59+
// clk_out1___190.025______0.000______50.0______100.051____130.256
60+
// clk_out2___174.190______0.000______50.0______101.370____130.256
61+
// clk_out3___156.771______0.000______50.0______102.992____130.256
62+
// clk_out4____92.218______0.000______50.0______111.617____130.256
63+
// clk_out5____87.095______0.000______50.0______112.592____130.256
64+
// clk_out6____74.653______0.000______50.0______115.271____130.256
6265
//
6366
//----------------------------------------------------------------------------
6467
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -67,14 +70,17 @@
6770

6871
`timescale 1ps/1ps
6972

70-
(* CORE_GENERATION_INFO = "clk_wiz_0_firesim,clk_wiz_v5_4_0_0,{component_name=clk_wiz_0_firesim,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
73+
(* CORE_GENERATION_INFO = "clk_wiz_0_firesim,clk_wiz_v5_4_0_0,{component_name=clk_wiz_0_firesim,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=6,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
7174

7275
module clk_wiz_0_firesim
7376
(
7477
// Clock out ports
7578
output clk_out1,
7679
output clk_out2,
7780
output clk_out3,
81+
output clk_out4,
82+
output clk_out5,
83+
output clk_out6,
7884
// Status and control signals
7985
input reset,
8086
output locked,
@@ -88,6 +94,9 @@ module clk_wiz_0_firesim
8894
.clk_out1(clk_out1),
8995
.clk_out2(clk_out2),
9096
.clk_out3(clk_out3),
97+
.clk_out4(clk_out4),
98+
.clk_out5(clk_out5),
99+
.clk_out6(clk_out6),
91100
// Status and control signals
92101
.reset(reset),
93102
.locked(locked),

‎hdk/cl/developer_designs/cl_firesim/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.veo‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,12 @@
5555
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5656
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5757
//----------------------------------------------------------------------------
58-
// clk_out1___189.972______0.000______50.0______111.845____141.450
59-
// clk_out2___175.130______0.000______50.0______113.271____141.450
60-
// clk_out3___155.671______0.000______50.0______115.371____141.450
58+
// clk_out1___190.025______0.000______50.0______100.051____130.256
59+
// clk_out2___174.190______0.000______50.0______101.370____130.256
60+
// clk_out3___156.771______0.000______50.0______102.992____130.256
61+
// clk_out4____92.218______0.000______50.0______111.617____130.256
62+
// clk_out5____87.095______0.000______50.0______112.592____130.256
63+
// clk_out6____74.653______0.000______50.0______115.271____130.256
6164
//
6265
//----------------------------------------------------------------------------
6366
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -76,6 +79,9 @@
7679
.clk_out1(clk_out1), // output clk_out1
7780
.clk_out2(clk_out2), // output clk_out2
7881
.clk_out3(clk_out3), // output clk_out3
82+
.clk_out4(clk_out4), // output clk_out4
83+
.clk_out5(clk_out5), // output clk_out5
84+
.clk_out6(clk_out6), // output clk_out6
7985
// Status and control signals
8086
.reset(reset), // input reset
8187
.locked(locked), // output locked

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