Prune an unnecessary timing constraint

Author: davidbiancolin

hdk/cl/developer_designs/cl_firesim/build/constraints/cl_pnr_user.xdc

@@ -1,8 +1,5 @@
 # This contains the CL specific constraints for Top level PNR
 
-# False path between vled on CL clock and Shell asynchronous clock
-set_false_path -from [get_cells WRAPPER_INST/CL/vled_q_reg*] 
-
 # False paths between main clock and tck
 set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]
 set_clock_groups -name TIG_SRAI_2 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks drck]