add stuff to xsim makefiles

Author: alonamid

hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f

@@ -33,6 +33,7 @@
 -y ${SH_SH_DIR}
 -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
 -y ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
+-y ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
 
 +incdir+${CL_ROOT}/../common/design
 +incdir+${CL_ROOT}/design
@@ -43,6 +44,9 @@
 +incdir+${HDK_COMMON_DIR}/verif/include
 +incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
 +incdir+${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
++incdir+${CL_ROOT}/design/axi_crossbar_0
++incdir+${HDK_SHELL_DESIGN_DIR}/ip/cl_axi_interconnect/ipshared/7e3a/hdl
++incdir+${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
 
 ${CL_ROOT}/../common/design/cl_common_defines.vh
 ${CL_ROOT}/design/cl_firesim_defines.vh
@@ -62,6 +66,7 @@
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
+${HDK_SHELL_DESIGN_DIR}/ip/cl_axi_interconnect/sim/cl_axi_interconnect.v
 ${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
 ${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v
 ${CL_ROOT}/ip/axi_clock_converter_oclnew/sim/axi_clock_converter_oclnew.v

hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vivado.f

@@ -34,6 +34,7 @@
 -sourcelibdir ${SH_SH_DIR}
 -sourcelibdir ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/hdl
 -sourcelibdir ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/sim
+-sourcelibdir ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
 
 -include ${CL_ROOT}/../common/design
 -include ${CL_ROOT}/verif/sv
@@ -46,6 +47,9 @@
 -include ${HDK_SHELL_DESIGN_DIR}/ip/cl_debug_bridge/bd_0/ip/ip_0/hdl/verilog
 -include ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/hdl
 -include ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl
+-include ${CL_ROOT}/design/axi_crossbar_0
+-include ${HDK_SHELL_DESIGN_DIR}/ip/cl_axi_interconnect/ipshared/7e3a/hdl
+-include ${HDK_SHELL_DESIGN_DIR}/sh_ddr/sim
 -include ${CL_ROOT}/ip/axi_clock_converter_oclnew/hdl
 -include ${CL_ROOT}/ip/axi_dwidth_converter_0/hdl
 
@@ -70,6 +74,7 @@
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
+${HDK_SHELL_DESIGN_DIR}/ip/cl_axi_interconnect/sim/cl_axi_interconnect.v
 ${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
 ${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v
 ${CL_ROOT}/ip/axi_clock_converter_oclnew/sim/axi_clock_converter_oclnew.v