Skip to content

Commit dee49e3

Browse files
committed
Merge remote-tracking branch 'upstream/master' into width-adapter-fix-upstream-1.3.6
2 parents 633f297 + b1ed5e9 commit dee49e3

File tree

168 files changed

+5718
-1928
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

168 files changed

+5718
-1928
lines changed

.gitignore

Lines changed: 4 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,8 @@ waves.shm
3535
*.a
3636
*.ko
3737

38+
!SDAccel/aws_platform/xilinx_aws-vu9p-f1_1ddr-xpr-2pr_4_0/libxilinxopencl.so
39+
3840
nohup.out
3941
*.nohup.out
4042

@@ -96,15 +98,5 @@ vivado*.log
9698
# pytest artifacts
9799
.cache/
98100

99-
sdk/userspace/lib
100-
101-
hdk/common/shell_v071417d3/build/debug_probes
102-
103-
sdk/linux_kernel_drivers/edma/.edma-drv.ko.cmd
104-
sdk/linux_kernel_drivers/edma/.edma-drv.mod.o.cmd
105-
sdk/linux_kernel_drivers/edma/.edma-drv.o.cmd
106-
sdk/linux_kernel_drivers/edma/.edma.o.cmd
107-
sdk/linux_kernel_drivers/edma/.edma_backend_xdma.o.cmd
108-
sdk/linux_kernel_drivers/edma/.edma_dev.o.cmd
109-
sdk/linux_kernel_drivers/edma/.libxdma.o.cmd
110-
sdk/linux_kernel_drivers/edma/.tmp_versions/
101+
# Patches
102+
patches/*

ERRATA.md

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,10 @@
2121
* FPGA to FPGA over the 400Gbps Ring for F1.16xl
2222
* Aurora and Reliable Aurora modules for the FPGA-to-FPGA
2323
* Preserving the DRAM content between different AFI loads (by the same running instance)
24-
* Cadence RTL simulations tools
24+
* Cadence Xcelium simulations tools
2525
* PCIM and DMA-PCIS AXI-4 interfaces do not support AxSIZE other than 3'b110 (64B)
2626

2727
## Known Bugs/Issues
28-
28+
* F1 CL designs using the v1.3 Shell must treat all clocks within the same group as asynchronous. For example: If using clk_main_a1, clk_extra_a1, clk_extra_a2, and clk_extra_a3 they need to be asynchronous. See [AWS Shell Interface Specification](./hdk/docs/AWS_Shell_Interface_Specification.md)
29+
* The API fpga-load-local-image, has a bug in the error messaging which does not indicate a PCI ID mismatch occurred. The PCI ID’s listed in the AFI manifest when an AFI is submitted to the CreateFpgaImage api (Vendor ID, Device ID, SubSystem ID, or SubSystem Vendor ID) should match the actual values in the submitted DCP. If there is a mismatch between the manifest IDs and the actual device ID, calling fpga-load-local-image on the AFI should report back load-failed (error 7), with a sub-error indicating there is a device ID mismatch. However, fpga-load-local-image does not report the sub-error, leaving no description as to why the load has failed. Until this issue has been fixed, if you experience an AFI load-failed when loading the AFI, double check the device IDs in the submitted manifest match the device IDs in the DCP.
2930

FAQs.md

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,8 @@ The developer can create multiple AFIs at no extra cost, up to a defined limited
107107

108108
**Q: What regions are supported?**
109109

110-
AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon) and eu-west-1 (Ireland).
110+
AWS FPGA generation and EC2 F1 instances are supported in us-east-1 (N. Virginia), us-west-2 (Oregon), eu-west-1 (Ireland) and us-gov-west-1 (GovCloud US).
111+
111112

112113

113114
**Q: What is the process for creating an AFI?**
@@ -137,6 +138,20 @@ Yes, use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) to delete an AFI i
137138

138139
Use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion. Review [IAM policy best practices](http://docs.aws.amazon.com/IAM/latest/UserGuide/best-practices.html#grant-least-privilege) to restrict access to this API.
139140

141+
**Q: Can I share an AFI with other AWS accounts?**
142+
143+
Yes, sharing allows accounts other than the owner account to load and use an AFI. Use [modify-fpga-image-attribute](./hdk/docs/fpga_image_attributes.md) API to update `loadPermission` attribute to grant/remove AFI load permission. AWS AFIs support two load permission types:
144+
* `UserId`: share AFI with specific AWS accounts using account IDs.
145+
* `UserGroups`: only supports `all` group to make an AFI public or private.
146+
147+
Use [reset-fpga-image-attribute](./hdk/docs/fpga_image_attributes.md) API to revoke all load permissions.
148+
149+
**Q: Can I delete an AFI?**
150+
151+
Yes, use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) to delete an AFI in a specific region. Deleting an AFI in one region does not affect AFIs in other regions.
152+
153+
Use [delete-fpga-image](./hdk/docs/delete_fpga_image.md) carefully. Once all AFIs of the same global AFI ID are deleted, the AFIs cannot be recovered from deletion. Review [IAM policy best practices](http://docs.aws.amazon.com/IAM/latest/UserGuide/best-practices.html#grant-least-privilege) to resrict access to this API.
154+
140155
**Q: Can I bring my own bitstream for loading on an F1 FPGA?**
141156

142157
No. There is no mechanism for loading a bitstream directly onto the FPGAs of an F1 instance. All Custom Logic is loaded onto the FPGA by calling `$ fpga-local-load-image` tool at [AWS FPGA SDK](./sdk).
@@ -170,7 +185,7 @@ No. AWS supports a cloud-only development model and provides the necessary eleme
170185

171186
**Q: Do I need to design for a specific power envelope?**
172187

173-
Yes, the design scripts provided in the HDK include checks for power consumption that exceeds the allocated power for the Custom Logic (CL) region. Developers do not need to include design considerations for DRAM, Shell, or Thermal. AWS includes the design considerations for those as part of providing the power envelop for the CL region.
188+
Yes, the Xilinx UltraScale+ FPGA devices used on the F1 instances have a maximum power limit that must be maintained. If a loaded AFI consumes maximum power, the F1 instance will automatically gate the input clocks provided to the AFI in order to prevent errors within the FPGA. Developers are provided warnings when power (Vccint) is greater than 85 watts. Above that level, the CL is in danger of being clock gated. [Additional details on AFI power](hdk/docs/afi_power.md)
174189

175190

176191
**Q: What IP blocks are provided in the HDK?**
@@ -190,6 +205,10 @@ Yes. Developers are free to use any IP blocks within the Custom Logic region. Th
190205

191206

192207
## Getting Started
208+
**Q: What AWS knowledge do I need to learn before I can develop accelerators and run on AWS F1 instances?**
209+
210+
[AWS Getting Started Resource Center](https://aws.amazon.com/getting-started/) has lots of resources to help developers get started. For F1 development, launching linux virtual machines (EC2) and storing and retrieving files from S3 are required skills.
211+
193212
**Q: What do I need to get started on building accelerators for FPGA instances?**
194213

195214
Getting started requires downloading the latest HDK and SDK from the AWS FPGA GitHub repository. The HDK and SDK provide the needed code and information for building FPGA code. The HDK provides all the information needed for developing an FPGA image from source code, while the SDK provides all the runtime software for managing the Amazon FPGA Image (AFI) loaded into the F1 instance FPGA.

0 commit comments

Comments
 (0)