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sagarksagark
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pull in changes from cl_dram_dma to cl_firesim for v1.4.0 bump
1 parent 8e32578 commit df5df87

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7 files changed

+30
-27
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7 files changed

+30
-27
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‎hdk/cl/developer_designs/cl_firesim/build/constraints/cl_pnr_user.xdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# This contains the CL specific constraints for Top level PNR
22

33
# False path between vled on CL clock and Shell asynchronous clock
4-
set_false_path -from [get_cells CL/vled_q_reg*]
4+
set_false_path -from [get_cells WRAPPER_INST/CL/vled_q_reg*]
55

66
# False paths between main clock and tck
77
set_clock_groups -name TIG_SRAI_1 -asynchronous -group [get_clocks -of_objects [get_pins static_sh/SH_DEBUG_BRIDGE/inst/bsip/inst/USE_SOFTBSCAN.U_TAP_TCKBUFG/O]] -group [get_clocks -of_objects [get_pins SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/mmcme3_adv_inst/CLKOUT0]]

‎hdk/cl/developer_designs/cl_firesim/build/scripts/create_dcp_from_cl.tcl‎

Lines changed: 22 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,6 @@ set_msg_config -id {DRC CKLD-2} -suppress
142142
set_msg_config -id {DRC REQP-1853} -suppress
143143
set_msg_config -id {Timing 38-436} -suppress
144144

145-
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
146-
147145
# Check that an email address has been set, else unset notify_via_sns
148146

149147
if {[string compare $notify_via_sns "1"] == 0} {
@@ -185,6 +183,8 @@ switch $strategy {
185183
}
186184
}
187185

186+
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling the encrypt.tcl.";
187+
188188
#Encrypt source code
189189
source encrypt.tcl
190190

@@ -201,12 +201,20 @@ source $HDK_SHELL_DIR/build/scripts/step_user.tcl -notrace
201201
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer's specified recipe.";
202202

203203
source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
204+
#################################################################
205+
##### Do not remove this setting. Need to workaround bug in 2017.4
206+
##################################################################
207+
set_param hd.clockRoutingWireReduction false
204208

205209
##################################################
206210
### CL XPR OOC Synthesis
207211
##################################################
208212
if {${cl.synth}} {
209213
source -notrace ./synth_${CL_MODULE}.tcl
214+
set synth_dcp ${timestamp}.CL.post_synth.dcp
215+
} else {
216+
open_checkpoint ../checkpoints/CL.post_synth.dcp
217+
set synth_dcp CL.post_synth.dcp
210218
}
211219

212220
##################################################
@@ -223,8 +231,9 @@ if {$implement} {
223231
set_property IP_REPO_PATHS $cacheDir [current_project]
224232
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Combining Shell and CL design checkpoints";
225233
add_files $HDK_SHELL_DIR/build/checkpoints/from_aws/SH_CL_BB_routed.dcp
226-
add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
227-
set_property SCOPED_TO_CELLS {CL} [get_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp]
234+
#add_files $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
235+
add_files $CL_DIR/build/checkpoints/$synth_dcp
236+
set_property SCOPED_TO_CELLS {WRAPPER_INST/CL} [get_files $CL_DIR/build/checkpoints/$synth_dcp]
228237

229238
#Read the constraints, note *DO NOT* read cl_clocks_aws (clocks originating from AWS shell)
230239
read_xdc [ list \
@@ -233,7 +242,7 @@ if {$implement} {
233242
set_property PROCESSING_ORDER late [get_files cl_pnr_user.xdc]
234243

235244
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - Running link_design";
236-
link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {SH CL}
245+
link_design -top $TOP -part [DEVICE_TYPE] -reconfig_partitions {WRAPPER_INST/SH WRAPPER_INST/CL}
237246

238247
puts "\nAWS FPGA: ([clock format [clock seconds] -format %T]) - PLATFORM.IMPL==[get_property PLATFORM.IMPL [current_design]]";
239248
##################################################
@@ -309,7 +318,13 @@ if {$implement} {
309318
# This is what will deliver to AWS
310319
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
311320

312-
write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
321+
#FIXME -- THIS SHOULD BE REMOVED FROM THE FINAL SCRIPT
322+
#write_checkpoint -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed_before_ddr_fix.dcp
323+
#source top_ddr_fix.tcl
324+
#checkpoint can used by developer for analysis and hence donot encrypt
325+
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.SH_CL_routed.dcp
326+
#checkpoint that will be sent to aws and hence encrypt
327+
write_checkpoint -encrypt -force $CL_DIR/build/checkpoints/to_aws/${timestamp}.SH_CL_routed.dcp
313328

314329
# Generate debug probes file
315330
write_debug_probes -force -no_partial_ltxfile -file $CL_DIR/build/checkpoints/${timestamp}.debug_probes.ltx
@@ -374,7 +389,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Finished creating
374389

375390
if {[string compare $notify_via_sns "1"] == 0} {
376391
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Calling notification script to send e-mail to $env(EMAIL)";
377-
exec $env(HDK_COMMON_DIR)/scripts/notify_via_sns.py
392+
exec $env(AWS_FPGA_REPO_DIR)/shared/bin/scripts/notify_via_sns.py
378393
}
379394

380395
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Build complete.";

‎hdk/cl/developer_designs/cl_firesim/build/scripts/encrypt.tcl‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -63,20 +63,7 @@ set ver_2017_4 2017.4
6363
puts "AWS FPGA: VIVADO_TOOL_VERSION $TOOL_VERSION"
6464
puts "vivado_version $vivado_version"
6565

66-
if { [string first $ver_2017_4 $vivado_version] == 0 } {
6766
# encrypt .v/.sv/.vh/inc as verilog files
6867
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile_2017_4.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
69-
7068
# encrypt *vhdl files
7169
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile_2017_4.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
72-
73-
puts "encrypting using 2017.4"
74-
} else {
75-
# encrypt .v/.sv/.vh/inc as verilog files
76-
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
77-
78-
# encrypt *vhdl files
79-
encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
80-
81-
puts "encrypting using 2017.1"
82-
}

‎hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,9 +34,10 @@ puts "AWS FPGA: Reading AWS Shell design";
3434

3535
#Read AWS Design files
3636
read_verilog -sv [ list \
37-
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v\
38-
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv\
39-
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v\
37+
$HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
38+
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
39+
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
40+
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
4041
$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
4142
$HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
4243
]

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/Makefile.vivado‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ compile:
2121
mkdir -p $(SIM_DIR)
2222
cd $(SIM_DIR) && xsc $(C_FILES) --additional_option "-I$(C_SDK_USR_INC_DIR)" --additional_option "-I$(C_SDK_USR_UTILS_DIR)" --additional_option "-I$(C_COMMON_DIR)/include" --additional_option "-I$(C_COMMON_DIR)/src" --additional_option "-I$(C_INC_DIR)" --additional_option "-DVIVADO_SIM" --additional_option "-DSV_TEST" --additional_option "-DDMA_TEST"
2323
cd $(SIM_DIR) && xvlog --sv -m64 --define DMA_TEST --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --work xil_defaultlib --relax -f $(SCRIPTS_DIR)/top.vivado.f
24-
cd $(SIM_DIR) && xelab -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_11 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L axi_dwidth_converter_v2_1_12 -L blk_mem_gen_v8_3_6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)
24+
cd $(SIM_DIR) && xelab -m64 --initfile $(XILINX_VIVADO)/data/xsim/ip/xsim_ip.ini --timescale 1ps/1ps --debug typical --relax --mt 8 -L axi_clock_converter_v2_1_14 -L generic_baseblocks_v2_1_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_15 -L axi_register_slice_v2_1_12 -L fifo_generator_v13_2_1 -L fifo_generator_v13_1_4 -L axi_data_fifo_v2_1_11 -L axi_crossbar_v2_1_13 -L axi_dwidth_converter_v2_1_12 -L blk_mem_gen_v8_3_6 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -sv_lib dpi --snapshot tb xil_defaultlib.tb xil_defaultlib.glbl xil_defaultlib.$(TEST)
2525

2626
compile_chk:
2727
mkdir -p $(SIM_DIR)

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@
6262
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
6363
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
6464
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
65-
${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
65+
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
6666
${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v
6767
${CL_ROOT}/ip/axi_clock_converter_oclnew/sim/axi_clock_converter_oclnew.v
6868
${CL_ROOT}/ip/axi_clock_converter_512_wide/sim/axi_clock_converter_512_wide.v

‎hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vivado.f‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
6262
${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
6363
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v
64-
${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
64+
${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
6565
${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v
6666
${CL_ROOT}/ip/axi_clock_converter_oclnew/sim/axi_clock_converter_oclnew.v
6767
${CL_ROOT}/ip/axi_clock_converter_512_wide/sim/axi_clock_converter_512_wide.v

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