Generate PLL IP on every build with a single desired frequency

Author: davidbiancolin

hdk/cl/developer_designs/cl_firesim/build/scripts/create_dcp_from_cl.tcl

@@ -154,6 +154,10 @@ if {[string compare $notify_via_sns "1"] == 0} {
     puts "AWS FPGA: ([clock format [clock seconds] -format %T]) EMAIL address for completion notification set to $env(EMAIL).";
   }
 }
+##################################################
+### Source FireSim Generated TCL Env variables
+##################################################
+source $CL_DIR/design/cl_firesim_generated_env.tcl
 
 ##################################################
 ### Strategy options 
@@ -271,6 +275,7 @@ if {$implement} {
          impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
       }
    }
+   report_utilization -hierarchical -file $CL_DIR/build/reports/${timestamp}.post_opt_utilization.rpt
 
    ########################
    # CL Place

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

@@ -78,13 +78,12 @@ read_ip [ list \
   $CL_DIR/ip/axi_clock_converter_oclnew/axi_clock_converter_oclnew.xci \
   $CL_DIR/ip/axi_clock_converter_512_wide/axi_clock_converter_512_wide.xci \
   $CL_DIR/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci \
-  $CL_DIR/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.xci \
   $CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci
 ]
 
 # Additional IP's that might be needed if using the DDR
 read_ip [ list \
- $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci 
+ $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci
 ]
 read_bd [ list \
  $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
@@ -104,6 +103,9 @@ read_xdc [ list \
    $CL_DIR/build/constraints/cl_synth_user.xdc
 ]
 
+# FireSim custom clocking
+source $CL_DIR/build/scripts/synth_firesim_clk_wiz.tcl
+
 #Do not propagate local clock constraints for clocks generated in the SH
 set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
 set_property PROCESSING_ORDER EARLY  [get_files cl_clocks_aws.xdc]

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_firesim_clk_wiz.tcl

@@ -0,0 +1,7 @@
+read_ip [list $CL_DIR/ip/clk_wiz_0_firesim/clk_wiz_0_firesim.xci]
+upgrade_ip [get_ips clk_wiz_0_firesim]
+set_property CONFIG.CLKOUT1_REQUESTED_OUT_FREQ $desired_host_frequency [get_ips clk_wiz_0_firesim]
+# # Generates half the output files
+generate_target {all} [get_ips clk_wiz_0_firesim]
+# # Generates some missing stub files for sim and the dcp
+synth_ip [get_ips clk_wiz_0_firesim]

hdk/cl/developer_designs/cl_firesim/design/cl_firesim.sv

@@ -86,50 +86,14 @@ always_ff @(negedge rst_main_n or posedge clk_extra_a1)
       rst_extra1_n_sync <= pre_sync_rst_n_extra1;
    end
 
-
-
 //---------------------------
-// new clocking
-//-------------------
-// None
-//
-//----------------------------------------------------------------------------
-//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
-//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
-//----------------------------------------------------------------------------
-// clk_out1___190.025______0.000______50.0______100.051____130.256
-// clk_out2___174.190______0.000______50.0______101.370____130.256
-// clk_out3___156.771______0.000______50.0______102.992____130.256
-// clk_out4____92.218______0.000______50.0______111.617____130.256
-// clk_out5____87.095______0.000______50.0______112.592____130.256
-// clk_out6____74.653______0.000______50.0______115.271____130.256
-//
-//----------------------------------------------------------------------------
-// Input Clock   Freq (MHz)    Input Jitter (UI)
-//----------------------------------------------------------------------------
-// __primary_________125.000____________0.010
-
-logic clock_gend_190;
-logic clock_gend_175;
-logic clock_gend_160; // see above, really ~156
-logic clock_gend_90;  // see above, really ~92
-logic clock_gend_85;  // see above, really ~87
-logic clock_gend_75;
-
-`define FIRESIM_CLOCK_SIGNAL_SETTING(freq)    clock_gend_``freq
 
 logic firesim_internal_clock;
-assign firesim_internal_clock = `FIRESIM_CLOCK_SIGNAL_SETTING(`SELECTED_FIRESIM_CLOCK);
 
 clk_wiz_0_firesim firesim_clocking
 (
     // Clock out ports
-    .clk_out1(clock_gend_190),     // output clk_out1
-    .clk_out2(clock_gend_175),     // output clk_out2
-    .clk_out3(clock_gend_160),     // output clk_out3
-    .clk_out4(clock_gend_90),     // output clk_out4
-    .clk_out5(clock_gend_85),     // output clk_out5
-    .clk_out6(clock_gend_75),     // output clk_out6
+    .clk_out1(firesim_internal_clock),
     // Status and control signals
     .reset(!rst_extra1_n_sync), // input reset
     .locked(),       // output locked

hdk/cl/developer_designs/cl_firesim/ip/clk_wiz_0_firesim/.gitignore

@@ -0,0 +1,2 @@
+doc
+.Xil