add DDR channels

Author: alonamid

hdk/cl/developer_designs/cl_firesim/build/scripts/synth_cl_firesim.tcl

@@ -48,6 +48,11 @@ read_verilog -sv [ list \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
   $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
+  $HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
+  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv  \
+  $HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv  \
   $HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
 ]
 
@@ -76,10 +81,10 @@ read_ip [ list \
 ]
 
 # Additional IP's that might be needed if using the DDR
-#read_bd [ list \
-# $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci \
-# $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
-#]
+read_bd [ list \
+ $HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci \
+ $HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
+]
 
 puts "AWS FPGA: Reading AWS constraints";