Merge pull request #3 from firesim/donggyu-bump-with-mem-model

Move simulation defines into makefrags

Author: davidbiancolin

hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vcs.f

@@ -15,6 +15,12 @@
 
 +define+VCS_SIM
 +define+CARD_1=card
++define+RANDOMIZE_MEM_INIT
++define+RANDOMIZE_REG_INIT
++define+RANDOMIZE_GARBAGE_ASSIGN
++define+RANDOMIZE_INVALID_ASSIGN
++define+PRINTF_COND=1'b1
++define+STOP_COND=1'b1
 +libext+.v
 +libext+.sv
 +libext+.svh
@@ -55,12 +61,11 @@
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v
 ${HDK_SHELL_DESIGN_DIR}/ip/axi_register_slice/sim/axi_register_slice.v
-${HDK_SHELL_DESIGN_DIR}/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
-${CL_ROOT}/ip/axi_dwidth_converter_dram/sim/axi_dwidth_converter_dram.v
-${CL_ROOT}/ip/axi_clock_converter_dram/sim/axi_clock_converter_dram.v
-${CL_ROOT}/ip/axi_clock_converter_ocl2/sim/axi_clock_converter_ocl2.v
-
-
+${SH_LIB_DIR}/../ip/axi_clock_converter_0/sim/axi_clock_converter_0.v
+${CL_ROOT}/ip/axi_clock_converter_dramslim/sim/axi_clock_converter_dramslim.v
+${CL_ROOT}/ip/axi_clock_converter_oclnew/sim/axi_clock_converter_oclnew.v
+${CL_ROOT}/ip/axi_clock_converter_512_wide/sim/axi_clock_converter_512_wide.v
+${CL_ROOT}/ip/clk_wiz_0_firesim/clk_wiz_0_firesim_sim_netlist.v
 ${CL_ROOT}/design/cl_firesim_generated.sv
 ${CL_ROOT}/design/cl_firesim.sv
 

hdk/cl/developer_designs/cl_firesim/verif/scripts/top.vivado.f

@@ -14,6 +14,12 @@
 # limitations under the License.
 
 -define VIVADO_SIM
+-define RANDOMIZE_MEM_INIT
+-define RANDOMIZE_REG_INIT
+-define RANDOMIZE_GARBAGE_ASSIGN
+-define RANDOMIZE_INVALID_ASSIGN
+-define PRINTF_COND=1'b1
+-define STOP_COND=1'b1
 
 -sourcelibext .v
 -sourcelibext .sv