Porting blinky, servant, corescore to board Chameleon96 #51
Description
**Brief introduction of the Arrow Chameleon96 board (https://www.96boards.org/product/chameleon96/):
This board is a Cyclone V board (same chip as de10-nano) but FPGA was considered secondary and Novtech who designed the board did not include a direct pin clock into the FPGA fabric...
So in this board to get a clock signal we must use Platform Designer (Qsys) and loan one of the HPS clocks (ARM side) to the FPGA side (This is what Altera call LoanIO pins).
**What is needed to port Fusesoc cores to Chameleon96:
Firstly I need to include a .qsys file but I think this is not suported in Fusesoc yet. I tried with this but gave me error of course because it's not a verilog file.
- rtl/chameleon96_soc_hps.qsys : {file_type : verilogSource}