Detect if 5-level paging is actually enabled on the host.

The CPUID can indicate support for 5-level paging (57 virtual address bits),
 but the kernel might not have it enabled. This change adds a check using
`mmap` to see if addresses above 2^48 are usable. If not,
`VirtualAddressBits` is capped at 48, even if CPUID suggests 57.

Fixes #12308

PiperOrigin-RevId: 832518109

Author: tranji-cloud

pkg/cpuid/BUILD

@@ -22,8 +22,11 @@ go_library(
     ],
     visibility = ["//:sandbox"],
     deps = [
+        "//pkg/hostarch",
+        "//pkg/hostsyscall",
         "//pkg/log",
         "//pkg/sync",
+        "@org_golang_x_sys//unix:go_default_library",
     ],
 )
 

pkg/cpuid/cpuid_amd64.go

@@ -21,6 +21,12 @@ import (
 	"context"
 	"fmt"
 	"io"
+
+	"golang.org/x/sys/unix"
+	"gvisor.dev/gvisor/pkg/hostarch"
+	"gvisor.dev/gvisor/pkg/hostsyscall"
+	"gvisor.dev/gvisor/pkg/log"
+	"gvisor.dev/gvisor/pkg/sync"
 )
 
 // FeatureSet defines features in terms of CPUID leaves and bits.
@@ -494,3 +500,27 @@ func (fs FeatureSet) AllowedHWCap2() uint64 {
 	// HWCAPS are not supported on amd64.
 	return 0
 }
+
+var fiveLevelPaging struct {
+	once    sync.Once
+	enabled bool
+}
+
+// FiveLevelPagingEnabled checks if 5-level paging is enabled on the host.
+//
+//go:nosplit
+func FiveLevelPagingEnabled() bool {
+	fiveLevelPaging.once.Do(func() {
+		addr := uintptr(1 << 48)
+		p, errno := hostsyscall.RawSyscall6(unix.SYS_MMAP,
+			addr, hostarch.PageSize, unix.PROT_NONE, unix.MAP_PRIVATE|unix.MAP_ANONYMOUS|unix.MAP_FIXED, 0, 0)
+		if errno != 0 {
+			log.Infof("5-level paging is not enabled: Failed to mmap a page size %d at 0x%x: %v", hostarch.PageSize, addr, errno)
+			fiveLevelPaging.enabled = false
+		} else {
+			hostsyscall.RawSyscall(unix.SYS_MUNMAP, p, hostarch.PageSize, 0)
+			fiveLevelPaging.enabled = true
+		}
+	})
+	return fiveLevelPaging.enabled
+}

pkg/ring0/kernel_amd64.go

@@ -205,7 +205,7 @@ func (c *CPU) CR4() uint64 {
 	if hasUMIP {
 		cr4 |= _CR4_UMIP
 	}
-	if hasLA57 {
+	if hasLA57 && cpuid.FiveLevelPagingEnabled() {
 		cr4 |= _CR4_LA57
 	}
 	return cr4
@@ -222,6 +222,9 @@ func (c *CPU) EFER() uint64 {
 //
 //go:nosplit
 func IsCanonical(addr uint64) bool {
+	if hasLA57 && cpuid.FiveLevelPagingEnabled() {
+		return addr <= 0x00ffffffffffffff || addr >= 0xff00000000000000
+	}
 	return addr <= 0x00007fffffffffff || addr >= 0xffff800000000000
 }
 

pkg/ring0/lib_amd64.go

@@ -100,7 +100,11 @@ var (
 // another time with a  different FeatureSet.
 func Init(fs cpuid.FeatureSet) {
 	// Initialize all sizes.
-	VirtualAddressBits = uintptr(fs.VirtualAddressBits())
+	if fs.VirtualAddressBits() > 48 && !cpuid.FiveLevelPagingEnabled() {
+		VirtualAddressBits = 48
+	} else {
+		VirtualAddressBits = uintptr(fs.VirtualAddressBits())
+	}
 	if PhysicalAddressBits == 0 {
 		PhysicalAddressBits = uintptr(fs.PhysicalAddressBits())
 	}

pkg/ring0/pagetables/pagetables_amd64.go

@@ -54,7 +54,7 @@ const (
 //go:nosplit
 func (p *PageTables) InitArch(allocator Allocator) {
 	featureSet := cpuid.HostFeatureSet()
-	if featureSet.HasFeature(cpuid.X86FeatureLA57) {
+	if featureSet.HasFeature(cpuid.X86FeatureLA57) && cpuid.FiveLevelPagingEnabled() {
 		p.largeAddressesEnabled = true
 		lowerTop = 0x00FFFFFFFFFFFFFF
 		upperBottom = 0xFF00000000000000

pkg/ring0/pagetables/pagetables_amd64_test.go

@@ -31,7 +31,7 @@ var (
 
 func getLargeAddressesEnabled() bool {
 	featureSet := cpuid.HostFeatureSet()
-	return featureSet.HasFeature(cpuid.X86FeatureLA57)
+	return featureSet.HasFeature(cpuid.X86FeatureLA57) && cpuid.FiveLevelPagingEnabled()
 }
 
 func getLowerTopAligned() uintptr {