Feedback wanted - LogicAnalyzer V3

[gusmanb]

Hey! I know it seems like latelly has not been too much activity in the project, but that's because I've been working on the next iteration of the logic analyzer.

Let me show you what I have come to for this new version:

As you can see it's a big overhaul of the analyzer, let me show you what will be the functionalities and major changes.

• 31 input channels, I know a lot of people will love this as with a single analyzer you will be able to fully supervise a 8bit CPU
• 8 output channels, yes, you will be able to generate signals from the analyzer!
• 6 GPIOs, for now will be unused but in the future I may add support for SPI, I2C and UART
• 8MB of PSRAM! It will be used with low speed captures (still need to test the practical limits) and for the signal generator
• Based on the WaveShare Core2350B module to ease assembling

For capturing the improvements are clear, with 31 channels if you want to supervise for example a Z80 or a 6502 you will now have enough IOs with a single analyzer, 16 channels for address, 8 for data and 7 for additional signals will have all the key signals captured at once without the need of chaining a second analizer. Also, the new 8MB PSRAM will allow to capture massive amounts of data for slow speed captures. I have been toying with PSRAM for another project and I've got up to 50Mb/s write speeds, so this could mean up to 40Msps on 8 channels or 10Msps on 31 channels. We are talking around 8 million samples on 8 channel mode or 2 million samples on 31 channel mode, this is a 20x increase in size!

Next, the signal generator. You may have seen that the software contains a signal generator and a language to create signals, this has been in the backlog for a long time and now is the moment to implement it. You will be able to create up to 8 channels of signals and replay them from the device (or even replay captured signals from other devices 😄 ). I will not target very fast speeds but I think it will support up to 50Mhz without problems.

Finally there is a 6 pin port, these are the "leftover" pins, will not be used for now but in the future it may give support for SPI, I2C, UART or GPIO to be controlled using a small scripting language, that will be target of a later version if there is enough free ram.

In this new revision I have tried to ease the assembly for anyone that wants to do it manually: modules are again on pins instead of soldered directly to the board, all components are 0603 with hand-soldering pads, I have tried to leave enough room between components to fit properly the soldering iron (but without affecting the design's performance), etc. I also have ditched away the usage of JITX as it makes collaboration a pain while a plain KiCad project makes it extremely easy.

I have opted to use the WaveShare module because it reduces a lot the number of components to assemble and removes the complexity of soldering the RP2350B, so it is really easy to assemble manually. Also, I LOVE the aspect of this thing, the ressemblance to a i386 makes me to love it 😄

I was working in a more massive version with two RP2350B, but the complexity and the cost would make it not worth it for a lot of people, so I think this version is a good compromise between new functionalities and affordability, you still can chain 5 analyzers (so the limit will be raised to 155 channels!) but I know that for a very large user base this new analyzer will remove the need of chaining two of these and will be a lot more affordable at the end.

So, this is the target of the new design. What do you think? I would love to hear your thoughts about it (please, keep in mind the hand-soldering aspect, I have two "sides" of users, the ones that complain because I still use the pico modules and do not build a board from scratch, and the ones that complain that is difficult to assemble all manually, so I have decided to favor the manual assembling of the device 😆). Do you have any idea for the 6 left GPIOs? Maybe something that could be integrated on the device? Maybe changes to the shape in order to make it easier to build a 3D printed box? Throw whatever you think, any comment is welcome 😄

Thanks all for the support to the project!

[nizce]

Hi!
Quite new to electronics but love retro computers :)
Stumbled onto this project yesterday and ordered a couple of PCBs. This project made me aware of logic analysers and the great use and insights it can give! :) So that you so much for that.

Using the waveshare module, it seems like wifi would be lost?
As I said I'm very new and still learning, but one thing about the possibility of using a pico 2w with wifi was that I could power the logicanalyzer with a power bank and thus be safe from potential ground loops(if I understand correctly and do something foolish) since I could interact with it via via wifi.

So yeah, take it as feedback IF I got It right :D

[gusmanb]

The analyzer V2 will still work, so nothing is lost, I always maintain compatibility with all the boards 😄 . Also one of the possibilities that I have considered is to create a WiFi module and use the GPIO port for that, but I'm not sure if this model with the pattern generator and the handling of the PSRAM will have enough memory... maybe I could add the WiFi stack to the PSRAM itself :)

[nizce]

Don't want your progress to get hindered by having to support too many old boards :)
I guess a USB galvanic isolator could be used on the new board to keep us noobs be more "safe" from creating around loops.
But then again, a WIFI adapter/add-on would be much coolers :)

Thanks! And great work!