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Outline verification incorrect #10

@jamosaur

Description

@jamosaur

Describe the bug

With small PCB's, the outline verification is incorrect and causes the panelised output to have no edgecuts whatsoever.

as you can see in the screenshots, the layout validation is a fraction of the size of the PCB.

To Reproduce
Steps to reproduce the behavior:

import gerbers, set JLC type, set panel to 8x5 (breaks even at 2x1)

Expected behavior
A panelised PCB to be created

Screenshots
image
image

Desktop (please complete the following information):

  • OS: Linux

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