From c01bcbbb374cd5be412c204cc27b16771a467d83 Mon Sep 17 00:00:00 2001 From: Sride Shankar Date: Sun, 9 Jun 2024 17:43:34 +0530 Subject: [PATCH] update readmes --- README.md | 45 +++++++++++++++++++++++++++------------------ codes/Q1/README.md | 1 + codes/Q10/README.md | 1 + codes/Q2/README.md | 1 + codes/Q3/README.md | 1 + codes/Q4/README.md | 1 + codes/Q5/README.md | 1 + codes/Q6/README.md | 1 + codes/Q7/README.md | 1 + codes/Q8/README.md | 1 + codes/Q9/README.md | 1 + 11 files changed, 37 insertions(+), 18 deletions(-) create mode 100644 codes/Q3/README.md diff --git a/README.md b/README.md index 6eb9aa4..d987416 100644 --- a/README.md +++ b/README.md @@ -1,61 +1,70 @@ # Questions, Codes & Their Solutions -## Try these questions on your own before you head to the solutions. +## Try these questions on your own before you head to the solutions. -Q1: Implement a 4-bit register using D flip-flops. +Q1: Registers -[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register.v) -[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register_tb.v) +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/README.md) +[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register.v) +[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q1/register_tb.v) -Q2: Implement an 8-bit register using behavioral modeling with a single read and write port such that both read and write operations can occur simultaneously, but when they do read is given more priority. +Q2: Registers -[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations.v) -[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations_tb.v) +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/README.md) +[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations.v) +[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q2/registeroperations_tb.v) -Q3: Implement an 8-bit SISO shift register using behavioral modeling. +Q3: Shift Registers -[Solution Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO.v) -[Testbench Code: ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO_tb.v) +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/README.md) +[Solution Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO.v) +[Testbench Code ](https://github.com/hwlabnitc/Registers/blob/main/codes/Q3/shiftregister_SISO_tb.v) -Q4: Implement an 8-bit SIPO shift register using behavioral modeling. +Q4: Shift Registers +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/shiftregister_SIPO.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q4/shiftregister_SIPO_tb.v) -Q5: Implement an 8-bit PISO shift register using behavioral modeling. +Q5: Shift Registers +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/shiftregister_PISO.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q5/shiftregister_PISO_tb.v) -Q6: Implement an 8-bit PIPO shift register using behavioral modeling. +Q6: Shift Registers +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/shiftregister_PIPO.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q6/shiftregister_PIPO_tb.v) -Q7: Implement an 8-bit register with 1 read port and 2 write ports. Either read or write is permitted at a time and when you perform write, you are to write through the two write ports alternately. +Q7: Registers +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/regnew.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q7/regnew_tb.v) -Q8: Implement an 8-bit register file with 8 registers such that only a read or write can oc -cur at a time. +Q8: Register File +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/regfile2.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q8/regfile2_tb.v) -Q9: Implement a 64-bit register file with 32 register with 4 read ports and 2 write ports. Multiple operations can occur at a time, but the lower port is given more priority in such cases. Read > Write . +Q9: Register File +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/regfile3.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q9/regfile3_tb.v) -Q10: Implement a 4-bit universal shift register. +Q10: Universal Shift Register +[Question](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/README.md) [Solution Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/universal_shift_register.v) [Testbench Code](https://github.com/hwlabnitc/Registers/blob/main/codes/Q10/universal_shift_register_tb.v) diff --git a/codes/Q1/README.md b/codes/Q1/README.md index e69de29..7c4d04e 100644 --- a/codes/Q1/README.md +++ b/codes/Q1/README.md @@ -0,0 +1 @@ +Implement a 4-bit register using D flip-flops. \ No newline at end of file diff --git a/codes/Q10/README.md b/codes/Q10/README.md index e69de29..397255c 100644 --- a/codes/Q10/README.md +++ b/codes/Q10/README.md @@ -0,0 +1 @@ +Implement a 4-bit universal shift register. \ No newline at end of file diff --git a/codes/Q2/README.md b/codes/Q2/README.md index e69de29..8d7858f 100644 --- a/codes/Q2/README.md +++ b/codes/Q2/README.md @@ -0,0 +1 @@ +Implement an 8-bit register using behavioral modeling with a single read and write port such that both read and write operations can occur simultaneously, but when they do read is given more priority. \ No newline at end of file diff --git a/codes/Q3/README.md b/codes/Q3/README.md new file mode 100644 index 0000000..26db479 --- /dev/null +++ b/codes/Q3/README.md @@ -0,0 +1 @@ +Implement an 8-bit SISO shift register using behavioral modeling. \ No newline at end of file diff --git a/codes/Q4/README.md b/codes/Q4/README.md index e69de29..af2053b 100644 --- a/codes/Q4/README.md +++ b/codes/Q4/README.md @@ -0,0 +1 @@ +Implement an 8-bit SIPO shift register using behavioral modeling. \ No newline at end of file diff --git a/codes/Q5/README.md b/codes/Q5/README.md index e69de29..e21d0e6 100644 --- a/codes/Q5/README.md +++ b/codes/Q5/README.md @@ -0,0 +1 @@ +Implement an 8-bit PISO shift register using behavioral modeling. \ No newline at end of file diff --git a/codes/Q6/README.md b/codes/Q6/README.md index e69de29..426a1ce 100644 --- a/codes/Q6/README.md +++ b/codes/Q6/README.md @@ -0,0 +1 @@ +Implement an 8-bit PIPO shift register using behavioral modeling. \ No newline at end of file diff --git a/codes/Q7/README.md b/codes/Q7/README.md index e69de29..c44f3b7 100644 --- a/codes/Q7/README.md +++ b/codes/Q7/README.md @@ -0,0 +1 @@ +Implement an 8-bit register with 1 read port and 2 write ports. Either read or write is permitted at a time and when you perform write, you are to write through the two write ports alternately. \ No newline at end of file diff --git a/codes/Q8/README.md b/codes/Q8/README.md index e69de29..90e5773 100644 --- a/codes/Q8/README.md +++ b/codes/Q8/README.md @@ -0,0 +1 @@ +Implement an 8-bit register file with 8 registers such that only a read or write can occur at a time. \ No newline at end of file diff --git a/codes/Q9/README.md b/codes/Q9/README.md index e69de29..0e26800 100644 --- a/codes/Q9/README.md +++ b/codes/Q9/README.md @@ -0,0 +1 @@ +Implement a 64-bit register file with 32 register with 4 read ports and 2 write ports. Multiple operations can occur at a time, but the lower port is given more priority in such cases. Read > Write . \ No newline at end of file