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[SelectionDAG] Use getShiftAmountConstant. (llvm#158395)
Many of the shifts in LegalizeIntegerTypes.cpp were using getPointerTy.
1 parent 4ebd202 commit 4cbf440

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4 files changed

+46
-72
lines changed

4 files changed

+46
-72
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp‎

Lines changed: 24 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -585,8 +585,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
585585
DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(IncrementSize), dl);
586586
Hi = DAG.getNode(
587587
ISD::SRL, dl, Value.getValueType(), Value,
588-
DAG.getConstant(RoundWidth, dl,
589-
TLI.getShiftAmountTy(Value.getValueType(), DL)));
588+
DAG.getShiftAmountConstant(RoundWidth, Value.getValueType(), dl));
590589
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
591590
ST->getPointerInfo().getWithOffset(IncrementSize),
592591
ExtraVT, ST->getBaseAlign(), MMOFlags, AAInfo);
@@ -596,8 +595,7 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
596595
// Store the top RoundWidth bits.
597596
Hi = DAG.getNode(
598597
ISD::SRL, dl, Value.getValueType(), Value,
599-
DAG.getConstant(ExtraWidth, dl,
600-
TLI.getShiftAmountTy(Value.getValueType(), DL)));
598+
DAG.getShiftAmountConstant(ExtraWidth, Value.getValueType(), dl));
601599
Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), RoundVT,
602600
ST->getBaseAlign(), MMOFlags, AAInfo);
603601

@@ -816,8 +814,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
816814
// Move the top bits to the right place.
817815
Hi = DAG.getNode(
818816
ISD::SHL, dl, Hi.getValueType(), Hi,
819-
DAG.getConstant(RoundWidth, dl,
820-
TLI.getShiftAmountTy(Hi.getValueType(), DL)));
817+
DAG.getShiftAmountConstant(RoundWidth, Hi.getValueType(), dl));
821818

822819
// Join the hi and lo parts.
823820
Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
@@ -845,8 +842,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
845842
// Move the top bits to the right place.
846843
Hi = DAG.getNode(
847844
ISD::SHL, dl, Hi.getValueType(), Hi,
848-
DAG.getConstant(ExtraWidth, dl,
849-
TLI.getShiftAmountTy(Hi.getValueType(), DL)));
845+
DAG.getShiftAmountConstant(ExtraWidth, Hi.getValueType(), dl));
850846

851847
// Join the hi and lo parts.
852848
Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
@@ -2767,8 +2763,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(SDNode *Node,
27672763
SDValue SignBitTest = DAG.getSetCC(
27682764
dl, SetCCVT, Op0, DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
27692765

2770-
EVT ShiftVT = TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout());
2771-
SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
2766+
SDValue ShiftConst = DAG.getShiftAmountConstant(1, SrcVT, dl);
27722767
SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
27732768
SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
27742769
SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
@@ -3350,10 +3345,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
33503345
} else {
33513346
Op = DAG.getAnyExtOrTrunc(Op, dl, MVT::i32);
33523347
}
3353-
Op = DAG.getNode(
3354-
ISD::SHL, dl, MVT::i32, Op,
3355-
DAG.getConstant(16, dl,
3356-
TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
3348+
Op = DAG.getNode(ISD::SHL, dl, MVT::i32, Op,
3349+
DAG.getShiftAmountConstant(16, MVT::i32, dl));
33573350
Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op);
33583351
// Add fp_extend in case the output is bigger than f32.
33593352
if (Node->getValueType(0) != MVT::f32)
@@ -3370,10 +3363,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
33703363
if (!DAG.isKnownNeverSNaN(Op)) {
33713364
Op = DAG.getNode(ISD::FCANONICALIZE, dl, MVT::f32, Op, Node->getFlags());
33723365
}
3373-
Op = DAG.getNode(
3374-
ISD::SRL, dl, MVT::i32, DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op),
3375-
DAG.getConstant(16, dl,
3376-
TLI.getShiftAmountTy(MVT::i32, DAG.getDataLayout())));
3366+
Op = DAG.getNode(ISD::SRL, dl, MVT::i32,
3367+
DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op),
3368+
DAG.getShiftAmountConstant(16, MVT::i32, dl));
33773369
// The result of this node can be bf16 or an integer type in case bf16 is
33783370
// not supported on the target and was softened to i16 for storage.
33793371
if (Node->getValueType(0) == MVT::bf16) {
@@ -3431,13 +3423,11 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
34313423

34323424
// NOTE: we could fall back on load/store here too for targets without
34333425
// SRA. However, it is doubtful that any exist.
3434-
EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
34353426
unsigned BitsDiff = VT.getScalarSizeInBits() -
34363427
ExtraVT.getScalarSizeInBits();
3437-
SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3438-
Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3439-
Node->getOperand(0), ShiftCst);
3440-
Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3428+
SDValue ShiftCst = DAG.getShiftAmountConstant(BitsDiff, VT, dl);
3429+
Tmp1 = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftCst);
3430+
Tmp1 = DAG.getNode(ISD::SRA, dl, VT, Tmp1, ShiftCst);
34413431
Results.push_back(Tmp1);
34423432
break;
34433433
}
@@ -3666,11 +3656,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
36663656
EVT OpTy = Node->getOperand(0).getValueType();
36673657
if (Node->getConstantOperandVal(1)) {
36683658
// 1 -> Hi
3669-
Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3670-
DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3671-
TLI.getShiftAmountTy(
3672-
Node->getOperand(0).getValueType(),
3673-
DAG.getDataLayout())));
3659+
Tmp1 = DAG.getNode(
3660+
ISD::SRL, dl, OpTy, Node->getOperand(0),
3661+
DAG.getShiftAmountConstant(OpTy.getSizeInBits() / 2, OpTy, dl));
36743662
Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
36753663
} else {
36763664
// 0 -> Lo
@@ -3950,9 +3938,8 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
39503938
for (unsigned i = 0; i < 2; ++i) {
39513939
SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
39523940
SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3953-
SDValue Shift = DAG.getConstant(
3954-
HalfType.getScalarSizeInBits(), dl,
3955-
TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3941+
SDValue Shift =
3942+
DAG.getShiftAmountConstant(HalfType.getScalarSizeInBits(), VT, dl);
39563943
Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
39573944
Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
39583945
}
@@ -3999,8 +3986,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
39993986
Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
40003987
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
40013988
SDValue Shift =
4002-
DAG.getConstant(HalfType.getSizeInBits(), dl,
4003-
TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3989+
DAG.getShiftAmountConstant(HalfType.getSizeInBits(), VT, dl);
40043990
Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
40053991
Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
40063992
}
@@ -4130,8 +4116,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
41304116
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
41314117
Tmp2 = DAG.getNode(
41324118
ISD::SHL, dl, PairTy, Tmp2,
4133-
DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
4134-
TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
4119+
DAG.getShiftAmountConstant(PairTy.getSizeInBits() / 2, PairTy, dl));
41354120
Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
41364121
break;
41374122
}
@@ -5368,10 +5353,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
53685353
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
53695354
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
53705355
Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
5371-
Tmp1 = DAG.getNode(
5372-
ISD::SRL, dl, NVT, Tmp1,
5373-
DAG.getConstant(DiffBits, dl,
5374-
TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
5356+
Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
5357+
DAG.getShiftAmountConstant(DiffBits, NVT, dl));
53755358

53765359
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
53775360
break;
@@ -5483,11 +5466,9 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54835466
Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
54845467
Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
54855468

5486-
auto &DL = DAG.getDataLayout();
54875469
unsigned OriginalSize = OVT.getScalarSizeInBits();
5488-
Tmp2 = DAG.getNode(
5489-
ISD::SRL, dl, NVT, Tmp1,
5490-
DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
5470+
Tmp2 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
5471+
DAG.getShiftAmountConstant(OriginalSize, NVT, dl));
54915472
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
54925473
Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
54935474
break;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp‎

Lines changed: 20 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1938,9 +1938,9 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
19381938
for (unsigned i = 1; i < NumRegs; ++i) {
19391939
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
19401940
// Shift it to the right position and "or" it in.
1941-
Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1942-
DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1943-
TLI.getPointerTy(DAG.getDataLayout())));
1941+
Part = DAG.getNode(
1942+
ISD::SHL, dl, NVT, Part,
1943+
DAG.getShiftAmountConstant(i * RegVT.getSizeInBits(), NVT, dl));
19441944
Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
19451945
}
19461946

@@ -2293,9 +2293,9 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
22932293
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
22942294
SDLoc dl(N);
22952295

2296-
Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
2297-
DAG.getConstant(OVT.getSizeInBits(), dl,
2298-
TLI.getPointerTy(DAG.getDataLayout())));
2296+
Hi = DAG.getNode(
2297+
ISD::SHL, dl, N->getValueType(0), Hi,
2298+
DAG.getShiftAmountConstant(OVT.getSizeInBits(), N->getValueType(0), dl));
22992299
return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
23002300
}
23012301

@@ -3943,8 +3943,7 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
39433943
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
39443944
// The high part replicates the sign bit of Lo, make it explicit.
39453945
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3946-
DAG.getConstant(NVTBits - 1, dl,
3947-
TLI.getPointerTy(DAG.getDataLayout())));
3946+
DAG.getShiftAmountConstant(NVTBits - 1, NVT, dl));
39483947
}
39493948
}
39503949

@@ -4329,8 +4328,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
43294328
// lo part.
43304329
unsigned LoSize = Lo.getValueSizeInBits();
43314330
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
4332-
DAG.getConstant(LoSize - 1, dl,
4333-
TLI.getPointerTy(DAG.getDataLayout())));
4331+
DAG.getShiftAmountConstant(LoSize - 1, NVT, dl));
43344332
} else if (ExtType == ISD::ZEXTLOAD) {
43354333
// The high part is just a zero.
43364334
Hi = DAG.getConstant(0, dl, NVT);
@@ -4391,13 +4389,12 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
43914389
Lo = DAG.getNode(
43924390
ISD::OR, dl, NVT, Lo,
43934391
DAG.getNode(ISD::SHL, dl, NVT, Hi,
4394-
DAG.getConstant(ExcessBits, dl,
4395-
TLI.getPointerTy(DAG.getDataLayout()))));
4392+
DAG.getShiftAmountConstant(ExcessBits, NVT, dl)));
43964393
// Move high bits to the right position in Hi.
43974394
Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
43984395
Hi,
4399-
DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
4400-
TLI.getPointerTy(DAG.getDataLayout())));
4396+
DAG.getShiftAmountConstant(
4397+
NVT.getSizeInBits() - ExcessBits, NVT, dl));
44014398
}
44024399
}
44034400

@@ -5165,12 +5162,12 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
51655162
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
51665163
SDValue &Lo, SDValue &Hi) {
51675164
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
5165+
SDValue InOp = N->getOperand(0);
5166+
EVT InVT = InOp.getValueType();
51685167
SDLoc dl(N);
5169-
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
5170-
Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
5171-
N->getOperand(0),
5172-
DAG.getConstant(NVT.getSizeInBits(), dl,
5173-
TLI.getPointerTy(DAG.getDataLayout())));
5168+
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, InOp);
5169+
Hi = DAG.getNode(ISD::SRL, dl, InVT, InOp,
5170+
DAG.getShiftAmountConstant(NVT.getSizeInBits(), InVT, dl));
51745171
Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
51755172
}
51765173

@@ -5928,14 +5925,13 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
59285925

59295926
if (ExcessBits < NVT.getSizeInBits()) {
59305927
// Transfer high bits from the top of Lo to the bottom of Hi.
5931-
Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
5932-
DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
5933-
TLI.getPointerTy(DAG.getDataLayout())));
5928+
Hi = DAG.getNode(
5929+
ISD::SHL, dl, NVT, Hi,
5930+
DAG.getShiftAmountConstant(NVT.getSizeInBits() - ExcessBits, NVT, dl));
59345931
Hi = DAG.getNode(
59355932
ISD::OR, dl, NVT, Hi,
59365933
DAG.getNode(ISD::SRL, dl, NVT, Lo,
5937-
DAG.getConstant(ExcessBits, dl,
5938-
TLI.getPointerTy(DAG.getDataLayout()))));
5934+
DAG.getShiftAmountConstant(ExcessBits, NVT, dl)));
59395935
}
59405936

59415937
// Store both the high bits and maybe some of the low bits.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1001,11 +1001,10 @@ SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
10011001
EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
10021002
LVT.getSizeInBits() + HVT.getSizeInBits());
10031003

1004-
EVT ShiftAmtVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
10051004
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
10061005
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
10071006
Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
1008-
DAG.getConstant(LVT.getSizeInBits(), dlHi, ShiftAmtVT));
1007+
DAG.getShiftAmountConstant(LVT.getSizeInBits(), NVT, dlHi));
10091008
return DAG.getNode(ISD::OR, dlHi, NVT, Lo, Hi);
10101009
}
10111010

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5945,10 +5945,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
59455945
// interesting bits will end up at the wrong place.
59465946
if (DAG.getDataLayout().isBigEndian()) {
59475947
unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
5948-
EVT ShiftAmtTy = TLI.getShiftAmountTy(NInVT, DAG.getDataLayout());
5949-
assert(ShiftAmt < WidenVT.getSizeInBits() && "Too large shift amount!");
59505948
NInOp = DAG.getNode(ISD::SHL, dl, NInVT, NInOp,
5951-
DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
5949+
DAG.getShiftAmountConstant(ShiftAmt, NInVT, dl));
59525950
}
59535951
return DAG.getNode(ISD::BITCAST, dl, WidenVT, NInOp);
59545952
}

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