Revert "Change DIO level in the middle of the (low) clock pulse"

This change was too hasty: While now there are nice delays between
CLK and DIO changes, there's no longer a delay between CLK rising
at the end of a bit, and CLK falling for the next bit. That doesn't
work.

This reverts commit 5b75875.

Author: jannic

src/lib.rs

@@ -125,12 +125,12 @@ where
 
     fn send_bit_and_delay(&mut self, value: Bit) -> Res<E> {
         self.clk.set_low()?;
-        self.delay();
         if let Bit::ONE = value {
             self.dio.set_high()?;
         } else {
             self.dio.set_low()?;
         }
+        self.delay();
         self.clk.set_high()?;
         self.delay();