From a654d3cecedae70a73db4ef4a0e64828cbbadd40 Mon Sep 17 00:00:00 2001
From: Jan Niehusmann <jan@gondor.com>
Date: Tue, 5 Dec 2023 12:17:30 +0000
Subject: [PATCH 1/3] Make sure clock pulses have a defined length

Currently, clock pulses can be arbitrarily short, as the whole clock
delay is done after setting clk to low, setting the data bit, and
setting clk to high again. On fast processors, the clk pulse can become
too short to be recognized reliably, which may be the cause for
issue #5.

To fix that, split the delay in two equal halves, and do one of them
while the clock is low.

I duplicated all other calls to delay() to keep the delay lengths
stable. This might not be necessary, but shouldn't hurt either.
---
 src/lib.rs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/lib.rs b/src/lib.rs
index 66be25f..a3de717 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -101,6 +101,7 @@ where
                 return Ok(());
             }
             self.delay();
+            self.delay();
         }
 
         Err(Error::Ack)
@@ -117,6 +118,7 @@ where
         self.send_bit_and_delay(Bit::ZERO)?;
         self.dio.set_high()?;
         self.delay();
+        self.delay();
 
         Ok(())
     }
@@ -128,6 +130,7 @@ where
         } else {
             self.dio.set_low()?;
         }
+        self.delay();
         self.clk.set_high()?;
         self.delay();
 
@@ -141,7 +144,7 @@ where
 
 const MAX_FREQ_KHZ: u16 = 500;
 const USECS_IN_MSEC: u16 = 1_000;
-const DELAY_USECS: u16 = USECS_IN_MSEC / MAX_FREQ_KHZ;
+const DELAY_USECS: u16 = USECS_IN_MSEC.div_ceil(MAX_FREQ_KHZ * 2);
 
 const ADDRESS_AUTO_INCREMENT_1_MODE: u8 = 0x40;
 

From 5b7587520afb90110291dd839893ba38e0742ab9 Mon Sep 17 00:00:00 2001
From: Jan Niehusmann <jan@gondor.com>
Date: Fri, 8 Dec 2023 06:33:56 +0000
Subject: [PATCH 2/3] Change DIO level in the middle of the (low) clock pulse

---
 src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib.rs b/src/lib.rs
index a3de717..15cedd7 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -125,12 +125,12 @@ where
 
     fn send_bit_and_delay(&mut self, value: Bit) -> Res<E> {
         self.clk.set_low()?;
+        self.delay();
         if let Bit::ONE = value {
             self.dio.set_high()?;
         } else {
             self.dio.set_low()?;
         }
-        self.delay();
         self.clk.set_high()?;
         self.delay();
 

From 25e5e7e72ed7eed2e18d40db8664b355b677d76c Mon Sep 17 00:00:00 2001
From: Jan Niehusmann <jan@gondor.com>
Date: Fri, 8 Dec 2023 07:05:03 +0000
Subject: [PATCH 3/3] Revert "Change DIO level in the middle of the (low) clock
 pulse"

This change was too hasty: While now there are nice delays between
CLK and DIO changes, there's no longer a delay between CLK rising
at the end of a bit, and CLK falling for the next bit. That doesn't
work.

This reverts commit 5b7587520afb90110291dd839893ba38e0742ab9.
---
 src/lib.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/lib.rs b/src/lib.rs
index 15cedd7..a3de717 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -125,12 +125,12 @@ where
 
     fn send_bit_and_delay(&mut self, value: Bit) -> Res<E> {
         self.clk.set_low()?;
-        self.delay();
         if let Bit::ONE = value {
             self.dio.set_high()?;
         } else {
             self.dio.set_low()?;
         }
+        self.delay();
         self.clk.set_high()?;
         self.delay();