Tracking issue for gates #41
Description
This is a tracking issue for gates and their implementation status:
This includes both simulation implementation as well as visual implementation.
If a component requires it's own discussion that issue will be linked next to the component in this list.
Prio 1:
- Constant
- Input/output pins
- Buffer
- Not gate
- And gate
- Nand gate
- Or gate
- Nor gate
- Xor gate
- Xnor gate
- Tri-state buffer
- Tri-state inverter
- D/T/JK/SR Flip Flop
- Probe
- Clock
- LED
- Button
Prio 2:
- Register
- Shift register
- Counter
- Imply gate
- Nimply gate
Prio 3:
- Mux
- DeMux
- ROM
- RAM
- Splitter
- User-defined components
- Tunnel