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kbrunham-intelkbrunham-intel
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Removed unneeded SDCs
1 parent 2e7c1d4 commit 68ccc55

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-172
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2 files changed

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‎ref_designs/a10_pcie_devkit_cvp/auxiliary.sdc‎

Lines changed: 0 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -24,89 +24,3 @@ set_false_path -from {u_top|design_core|ddr4_status_bus|u_synch_fail|d[0]} -to {
2424
set_false_path -from {u_top|design_core|ddr4_status_bus|u_synch_success|d[0]} -to {u_top|design_core|ddr4_status_bus|u_synch_success|c[0]}
2525
set_clock_groups -asynchronous -group [get_clocks {u_top|ddr4_emif|ddr4_ctlr_emif_0_core_usr_clk}] -group [get_clocks {u_top|design_core|top_iopll|top_iopll_0|outclk_250mhz}]
2626

27-
set tx_ser_clk [get_clocks *tx_serial_clk]
28-
29-
if {[get_collection_size $tx_ser_clk] != 1} {
30-
puts "Error: tx_serial_clk does not exist or more than 1 tx_serial_clk"
31-
puts "Error: make sure derive_pll_clocks -create_base_clocks is run"
32-
} else {
33-
set clk_prefix [join [lrange [split [query_collection $tx_ser_clk] {|}] 0 {end-1}] {|}]
34-
}
35-
36-
set byte_ser_clk_pins [get_pins -compatibility_mode *|byte_deserializer_pcs_clk_div_by_4_txclk_reg]
37-
38-
if {[get_collection_size $byte_ser_clk_pins] < 1} {
39-
puts "Error: possibly a timing model issue"
40-
} else {
41-
set byte_ser_clk_pin0 [lindex [query_collection $byte_ser_clk_pins] 0]
42-
set hip_presence [regexp {(^.*)\|altpcie_a10_hip_pipen1b} $byte_ser_clk_pin0 all clk_pin_prefix]
43-
}
44-
45-
set phy_lane0_size 0 ;#Gen 3x1
46-
set phy_lane1_size 0 ;#Gen 3x2
47-
set phy_lane3_size 0 ;#Gen 3x4
48-
set phy_lane7_size 0 ;#Gen 3x8
49-
50-
set phy_lane0 [get_registers {*phy_g3x*|g_xcvr_native_insts[0]*}]
51-
set phy_lane1 [get_registers {*phy_g3x*|g_xcvr_native_insts[1]*}]
52-
set phy_lane3 [get_registers {*phy_g3x*|g_xcvr_native_insts[3]*}]
53-
set phy_lane7 [get_registers {*phy_g3x*|g_xcvr_native_insts[7]*}]
54-
55-
set phy_lane0_size [get_collection_size $phy_lane0]
56-
set phy_lane1_size [get_collection_size $phy_lane1]
57-
set phy_lane3_size [get_collection_size $phy_lane3]
58-
set phy_lane7_size [get_collection_size $phy_lane7]
59-
60-
if {$phy_lane7_size > 0} {
61-
set stop 8
62-
} elseif {$phy_lane3_size > 0} {
63-
set stop 4
64-
} elseif {$phy_lane1_size > 0} {
65-
set stop 2
66-
} elseif {$phy_lane0_size > 0} {
67-
set stop 1
68-
} else {
69-
set stop 0
70-
}
71-
72-
for {set i 0} {$i != $stop} {incr i} {
73-
create_generated_clock -divide_by 1 \
74-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_2_txclk_reg" \
75-
-name "$clk_prefix|rx_pcs_clk_div_by_4[$i]" \
76-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by2_1" ;# target
77-
78-
create_generated_clock -multiply_by 1 -divide_by 1 \
79-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_2_reg" \
80-
-name "$clk_prefix|tx_pcs_clk_div_by_4[$i]" \
81-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by2_1" ;# target
82-
}
83-
84-
#Constraint for Gen 3x2 and up
85-
if {$phy_lane1_size > 0} {
86-
create_generated_clock -multiply_by 1 -divide_by 5 \
87-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_*" \
88-
-master_clock "$clk_prefix|tx_serial_clk" \
89-
-name "$clk_prefix|tx_bonding_clocks[0]" \
90-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]"
91-
92-
}
93-
94-
set rx_clkouts [list]
95-
for {set i 0} {$i != $stop} {incr i} {
96-
97-
create_generated_clock -multiply_by 1 \
98-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg" \
99-
-master_clock "$clk_prefix|tx_bonding_clocks[0]" \
100-
-name "$clk_prefix|g_xcvr_native_insts[$i]|rx_clk" \
101-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1" ;# target
102-
103-
create_generated_clock -multiply_by 1 \
104-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg" \
105-
-master_clock "$clk_prefix|tx_bonding_clocks[0]" \
106-
-name "$clk_prefix|g_xcvr_native_insts[$i]|rx_clkout" \
107-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out"
108-
109-
set_clock_groups -exclusive -group "$clk_prefix|tx_bonding_clocks[0]" -group "$clk_prefix|g_xcvr_native_insts[$i]|rx_clkout"
110-
set_clock_groups -exclusive -group "$clk_prefix|tx_bonding_clocks[0]" -group "$clk_prefix|rx_pcs_clk_div_by_4[$i]"
111-
}
112-

‎ref_designs/a10_pcie_devkit_cvp_hpr/auxiliary.sdc‎

Lines changed: 0 additions & 86 deletions
Original file line numberDiff line numberDiff line change
@@ -24,89 +24,3 @@ set_false_path -from {u_top|design_core|ddr4_status_bus|u_synch_fail|d[0]} -to {
2424
set_false_path -from {u_top|design_core|ddr4_status_bus|u_synch_success|d[0]} -to {u_top|design_core|ddr4_status_bus|u_synch_success|c[0]}
2525
set_clock_groups -asynchronous -group [get_clocks {u_top|ddr4_emif|ddr4_ctlr_emif_0_core_usr_clk}] -group [get_clocks {u_top|design_core|top_iopll|top_iopll_0|outclk_250mhz}]
2626

27-
set tx_ser_clk [get_clocks *tx_serial_clk]
28-
29-
if {[get_collection_size $tx_ser_clk] != 1} {
30-
puts "Error: tx_serial_clk does not exist or more than 1 tx_serial_clk"
31-
puts "Error: make sure derive_pll_clocks -create_base_clocks is run"
32-
} else {
33-
set clk_prefix [join [lrange [split [query_collection $tx_ser_clk] {|}] 0 {end-1}] {|}]
34-
}
35-
36-
set byte_ser_clk_pins [get_pins -compatibility_mode *|byte_deserializer_pcs_clk_div_by_4_txclk_reg]
37-
38-
if {[get_collection_size $byte_ser_clk_pins] < 1} {
39-
puts "Error: possibly a timing model issue"
40-
} else {
41-
set byte_ser_clk_pin0 [lindex [query_collection $byte_ser_clk_pins] 0]
42-
set hip_presence [regexp {(^.*)\|altpcie_a10_hip_pipen1b} $byte_ser_clk_pin0 all clk_pin_prefix]
43-
}
44-
45-
set phy_lane0_size 0 ;#Gen 3x1
46-
set phy_lane1_size 0 ;#Gen 3x2
47-
set phy_lane3_size 0 ;#Gen 3x4
48-
set phy_lane7_size 0 ;#Gen 3x8
49-
50-
set phy_lane0 [get_registers {*phy_g3x*|g_xcvr_native_insts[0]*}]
51-
set phy_lane1 [get_registers {*phy_g3x*|g_xcvr_native_insts[1]*}]
52-
set phy_lane3 [get_registers {*phy_g3x*|g_xcvr_native_insts[3]*}]
53-
set phy_lane7 [get_registers {*phy_g3x*|g_xcvr_native_insts[7]*}]
54-
55-
set phy_lane0_size [get_collection_size $phy_lane0]
56-
set phy_lane1_size [get_collection_size $phy_lane1]
57-
set phy_lane3_size [get_collection_size $phy_lane3]
58-
set phy_lane7_size [get_collection_size $phy_lane7]
59-
60-
if {$phy_lane7_size > 0} {
61-
set stop 8
62-
} elseif {$phy_lane3_size > 0} {
63-
set stop 4
64-
} elseif {$phy_lane1_size > 0} {
65-
set stop 2
66-
} elseif {$phy_lane0_size > 0} {
67-
set stop 1
68-
} else {
69-
set stop 0
70-
}
71-
72-
for {set i 0} {$i != $stop} {incr i} {
73-
create_generated_clock -divide_by 1 \
74-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_2_txclk_reg" \
75-
-name "$clk_prefix|rx_pcs_clk_div_by_4[$i]" \
76-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by2_1" ;# target
77-
78-
create_generated_clock -multiply_by 1 -divide_by 1 \
79-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|byte_serializer_pcs_clk_div_by_2_reg" \
80-
-name "$clk_prefix|tx_pcs_clk_div_by_4[$i]" \
81-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_tx_pcs.inst_twentynm_hssi_8g_tx_pcs|sta_tx_clk2_by2_1" ;# target
82-
}
83-
84-
#Constraint for Gen 3x2 and up
85-
if {$phy_lane1_size > 0} {
86-
create_generated_clock -multiply_by 1 -divide_by 5 \
87-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|clk_fpll_*" \
88-
-master_clock "$clk_prefix|tx_serial_clk" \
89-
-name "$clk_prefix|tx_bonding_clocks[0]" \
90-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_pll.g_pll_g3n.lcpll_g3xn|lcpll_g3xn|a10_xcvr_atx_pll_inst|twentynm_hssi_pma_cgb_master_inst|cpulse_out_bus[0]"
91-
92-
}
93-
94-
set rx_clkouts [list]
95-
for {set i 0} {$i != $stop} {incr i} {
96-
97-
create_generated_clock -multiply_by 1 \
98-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pcs_clk_div_by_4_txclk_reg" \
99-
-master_clock "$clk_prefix|tx_bonding_clocks[0]" \
100-
-name "$clk_prefix|g_xcvr_native_insts[$i]|rx_clk" \
101-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1" ;# target
102-
103-
create_generated_clock -multiply_by 1 \
104-
-source "$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|byte_deserializer_pld_clk_div_by_4_txclk_reg" \
105-
-master_clock "$clk_prefix|tx_bonding_clocks[0]" \
106-
-name "$clk_prefix|g_xcvr_native_insts[$i]|rx_clkout" \
107-
"$clk_pin_prefix|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x*.phy_g3x*|phy_g3x*|g_xcvr_native_insts[$i].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs|sta_rx_clk2_by4_1_out"
108-
109-
set_clock_groups -exclusive -group "$clk_prefix|tx_bonding_clocks[0]" -group "$clk_prefix|g_xcvr_native_insts[$i]|rx_clkout"
110-
set_clock_groups -exclusive -group "$clk_prefix|tx_bonding_clocks[0]" -group "$clk_prefix|rx_pcs_clk_div_by_4[$i]"
111-
}
112-

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