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Updated printed messages used for DDR4 access in example host program
1 parent ea8f97b commit be77579

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2 files changed

+7
-11
lines changed

2 files changed

+7
-11
lines changed

ref_designs/a10_pcie_devkit_cvp/software/util/example_host_uio.c

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -408,9 +408,9 @@ static int do_basic_dsp_persona(struct test_handle *th,
408408
#define DDR4_BUSY_REGISTER PR_HOST_REGISTER_1
409409
#define DDR4_START_MASK 2
410410
#define DDR4_LOAD_SEED_MASK 1
411-
#define DDR4_ADDRESS_MAX 67108864
411+
#define DDR4_ADDRESS_MAX 1 << 25
412412
#define DDR4_CAL_MASK 3
413-
#define DDR4_CAL_OFFSET 0x10100
413+
#define DDR4_CAL_OFFSET 0x10010
414414
static int run_ddr4_address_sweep(struct test_handle *th, uint32_t base_address, uint32_t final_offset, uint32_t calibration, uint32_t verbose)
415415
{
416416
uint32_t data = 0;
@@ -453,27 +453,25 @@ static int do_ddr4_access_persona (struct test_handle *th, uint32_t seed, uint3
453453
calibration = 1;
454454

455455
VERBOSE_MESSAGE("\tDDR4 Calibration Check Successful\n");
456-
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Loading\n", seed);
457-
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Successfully loaded \n", seed);
458456
VERBOSE_MESSAGE("\tStarting Test cases\n");
459457

460458
for( i = 1; i <= number_of_runs; i++) {
461459
reset_pr_logic(th, verbose);
462460
printf("Beginning test %d of %d\n", i, number_of_runs);
463461
uint32_t rand_ready = 0;
464462
data = seed;
463+
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Loading\n", seed);
465464
(*th->write_u32)(th->arg, DDR4_SEED_ADDRESS, data);
466465
data = 0 | (1 << DDR4_LOAD_SEED_MASK);
467466
(*th->write_u32)(th->arg, PR_CONTROL_REGISTER, data);
468-
data = 0 | (1 << DDR4_LOAD_SEED_MASK);
469-
(*th->write_u32)(th->arg, PR_CONTROL_REGISTER, data);
470467
data = 0;
471468
(*th->read_u32)(th->arg, DDR4_SEED_ADDRESS, &data);
472469

473470
if(data != seed) {
474471
printf("ERROR: failed to load seed \n");
475472
exit(EXIT_FAILURE);
476473
}
474+
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Successfully loaded \n", seed);
477475

478476
while(!rand_ready) {
479477
base_address = rand();

ref_designs/a10_pcie_devkit_cvp_hpr/software/util/example_host_uio.c

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -457,27 +457,25 @@ static int do_ddr4_access_persona (struct test_handle *th, uint32_t seed, uint3
457457
calibration = 1;
458458

459459
VERBOSE_MESSAGE("\tDDR4 Calibration Check Successful\n");
460-
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Loading\n", seed);
461-
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Successfully loaded \n", seed);
462460
VERBOSE_MESSAGE("\tStarting Test cases\n");
463461

464462
for( i = 1; i <= number_of_runs; i++) {
465463
reset_pr_logic(th, verbose, region_offset);
466464
printf("Beginning test %d of %d\n", i, number_of_runs);
467465
uint32_t rand_ready = 0;
466+
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Loading\n", seed);
468467
data = seed;
469468
(*th->write_u32)(th->arg, (DDR4_SEED_ADDRESS + region_offset), data);
470469
data = 0 | (1 << DDR4_LOAD_SEED_MASK);
471470
(*th->write_u32)(th->arg, (PR_CONTROL_REGISTER + region_offset), data);
472-
data = 0 | (1 << DDR4_LOAD_SEED_MASK);
473-
(*th->write_u32)(th->arg, (PR_CONTROL_REGISTER + region_offset), data);
474-
data = 0;
471+
data=0;
475472
(*th->read_u32)(th->arg, (DDR4_SEED_ADDRESS + region_offset), &data);
476473

477474
if(data != seed) {
478475
printf("ERROR: failed to load seed \n");
479476
exit(EXIT_FAILURE);
480477
}
478+
VERBOSE_MESSAGE("\tDDR4 lfsr Seed 0x%08X Successfully loaded \n", seed);
481479

482480
while(!rand_ready) {
483481
base_address = rand();

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