vcs sim fail

[Jiahua-Gong]

Parsing design file 'design_top_sim_cfg_pkg.sv'
Parsing design file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_pkg.sv'
Parsing included file '/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Back to file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_pkg.sv'.
Parsing included file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/altr_cmn/altr_cmn_macros.sv'.
Parsing included file '/opt/synopsys/vcs-mx/O-2018.09-SP2/etc/uvm-1.2/uvm_macros.svh'.
Back to file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/altr_cmn/altr_cmn_macros.sv'.
Back to file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_pkg.sv'.
Parsing included file '/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_response_seq_item.sv'.

Error-[SV-EEM-SRE] Scope resolution error
/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_response_seq_item.sv, 59
avmm_pkg, "avalon_mm_pkg::Request_t"
  Target for scope resolution operator does not exist. Token 'avalon_mm_pkg' 
  is not a class/package.  Originating module 'avmm_pkg'.
  Check that class or package exists with referred token as the name.


Error-[SE] Syntax error
  Following verilog source has syntax error :
  "/home/jiahua/Desktop/fpga-partial-reconfig/verification/vkits/avmm/avmm_response_seq_item.sv",
  59: token is 'Request_t'
     avalon_mm_pkg::Request_t request;

I can't find avalon_mm_pkg.sv