Add CXL.CM 256B Flit mode support for CXL3+ compliant devices for SKID/Containment Setup and Key Refresh flows.

[kumars3-creator]

In CXL3+ specs
Enhancements in these sections of CXL Spec, require a enhancement in validator also
Currently in TEEIO validator we are not checking if CXL is operating in 68B FLIT mode or 256B FLIT Mode,
so based on these we need enhancements to the flow for SKID/Containment mode setup and potentially in key refresh flow also.

8.2.4.22 CXL IDE Capability Structure

8.2.4.22.6 Truncation Transmit Delay Capability (Offset 14h)

Rx Min Truncation Transmit Delay2: Number of IDE.Idle flits
the receiver needs before it is ready to receive protocol flits
after a Truncated MAC is received when operating in 256B Flit
mode. The Tx Truncation Transmit Delay (see
Section 8.2.4.22.8) field of the transmitter is configured, by
software, to block transmission of protocol flits for at

8.2.4.22.7 Key Refresh Time Control (Offset 18h)

Tx Key Refresh Time: For 68B Flit mode, this register
represents the minimum number of flits that the transmitter
needs to block transmission of protocol flits after IDE.Start has
been sent. For 256B Flit mode, this register represents the
minimum number of flits that the transmitter needs to block
transmission of protocol flits after IDE.Start has been sent or
after IDE.Stop has been sent. Used when switching keys (see
Section 11.3.7) or gracefully terminating IDE (256B Flit mode
only, see Section 11.3.10).
The default value of this field is 0.

8.2.4.22.9 Key Refresh Time Capability2 (Offset 20h)

Rx Min Key Refresh Time2: Number of IDE.Idle flits the
receiver needs to be ready to receive protocol flits after either
IDE.Start or IDE.Stop is received when operating in 256B Flit
mode. Tx Key Refresh Time (see Section 8.2.4.22.7) field of the
transmitter is configured by System Software to block
transmission of protocol flits for at least this duration when
switching keys (see Section 11.3.7) or terminating IDE (see
Section 11.3.10) when the link is operating in 256B Flit mode.

[gaojiaqi7]

I checked the CXL and PCIe specs but couldn’t find a way to detect which flit mode (68/256) the link is using; this information only appears in the host root port documentation. I may need to spend more time investigating the CXL spec in detail.