Additional output formats

[Muxianesty]

Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:

• Unscheduled DFCIR Closed with Uncheduled DFCIR output format #25 and Unscheduled DFCIR & SystemVerilog output path options revamp #31.
• Scheduled FIRRTL Closed with Scheduled FIRRTL output format #26 and Scheduled FIRRTL output format; minor refactoring, config and codestyle fixes #40.
• VHDL Currently cannot be generated via CIRCT (VHDL output format #28). Removed from stage II of the plan.
• Verilog (?)
• .dot Closed with Dataflow graph .dot output format #27 and DOT output format #48.

[ssmolov]

I'd rather split different formats into different issues.

For now, DFCIR/FIRRTL are the most preferable ones, DOT is also can be helpful for self-debugging.

Concerning Verilog, it should be checked carefully. We can already generated it but treat as SystemVerilog because of predefined ".sv" extension of the output file.

As for VHDL, I'd recommend to look for MLIR/CIRCT extensions that are capable to provide it.

[Muxianesty]

I'd rather split different formats into different issues.

For now, DFCIR/FIRRTL are the most preferable ones, DOT is also can be helpful for self-debugging.

Concerning Verilog, it should be checked carefully. We can already generated it but treat as SystemVerilog because of predefined ".sv" extension of the output file.

As for VHDL, I'd recommend to look for MLIR/CIRCT extensions that are capable to provide it.

I agree with the proposal to make different issues for different formats.
About .sv - as far as I understand, the output extension is not hardcoded and you can choose any valid Unix path to a file with any valid extension.